CN114995832A

CN114995832A - Dynamic and static combined binary program translation method

Info

Publication number: CN114995832A
Application number: CN202210748606.8A
Authority: CN
Inventors: 罗杰; 丁传新; 陈伟业; 刘曜; 王�锋; 张乔; 刘鑫
Original assignee: Hunan Kampele Information Technology Co ltd
Current assignee: Hunan Kampele Information Technology Co ltd
Priority date: 2022-06-28
Filing date: 2022-06-28
Publication date: 2022-09-02
Anticipated expiration: 2042-06-28
Also published as: CN114995832B

Abstract

The invention discloses a dynamic and static combined binary program translation method, aiming at reducing the overhead of a translation process, improving the translation efficiency and improving the performance of a translated binary program. Constructing a dynamic and static combined binary translation system consisting of a source program analysis module, an instruction decoding module, an IRs optimization module, an HIR generation module, an IRt optimization module, a dynamic translation function insertion module and a target program generation module, and statically translating programs which can be translated by a static method in the binary program to generate a binary program corresponding to a target platform by mainly static binary translation; and for the instruction which cannot be translated through static translation, inserting a dynamic translation function into a binary program corresponding to a target platform generated after the static translation, and dynamically translating the instruction which cannot be translated through the static translation by adopting the dynamic translation function. The invention can reduce the overhead brought by translation and effectively improve the performance of binary programs.

Description

Dynamic and static combined binary program translation method

Technical Field

The invention relates to the technical field of binary program translation, in particular to a dynamic and static combined binary program translation method.

Background

A binary translator is a tool for translating a binary program corresponding to an instruction from one source platform (for example, x86) into a binary program capable of running on another target platform (for example, arm), that is, translating a binary program corresponding to one instruction system (for short, a source binary program) into a binary program corresponding to another instruction system (for short, a target binary program). Binary translation is divided into two translation methods, static binary translation and dynamic binary translation. For example, a C language compiling process on an x86 platform includes C language- > IR- > x86 binary, and to translate an x86 binary program (a source binary program) into a program (a target binary program) that can run on an arm, it is necessary to rollback the x86 binary program to IR (intermediate representation, i.e., an intermediate representation, which refers to an internal representation generated by a compiler after scanning a source program and represents semantic and syntactic structures of the source program, and each stage of the compiler performs analysis or optimization transformation on IR), and then converts the IR into an arm binary program.

The static binary translation is to translate before the binary program is executed, translate the binary program of the source platform (namely, the source binary program) into the binary program of the target platform (namely, the target binary program), and the static binary translation process and the program execution process are two mutually independent processes, so that the static binary translation can optimize the binary program by adopting various optimization means (such as control flow analysis, data flow analysis, common sub-expression deletion and instruction combination), and the like, thereby reducing code expansion caused by the binary program translation and improving the execution performance of the program on the target platform. However, since the jump branch cannot be predicted before actual execution, the static binary translation method cannot optimally process the indirect jump instruction. The dynamic binary translation is to translate by taking a basic block as a unit by adopting a strategy of translating a source binary program and executing the translation at the same time, and after one basic block of the source binary program is translated, the dynamic binary translator enters an execution state, so that the dynamic translation can solve an instruction which cannot be processed by static translation such as indirect jump. Because the dynamic binary translator adopts a strategy of executing while translating, namely the translation process and the execution process are in the same process, the translation time can influence the execution time of the program on the target platform. And it is difficult to take too many optimization means inside the translator, which can cause the target binary program code to swell, and the translation process lacks effective measures to reduce the code swelling. This will result in a loss of performance of the source binary program on the target platform, ultimately resulting in a poor user experience (assuming that binary translation is from x86 to arm. runtime is t1 on x86 platform, runtime is t2 on arm platform after static translation, time of dynamic translation + runtime is t3. on arm and then efficiency of static translation is t1/t2, efficiency of dynamic translation is t2/t 3).

In modern processors, indirect jump is a common type of instruction, and indirect jump exists in x86 processors on the pc end, arm processors on the embedded end and the like. In an indirect jump instruction, the jump target (i.e., the jump target address) is stored in a register or memory. Because code expansion is introduced during binary translation, the address of a target binary program code obtained by translation is difficult to correspond to the address of an original binary program one by one, so that the indirect jump address is difficult to analyze and clarify during static translation, and the static translation cannot process an indirect jump instruction, namely the traditional static translation method is not suitable for binary program translation containing the indirect jump instruction. The dynamic binary translation can obtain the address of the indirect jump in the original binary program during dynamic execution to realize the translation of the indirect jump instruction, but if the traditional dynamic binary translation method is directly adopted, the problems of low translation efficiency, poor user experience and the like can be caused because the translation process lacks effective measures to reduce code expansion.

The Chinese patent application (publication number CN111625279A) discloses a dynamic and static fusion binary translation method and system based on a dynamic link library, the scheme divides a program by taking a function as a unit, and if the function is a third-party library function, the program is executed in a local library replacement mode; if the function has an indirect jump branch instruction, the function is placed in a dynamic translator for translation execution, if the indirect jump instruction does not exist, the function is statically translated by taking a basic block as a unit, relocation information after translation of the function is recorded, and a function relocation information table is generated; and generating a dynamic link library in the static translation process, collecting relocation information of the function after the static translation, and guiding the execution of the dynamic translator. However, the above scheme is only suitable for translation by using a binary program with a dynamic link, is not suitable for translation by using a binary program without a dynamic link, has a limited application range, places a function with an indirect jump instruction in a dynamic translator for dynamic translation, and still executes static translation and dynamic translation independently, so that the translation efficiency is still not high.

Chinese patent application (publication No. CN101452396A) discloses a dynamic binary translation method combined with static optimization, which collects rich subdivision information by inserting a probe instruction into a translated binary code and performing a first execution. And storing the subdivision information and the translated target code into a file when the program runs, performing various optimizations on the translated target binary code in a static period by using the stored subdivision information, and directly loading the optimized target codes in the later running of the program. However, in the scheme, a detection instruction needs to be inserted into the translated binary code, and the execution is performed again to collect the runtime information of the target binary code to guide the static optimization, so that not only is the implementation operation complex, but also the translation efficiency is reduced, and the translation implementation overhead is increased.

The Chinese patent application (publication number CN1716202A) discloses a processing method and a device for static information incompleteness in dynamic and static combined binary translation, the scheme selects some special basic blocks from static translatable codes as entries, a dynamic translation executor performs instant translation, when the entries reserved by the static translation are met, the codes of the static translation are transferred again, and finally a binary program of a target platform is generated. However, the scheme realizes translation through repeated and continuous static translation and dynamic alternate execution, the translation efficiency is greatly reduced in the continuous and alternate translation process, and the translation implementation cost is greatly increased because guidance must be carried out by depending on profile configuration information in the alternate translation process.

Although all of the above three binary program translation methods attempt to combine static translation and dynamic translation, either the application range is limited, an additional execution process is required, or the implementation process is complicated and the translation efficiency is reduced. How to provide a dynamic and static combined binary program translation method, which not only can give full play to the advantages of static translation and dynamic translation strategies, but also can improve the translation efficiency and reduce the translation overhead is still a technical problem which is of great concern to technical personnel in the field.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems of the existing dynamic and static combined binary translation method, the dynamic and static combined binary program translation method which is simple in implementation method, high in translation efficiency and low in cost is provided, the advantages that static translation codes are small in expansion, dynamic translation can solve indirect jump and the like, and instructions cannot be processed by static translation are fully played, so that the cost in the translation process is reduced, the translation efficiency is improved, and the performance of the translated binary program is improved.

In order to solve the technical problem, the invention provides a dynamic and static combined binary program translation method, which mainly adopts a static binary translation strategy, performs static translation and deep optimization on program segments which can be translated by adopting a static method in a binary program, and generates a binary program corresponding to a target platform; and for the instruction which cannot be translated through static translation, inserting a dynamic translation function into a binary program corresponding to a target platform generated after the static translation, and dynamically translating the instruction which cannot be translated through the static translation by adopting the dynamic translation function. By adopting the translation strategy of taking static translation as a main part and dynamic translation as an auxiliary part, the overhead brought by the translation process is reduced, and the performance of the binary program is effectively improved.

The technical scheme of the invention is as follows:

the method comprises the following steps of constructing a dynamic and static combined binary translation system, wherein the system comprises a source program analysis module, an instruction decoding module, an IRs (intermediate representation related to a source platform) optimization module, an HIR (High-level intermediate representation, also belonging to intermediate representation unrelated to the source platform) generation module, an IRt (intermediate representation related to a target platform) generation module, an IRt optimization module, a dynamic translation function insertion module and a target program generation module. The source program analysis module reads and identifies a source platform binary program input by a user to obtain a code segment, a data segment and a symbol table, constructs an address mapping table, translates the data segment to obtain a translated data segment, sends the symbol table and the code segment to the instruction decoding module, sends the address mapping table to the IRs optimization module, sends the symbol table to the IRt optimization module and the dynamic translation function insertion module, and sends the translated data segment to the target program generation module; the instruction decoding module decodes the code segments received from the source program analysis module, generates Intermediate Representations (IRs) related to a source platform, and sends the IRs to the IRs optimization module; the IRs optimization module constructs an address mapping table and a control flow diagram containing a basic block list, sends the address mapping table and the control flow diagram containing the basic block list to the IRt optimization module, sends the address mapping table containing the basic block list to the target program generation module, optimizes the IRs received from the instruction decoding module to obtain optimized IRs, and sends the optimized IRs to the HIR generation module; the HIR generation module converts the optimized IRs received from the IRs optimization module to obtain a source platform-independent intermediate representation HIR, and sends the HIR to the IRt generation module; the IRt generation module analyzes and converts the HIR received from the HIR generation module, generates an intermediate representation (IRt) related to a target platform, and sends the IRt to the IRt optimization module; the IRt optimization module receives an address mapping table containing a basic block list from the IRs optimization module, receives the IRt from the IRt generation module, optimizes the IRt to obtain the optimized IRt, and sends the optimized IRt to the dynamic translation function insertion module; the dynamic translation function inserting module receives a symbol table from the source program analyzing module, receives the optimized IRt from the IRt optimizing module, and inserts a jump target label into the symbol table; analyzing the optimized IRt, marking the optimized IRt, inserting a dynamic translation function to obtain the optimized IRt with the inserted dynamic translation function, sending the optimized IRt with the inserted dynamic translation function to a target program generation module, and sending a symbol table with an inserted jump target label to the target program generation module; and the target program generation module receives the optimized IRt and the address mapping table into which the dynamic translation function is inserted from the dynamic translation function insertion module, and generates a final target platform binary program and the address mapping table.

And secondly, reading a source platform binary program input by a user through a source program analysis module, identifying the source platform binary program into a code segment, a data segment and a symbol table, constructing an address mapping table, and adding a function address and a variable address in the address mapping table. The method comprises the following steps:

2.1 the source program analysis module reads the source platform binary program input by the user, and identifies the source platform binary program into a code segment (the content is an instruction), a data segment (the content is data), and a symbol table (the content is a function name, a variable name and their addresses in the source platform binary program) according to the format of the source platform binary program.

2.2, an address mapping table is constructed, the address mapping table is used for storing corresponding address information of functions and variables in a binary program of a source platform, and the method comprises the following steps: and adding the function name and the variable name in the symbol table and the address of the function name and the variable name in the source platform binary program to the address mapping table. The address mapping table consists of M + N table entries, where M is the number of functions in the source platform binary program, N is the number of variables in the source platform binary program, and each table entry includes 2 fields, namely a function name and a function start address (the start address of a function in the source platform binary program), or a variable name and a variable address (the address of a variable in the source platform binary program).

2.3 according to the source platform and the target platform size end have difference to translate the source platform binary program data segment, get the translated data segment, the method is: if the size end modes of the source platform and the target platform are not different, the whole data segment is completely copied to be used as the data segment of the final target binary program; if the source platform and the target platform have opposite big-end and small-end modes, the data segment is converted into a big end and a small end, the sequence of high and low bits of data is exchanged under the condition that the original attributes (the number of bytes occupied by the data and the actual value of the data) of the data segment are not changed, and the data segment is adjusted to be suitable for the data organization mode of the target platform. The data organization mode comprises a big-end mode and a small-end mode, wherein the big-end mode means that high bytes of data are stored in a low address of the memory, low bytes of data are stored in a high address of the memory, the addresses are increased from small to big, and the data are released from a high bit to a low bit; the small end mode is opposite to the large end mode. The conversion of the big end and the small end is to exchange the sequence of the high order and the low order of the data according to the definition of the big end and the small end.

2.4 sending the symbol table and the code segment to an instruction decoding module, and sending the translated data segment to a target program generating module; and sending the address mapping table to an IRs optimization module, and sending the symbol table to an IRt optimization module and a dynamic translation function insertion module.

Thirdly, the instruction decoding module receives the symbol table and the code segment from the source program analyzing module, translates the code segment into intermediate representation IRs related to the source platform, and sends the IRs to the IRs optimizing module, and the method is as follows:

3.1 making variable m ═ 1;

3.2 obtain the start address of the mth function from the symbol table, traverse each instruction of the mth function, decode each instruction, convert the instruction into the intermediate representation form related to the source platform (i.e. restore the binary code of the source platform into IRs, which is the reverse process of encoding). In this process, each source instruction in the code segment corresponds to one or more IRs: if the instruction is an operation instruction (such as common addition, subtraction, multiplication, division and shift), one instruction corresponds to one IRs; IF the instruction is a special instruction (such as a comparison instruction), the execution OF the instruction can cause the change OF flag bits (such as operation result flag bits reflecting operation results, such as a carry flag CF, a parity flag PF, an auxiliary carry flag AF, a sign flag SF, an overflow flag OF, a zero flag ZF, state control flag bits for controlling CPU operation, such as a tracking flag TF, an interruption allowance flag IF, a direction flag DF and the like), and one instruction corresponds to a plurality OF IRs; if the execution of an instruction depends on a flag bit (e.g., a jump instruction), then an instruction corresponds to multiple IRs.

3.3, if M is equal to M +1, rotating to 3.2; and if M is greater than M, sending the intermediate representation (namely IRs) related to the source platform obtained by translation to an IRs optimization module, and turning to the fourth step.

Fourthly, the IRs optimization module receives IRs from the instruction decoding module, receives an address mapping table from the source program analysis module, optimizes the IRs to obtain optimized IRs, and modifies the address mapping table to obtain an address mapping table containing a basic block list; constructing a control flow graph; and sending the optimized IRs to an HIR generation module, sending an address mapping table containing a basic block list and a control flow map to an IRt optimization module, and sending the address mapping table containing the basic block list to a dynamic translation function insertion module. The method comprises the following steps:

4.1 basic block segmentation is carried out on IRs, and an address mapping table is modified, wherein the method comprises the following steps: taking a function entry instruction in the IRs, a first instruction at a jump target address of the jump instruction, the jump instruction and a next instruction of the function call instruction as an entry of the basic block; and taking a jump instruction, a function call instruction and a program return instruction as the exits of the basic blocks. Meanwhile, the address of the first instruction of the basic block in the source platform binary program is added into an address mapping table, and if Q basic blocks exist, Q basic block table entries (the Q basic block table entries are called basic block lists) are added into the address mapping table, wherein each basic block table entry comprises two fields of a basic block serial number and a basic block address;

4.2, traversing the basic block list in the address mapping table obtained in the step 4.1, and finding out the parent node and the child node corresponding to each basic block in the basic block list, namely the predecessor and the successor of each basic block. Forming a control flow diagram by all basic blocks in the same function according to the relationship between a precursor and a successor; the M functions have M control flow graphs. And sending the M control flow graphs to an IRt optimization module.

4.3 perform data flow analysis on the M control flow graphs respectively, including active variable analysis, arrival fixed value analysis, constructing a reference-fixed value chain (abbreviated as ud chain, which is a list, for each reference of a variable, all fixed values arriving at the reference are in the ud chain) and a fixed value-reference chain (abbreviated as du chain, which is a set, for each definition, all reference sets that it can reach), calculating active information of each basic block register (i.e. active information of a variable.

And 4.4 deleting unused instructions for assigning the zone bits in the IRs according to the data flow information related to the zone bits in the data flow analysis result to obtain the optimized IRs. The method is beneficial to reducing code expansion generated in the translation process, so that the execution performance of the translated program is improved;

4.5 sending the optimized IRs to the HIR generation module, sending the address mapping table containing the basic block list and the control flow chart to the IRt optimization module, and sending the address mapping table containing the basic block list to the dynamic translation function insertion module.

Fifthly, the HIR generation module receives the optimized IRs from the IRs optimization module, converts the optimized IRs into an intermediate representation (HIR) irrelevant to a source platform, and sends the HIR to the IRt generation module. The method comprises the following steps:

and 5.1, converting information of all physical registers (namely all available hardware registers in an instruction set architecture of the source platform) related to the source platform in the optimized IRs into a global memory space, enabling the physical registers of each source platform to correspond to an independent global memory storage position, recording the attribute (the attribute refers to the use of the physical registers and comprises a stack pointer used for storing a function call return address and a parameter transfer function) of each physical register in the source platform, and adding the attribute of each physical register in the source platform into the primarily optimized IRs to obtain a source platform-independent intermediate representation (HIR).

And 5.2, sending the HIR to an IRt generation module, wherein Q physical registers are shared in the HIR, and Q is a positive integer.

Sixthly, the IRt generation module receives the HIR from the HIR generation module, converts the HIR into an intermediate representation related to the target platform, namely the IRt, and sends the IRt to the IRt optimization module, wherein the method comprises the following steps:

6.1 mapping partial registers of the source platform (i.e. registers that can be mapped to the target platform) to registers of the target platform by:

6.1.1 let variable q ═ 1;

6.1.2 reading the attribute of the q physical register in the HIR in the source platform, comparing the use rule of the target platform register and the register information, and mapping the q physical register of the source platform to the register of the target platform, wherein the method comprises the following steps: if the registers with the same function and usage are found in the target platform, replacing the qth physical register in the binary program of the source platform with the registers with the same function and usage, and turning to 6.1.3; if no register with the same function and usage is found in the target platform, directly turning to 6.1.3;

6.1.3, if Q is not more than Q, turning to 6.1.2; if Q > Q, the mapping of Q physical registers is completed, and an intermediate representation irrelevant to a target platform is obtained, wherein P items are shared in the intermediate representation irrelevant to the target platform and the intermediate representation irrelevant to the target platform is marked with a platform, and P is a positive integer and is converted to 6.2.

6.2 mapping the target platform independent intermediate representation to the target platform dependent intermediate representation IRt. The method comprises the following steps:

6.2.1 letting the variable p be 1;

6.2.2 operate with the p-th item target platform-independent intermediate representation as the current intermediate representation.

6.2.3 determining whether the current intermediate representation operation is a target platform independent operation that is directly supported by the target platform. If yes, the current intermediate representation operation does not need to be changed, and the current intermediate representation operation is directly used as intermediate representation related to the target platform, and the operation is switched to 6.2.5; otherwise, turning to 6.2.4;

6.2.4 determining whether the current intermediate representation operation is a target platform independent operation that can be implemented by combining with the target platform instruction. If so, converting the target platform irrelevant operation which can be realized by the target platform instruction through combination into the instruction combination corresponding to the target platform to obtain the target platform relevant intermediate representation IRt, and converting to 6.2.6; otherwise, go to 6.2.5;

6.2.5 inserting function call instruction into the intermediate representation related to the target platform at this time, and implementing the function of the current intermediate representation operation in the form of calling the library function in the target platform with the same function as the current intermediate representation operation, turning to 6.2.6.

6.2.6 changing P to P +1, if P is less than or equal to P, changing to 6.2.2; if P > P, the conversion from the target platform irrelevant intermediate representation to the target platform relevant intermediate representation is completed, the target platform relevant intermediate representation IRt is sent to the IRt optimization module, and the seventh step is executed.

Seventhly, the IRt optimization module receives an address mapping table and a control flow diagram which contain a basic block list from the IRs optimization module, receives the IRt from the IRt generation module, receives a symbol table from the source program analysis module, and optimizes the IRt to obtain the optimized IRt, wherein the method comprises the following steps:

7.1 according to the control flow diagram received from the IRs optimization module, carrying out arrival fixed value analysis and active variable analysis on the IRt received from the IRt generation module, and constructing a du chain and a ud chain by using the analysis result;

7.2, optimizing the IRt according to the results of the arrival fixed value analysis and the active variable analysis. The method comprises the following steps:

7.2.1 traversing the instruction sequence in the IRt, folding the constant for the calculation of the constant, and reducing the number of the calculated instructions;

7.2.2 traversing the instruction sequence in the IRt, and performing register copy propagation optimization aiming at a target register in the register copy instruction to reduce register shifting operation;

7.2.3 traversing the function call instruction in the IRt, reading symbol table information, identifying whether the called function is a library function, if the called function is the library function, converting the call of the library function of the source platform into the call of the library function of the target platform, and simultaneously converting the parameter transfer rule of the source platform into the parameter transfer rule of the target platform, and converting 7.2.4; if not, go directly to 7.2.4;

7.2.4 traversing the instruction sequence in the IRt, replacing the corresponding instruction in the IRt with an instruction with higher efficiency of the target platform (i.e. fewer bytes than the instruction of the source platform, faster execution speed, higher pipeline throughput, etc., for example, an operation realized by several consecutive instructions of the ARM platform, which can be realized by one instruction of the X86 platform, which is considered more efficient by the field as the equivalent instruction on the X86 platform);

7.2.5 register allocation is carried out on temporary variables in IRt, a circulation area is identified, register allocation is carried out on the temporary variables in the circulation area in priority, overflow of registers in circulation is reduced, access times to a memory are reduced, and execution efficiency of circulation is improved;

after the 5 kinds of optimization operations, an optimized intermediate representation related to the target platform, that is, an optimized IRt, is obtained.

7.3 sending the optimized IRt to the dynamic translation function insertion module.

Eighthly, the dynamic translation function insertion module receives a symbol table from the source program analysis module, receives the optimized IRt from the IRt optimization module, and inserts a jump target label into the symbol table; analyzing the optimized IRt, marking the optimized IRt and inserting a dynamic translation function to obtain the optimized IRt inserted with the dynamic translation function, sending the optimized IRt inserted with the dynamic translation function to a target program generation module, and sending a symbol table inserted with a jump target label to the target program generation module, wherein the method comprises the following steps:

8.1 the dynamic translation function insertion module receives the symbol table from the source program analysis module, receives the optimized IRt from the IRt optimization module, and translates the indirect jump instruction in the optimized IRt, the method is: traversing the optimized indirect jump instruction in the IRt, inserting a label (namely label) of the jump target into a symbol table for the jump instruction which can statically deduce the jump target, and modifying the indirect jump instruction into a direct jump instruction; for jump instructions that cannot statically infer jump targets, marking is performed in the optimized IRt. After this treatment, the labeled optimized IRt is obtained. The method for inserting the label of the jump target into the symbol table comprises the following steps: and S jump instructions capable of statically deducing jump targets are provided, S jump target table entries are added into the symbol table, and each table entry comprises a jump target sequence number and a label of the jump target.

8.2 the dynamic translation function insertion module constructs a stack for the dynamic translation function, and presses the parameters needed by the dynamic translation function into the stack, and saves the dynamic and static switching field. The dynamic translation function needs 4 parameters, which are the source binary program file name, the original jump target address, the address mapping table and the state of all registers of the source platform.

8.3 insert dynamic translation function in the marked optimized IRt; the essence of the method is that the program segments which can be translated by adopting a static method in the binary program are statically translated and optimized to generate the binary program corresponding to the target platform; for the instruction which cannot be translated through static translation, a dynamic translation function is inserted into a binary program corresponding to a target platform generated after the static translation, the instruction which cannot be translated through the static translation is dynamically translated through the dynamic translation function, and after the dynamic translation function is inserted into the IRt, the dynamic translation function starts to translate as long as the instruction which cannot be translated through the static translation is met, so that the effective combination of the dynamic translation and the static translation is realized. The execution flow of the inserted dynamic translation function is as follows:

8.3.1 save the static translation live, save all registers of the target platform, and then build the call stack. And pressing the path of the source binary program file, the path of the address mapping table and the original jump address into a call stack by taking the path of the source binary program file, the path of the address mapping table and the original jump address as parameters, and simultaneously storing the states of all registers of the source platform in the call stack according to a certain sequence.

And 8.3.2 the dynamic translation function reads the states of all registers of the source platform from the call stack, and maps the states to the memory space of the dynamic translation function to realize the switching of the states of the registers of the source platform.

8.3.3 store the target address returned by the dynamic translation function after the indirect jump instruction has been translated in the return value register (e.g., eax of x86) and push all register state of the source platform onto the call stack.

8.3.4 switching the execution flow to the static translation code space, the static code reads the state of all registers of the source platform from the call stack, and stores the state of the registers to the corresponding position of the static translation code space, completing the data interaction of the source platform in the dynamic and static translation process, then restoring the site, and restoring the registers of the target platform stored in the 8.3.1 call stack. And after the field recovery is finished, jumping to the corresponding position of the static code, and restarting to execute the static code.

And 8.4, sending the optimized IRt with the dynamic translation function inserted and the symbol table with the label of the jump target inserted to the target program generation module.

Ninthly, the target program generation module generates a binary program and an address mapping table corresponding to the target platform according to the optimized IRt inserted with the dynamic translation function;

9.1 the target program generation module receives the optimized IRt inserted with the dynamic translation function and the symbol table inserted with the jump target label from the dynamic translation function insertion module, receives the address mapping table containing the basic block list from the IRs optimization module, and receives the translated data segment from the source program analysis module.

9.2 traversing the optimized IRt inserted with the dynamic translation function, converting each intermediate representation into binary representations of the corresponding instructions of the target platform (the binary representations form a target binary program), and meanwhile accumulating the sizes of the generated instruction segments in the conversion process; for an instruction needing to access a data segment, inserting a relocation item into a symbol table inserted with a jump target tag (when a compiler encounters a reference to a symbol with an unknown final position, a relocation item is generated for the symbol with the unknown final position and used for indicating a linker how to modify the reference when the linker generates an executable file), obtaining a relocation table, and updating a function in a target binary program and a starting address of a basic block into an address mapping table containing a basic block list;

9.3 the target program generation module outputs the translated data segment received from the source program analysis module to the corresponding position of the target binary program according to the principle of first address alignment, compares the difference between the initial address of the generated data segment in the target binary program and the initial address in the source platform binary program, calculates the data segment offset,

9.4 according to the data segment offset calculated in step 9.3 and the relocation table generated in step 9.2, address adjustment is carried out on the data segment offset in the binary instruction, and the corresponding value in the symbol table inserted with the jump target label is updated. And obtaining a target platform binary program and an address mapping table.

Compared with the prior art, the invention can achieve the following technical effects:

1. according to the method, a source platform binary program is translated into intermediate representation related to a target platform in a dynamic and static combined binary program translation mode by mainly adopting a static translation method, a dynamic translation function is inserted into the optimized intermediate representation related to the target platform for the target instruction which cannot be translated by the static translation method, and the target instruction is translated by adopting the dynamic translation method through the mode. The binary program translation based on static and dynamic fusion not only can reduce translation overhead and improve translation efficiency, but also can improve the performance of the translated target platform binary program.

2. The invention realizes dynamic translation for instructions which can not be translated by static translation by inserting a dynamic translation function and simultaneously transmitting required parameters, integrates the dynamic translation process in a target platform binary program generated after translation, directly refers and executes the dynamic translation process from a source binary program, does not need a complex iteration flow, can complete the translation of the binary program by executing one-time static translation, and can greatly improve the efficiency of translation execution.

3. The method converts the binary program of the source platform into the intermediate representation by adopting a static translation method, and adopts various static optimization strategies when generating the IRs, the HIR and the IRt, thereby not only further improving the translation efficiency and reducing the translation cost, but also further improving the performance of the translated binary program on the target platform.

Drawings

FIG. 1 is a logic structure diagram of a dynamic and static binary translation system constructed in the first step of the present invention;

FIG. 2 is a general flow diagram of the dynamic and static combined binary translation system of the present invention.

Detailed Description

The technical scheme of the invention is explained in detail in the following by combining the attached drawings.

As shown in fig. 2, the present invention comprises the steps of:

firstly, a dynamic and static combined binary translation system is constructed, and as shown in fig. 1, the system is composed of a source program analysis module, an instruction decoding module, an IRs optimization module, an HIR generation module, an IRt optimization module, a dynamic translation function insertion module and a target program generation module. The source program analysis module reads and identifies a source platform binary program input by a user to obtain a code segment, a data segment and a symbol table, constructs an address mapping table, translates the data segment to obtain a translated data segment, sends the symbol table and the code segment to an instruction decoding module, sends the address mapping table to an IRs optimization module, sends the symbol table to an IRt optimization module and a dynamic translation function insertion module, and sends the translated data segment to a target program generation module; the instruction decoding module decodes the code segment received from the source program analysis module, generates intermediate representation IRs related to the source platform, and sends the IRs to the IRs optimization module; the IRs optimization module constructs an address mapping table and a control flow diagram containing a basic block list, sends the address mapping table and the control flow diagram containing the basic block list to the IRt optimization module, sends the address mapping table containing the basic block list to the target program generation module, optimizes the IRs received from the instruction decoding module to obtain optimized IRs, and sends the optimized IRs to the HIR generation module; the HIR generation module converts the optimized IRs received from the IRs optimization module to obtain a source platform-independent intermediate representation HIR, and sends the HIR to the IRt generation module; the IRt generation module analyzes and converts the HIR received from the HIR generation module, generates an intermediate representation IRt related to the target platform, and sends the IRt to the IRt optimization module; the IRt optimization module receives an address mapping table containing a basic block list from the IRs optimization module, receives the IRt from the IRt generation module, optimizes the IRt to obtain the optimized IRt, and sends the optimized IRt to the dynamic translation function insertion module; the dynamic translation function insertion module receives a symbol table from the source program analysis module, receives the optimized IRt from the IRt optimization module, and inserts a jump target label into the symbol table; analyzing the optimized IRt, marking the optimized IRt, inserting a dynamic translation function to obtain the optimized IRt with the inserted dynamic translation function, sending the optimized IRt with the inserted dynamic translation function to a target program generation module, and sending a symbol table with an inserted jump target label to the target program generation module; and the target program generation module receives the optimized IRt and the address mapping table into which the dynamic translation function is inserted from the dynamic translation function insertion module, and generates a final target platform binary program and the address mapping table.

and 2.1 reading the source platform binary program input by the user through the source program analysis module, and identifying the source platform binary program into a code segment, a data segment and a symbol table according to the format of the source platform binary program.

2.2, an address mapping table is constructed, the address mapping table is used for storing corresponding address information of functions and variables in a binary program of a source platform, and the method comprises the following steps: and adding the function name and the variable name in the symbol table and the address of the function name and the variable name in the source platform binary program to the address mapping table. The address mapping table is composed of M + N table entries, where M is the number of functions in the source platform binary program, N is the number of variables in the source platform binary program, and each table entry includes 2 fields, which are respectively a function name and a function start address (the start address of a function in the source platform binary program), or a variable name and a variable address (the address of a variable in the source platform binary program).

2.3 according to the source platform and the target platform size end have difference to translate the source platform binary program data segment, get the translated data segment, the method is: if the size end modes of the source platform and the target platform are not different, the whole data segment is completely copied to be used as the data segment of the final target binary program; if the source platform and the target platform have opposite big-end and small-end modes, the data segment is converted into a big end and a small end, the sequence of high and low bits of data is exchanged under the condition that the original attributes (the number of bytes occupied by the data and the actual value of the data) of the data segment are not changed, and the data segment is adjusted to be suitable for the data organization mode of the target platform.

2.4, the symbol table and the code segment are sent to an instruction decoding module, and the translated data segment is sent to a target program generating module; and sending the address mapping table to an IRs optimization module, and sending the symbol table to an IRt optimization module and a dynamic translation function insertion module.

3.1 letting the variable m be 1;

3.2 obtaining the start address of the mth function from the symbol table, traversing each instruction of the mth function, decoding each instruction, and converting the instruction into an intermediate representation form related to the source platform. In the process, each source instruction in the code segment corresponds to one or more IR: if the instruction is an operation instruction (such as common addition, subtraction, multiplication, division and shift), one instruction corresponds to one IR; IF the instruction is a special instruction (such as a comparison instruction), the execution OF the instruction can cause the change OF a flag bit (such as an operation result flag bit reflecting an operation result, such as a carry flag CF, a parity flag PF, an auxiliary carry flag AF, a sign flag SF, an overflow flag OF, a zero flag ZF, a state control flag bit controlling the operation OF a CPU, such as a tracking flag TF, an interruption permission flag IF, a direction flag DF and the like), one instruction corresponds to a plurality OF IRs; if the execution of an instruction depends on a flag bit (e.g., a jump instruction), then one instruction corresponds to multiple IRs.

Fourthly, the IRs optimization module receives IRs from the instruction decoding module, receives an address mapping table from the source program analysis module, optimizes the IRs to obtain optimized IRs, and modifies the address mapping table to obtain an address mapping table containing a basic block list; constructing a control flow graph; and sending the optimized IRs to an HIR generation module, sending an address mapping table containing a basic block list and a control flow chart to an IRt optimization module, and sending the address mapping table containing the basic block list to a dynamic translation function insertion module. The method comprises the following steps:

4.1 basic block segmentation is carried out on IRs, and an address mapping table is modified, wherein the method comprises the following steps: taking a function entry instruction in the IRs, a first instruction at a jump target address of the jump instruction, the jump instruction and a next instruction of the function call instruction as an entry of the basic block; and taking a jump instruction, a function call instruction and a program return instruction as the exits of the basic blocks. Meanwhile, the address of the first instruction of the basic block in the source platform binary program is added into an address mapping table, and Q basic blocks are added into the address mapping table (the Q basic block entries are called basic block lists), wherein each basic block entry comprises two fields of a basic block sequence number and a basic block address;

4.2, traversing the basic block list in the address mapping table obtained in the step 4.1, and finding out the parent node and the child node corresponding to each basic block in the basic block list, namely the predecessor and the successor of each basic block. Forming a control flow graph by all basic blocks in the same function according to the relationship between a precursor and a successor; the M functions have M control flow graphs. And sending the M control flow graphs to an IRt optimization module.

And 4.3, respectively carrying out data flow analysis on the M control flow diagrams, wherein the data flow analysis comprises active variable analysis and arrival fixed value analysis, constructing a reference-fixed value chain (a ud chain for short) and a fixed value-reference chain (a du chain for short), and calculating active information of each basic block register, wherein the active information comprises data flow information related to the flag bit.

And 4.4 deleting unused instructions for assigning the zone bits in the IRs according to the data flow information related to the zone bits in the data flow analysis result to obtain the optimized IRs. The code expansion generated in the translation process is reduced, so that the execution performance of the translated program is improved;

6.1.1 letting the variable q be 1;

6.1.3, if Q is not more than Q, turning to 6.1.2; if Q > Q, the mapping of Q physical registers is completed, an intermediate representation irrelevant to the target platform is obtained, P items are shared in the intermediate representation irrelevant to the target platform, the intermediate representation irrelevant to the target platform is marked with platform, P is a positive integer, and 6.2 is carried out.

6.2.1 letting the variable p be 1;

6.2.4 determining whether the current intermediate representation operation is a target platform independent operation that can be implemented by combination with the target platform instruction. If so, converting the target platform irrelevant operation which can be realized by the target platform instruction through combination into the instruction combination corresponding to the target platform to obtain the target platform relevant intermediate representation IRt, and converting to 6.2.6; otherwise, go to 6.2.5;

6.2.6 making P equal to P +1, if P is less than or equal to P, rotating to 6.2.2; if P > P, the conversion from the target platform irrelevant intermediate representation to the target platform relevant intermediate representation is completed, the target platform relevant intermediate representation IRt is sent to the IRt optimization module, and the seventh step is executed.

7.2.5 distributing register to the temporary variable in IRt, identifying cycle area, distributing register to the temporary variable in cycle area, reducing the overflow of register in cycle, reducing the access frequency to memory, and improving the execution efficiency of cycle;

after the above 5 kinds of optimization operations, an intermediate representation related to the optimized target platform, that is, an optimized IRt, is obtained.

Eighthly, the dynamic translation function inserting module receives a symbol table from the source program analyzing module, receives the optimized IRt from the IRt optimizing module, and inserts a jump target label into the symbol table; analyzing the optimized IRt, marking the optimized IRt and inserting a dynamic translation function to obtain the optimized IRt inserted with the dynamic translation function, sending the optimized IRt inserted with the dynamic translation function to a target program generation module, and sending a symbol table inserted with a jump target label to the target program generation module, wherein the method comprises the following steps:

8.3.1 save the static translation site, save all registers of the target platform, and then build the call stack. And pressing the path of the source binary program file, the path of the address mapping table and the original jump address into a call stack by taking the path of the source binary program file, the path of the address mapping table and the original jump address as parameters, and simultaneously storing the states of all registers of the source platform in the call stack according to a certain sequence.

And 8.4, sending the optimized IRt with the dynamic translation function inserted and the symbol table with the label of the jump target inserted to a target program generation module.

Ninthly, generating a binary program and an address mapping table corresponding to the target platform by the target program generation module according to the optimized IRt inserted with the dynamic translation function;

9.4 according to the data segment offset calculated in step 9.3 and the relocation table generated in step 9.2, address adjustment is carried out on the data segment offset in the binary instruction, and a corresponding value in the symbol table inserted with the jump target tag is updated. And obtaining a target platform binary program and an address mapping table.

In order to verify the effect of the invention, an embodiment of the invention is constructed on an X86 platform, that is, a dynamic and static binary translation system (hereinafter referred to as a test embodiment) from an ARM platform to an X86 platform is constructed, and then the binary translation effect of the embodiment is tested. The input (source binary program) of the test embodiment is an android apk application program on an ARM platform, and the binary program and the address mapping table (output of the test embodiment) of the X86 platform are output after the binary translation system constructed in the first step of the invention is adopted for translation. The specific process comprises the following steps: firstly, applying a static translation and optimization process to the ARM program, and inserting a part which cannot be statically translated into a dynamic translation function to obtain an intermediate file; and then loading and operating the intermediate file, directly operating the part after the static translation, and dynamically translating and operating the part inserted with the dynamic translation function.

The testing method comprises the steps of running the android apk application program on an ARM hardware platform (the single core specification of a processor is ARMv82.2GHz), and testing and recording the turnover time of each function of the android apk application program. And then, running the test embodiment on an X86 hardware platform (the processor single core specification is 2.2GHz), translating and executing the same android apk application program, and testing and recording the turnover time of each function of the android apk application program. The result shows that when the android apk is translated and operated on the x86 hardware platform with the same frequency by adopting the method, the execution performance of about 80% can be obtained compared with the execution performance of the android apk which is originally operated on the ARM hardware platform. For the technical field of binary translation, 80% has excellent effect.

Claims

1. A dynamic and static combined binary program translation method is characterized by comprising the following steps:

firstly, constructing a dynamic and static combined binary translation system, wherein the dynamic and static combined binary translation system consists of a source program analysis module, an instruction decoding module, an IRs optimization module, an HIR generation module, an IRt optimization module, a dynamic translation function insertion module and a target program generation module; the source program analysis module reads and identifies a source platform binary program input by a user to obtain a code segment, a data segment and a symbol table, constructs an address mapping table, translates the data segment to obtain a translated data segment, sends the symbol table and the code segment to the instruction decoding module, sends the address mapping table to the IRs optimization module, sends the symbol table to the IRt optimization module and the dynamic translation function insertion module, and sends the translated data segment to the target program generation module; the instruction decoding module decodes the code segment received from the source program analysis module, generates intermediate representation IRs related to the source platform, and sends the IRs to the IRs optimization module; the IRs optimization module constructs an address mapping table and a control flow diagram containing a basic block list, sends the address mapping table and the control flow diagram containing the basic block list to the IRt optimization module, sends the address mapping table containing the basic block list to the target program generation module, optimizes the IRs received from the instruction decoding module to obtain optimized IRs, and sends the optimized IRs to the HIR generation module; the HIR generation module converts the optimized IRs received from the IRs optimization module to obtain a source platform-independent intermediate representation HIR, and sends the HIR to the IRt generation module; the IRt generation module analyzes and converts the HIR received from the HIR generation module, generates an intermediate representation IRt related to the target platform, and sends the IRt to the IRt optimization module; the IRt optimization module receives an address mapping table containing a basic block list from the IRs optimization module, receives the IRt from the IRt generation module, optimizes the IRt to obtain the optimized IRt, and sends the optimized IRt to the dynamic translation function insertion module; the dynamic translation function insertion module receives a symbol table from the source program analysis module, receives the optimized IRt from the IRt optimization module, and inserts a jump target label into the symbol table; analyzing the optimized IRt, inserting a dynamic translation function into the optimized IRt to obtain the optimized IRt with the inserted dynamic translation function, sending the optimized IRt with the inserted dynamic translation function to a target program generation module, and sending the symbol table with the inserted jump target tag to the target program generation module; the target program generation module receives the optimized IRt and the address mapping table after the dynamic translation function is inserted from the dynamic translation function insertion module, and generates a final target platform binary program and an address mapping table;

secondly, a source program analysis module reads a source platform binary program input by a user, identifies the source platform binary program into a code segment, a data segment and a symbol table, constructs an address mapping table, and adds a function address and a variable address in the address mapping table; the method comprises the following steps:

2.1 the source program analysis module reads a source platform binary program input by a user, and identifies the source platform binary program into a code segment, a data segment and a symbol table with contents as instructions according to the format of the source platform binary program, wherein the contents of the symbol table are function names, variable names and addresses of the function names and the variable names in the source platform binary program;

2.2, an address mapping table is constructed, the address mapping table is used for storing corresponding address information of functions and variables in a binary program of a source platform, and the method comprises the following steps: adding function names and variable names in the symbol table and addresses of the function names and the variable names in the source platform binary program into an address mapping table; the address mapping table consists of M + N table entries, wherein M is the number of functions in the source platform binary program, N is the number of variables in the source platform binary program, and each table entry comprises 2 domains which are respectively a function name and a function initial address or a variable name and a variable address;

2.3 translating the data segment of the binary program of the source platform according to the difference between the size ends of the source platform and the target platform to obtain a translated data segment;

2.4, the symbol table and the code segment are sent to an instruction decoding module, and the translated data segment is sent to a target program generating module; sending the address mapping table to an IRs optimization module, and sending the symbol table to an IRt optimization module and a dynamic translation function insertion module;

3.1 making variable m ═ 1;

3.2 obtaining the starting address of the mth function from the symbol table, traversing each instruction of the mth function, decoding each instruction, and converting the instruction into an intermediate representation form (IRs) related to the source platform; if the instruction is an operation instruction, one instruction corresponds to one IRs; if the instruction is a special instruction which can cause the change of the zone bit when executed, one instruction corresponds to a plurality of IRs; if the execution of the instruction depends on the zone bit, one instruction corresponds to a plurality of IRs;

3.3, if M is equal to M +1, rotating to 3.2; if M is greater than M, sending the Intermediate Representation (IRs) related to the source platform obtained by translation to an IRs optimization module, and turning to the fourth step;

fourthly, the IRs optimization module receives IRs from the instruction decoding module, receives an address mapping table from the source program analysis module, optimizes the IRs to obtain optimized IRs, and modifies the address mapping table to obtain an address mapping table containing a basic block list; constructing a control flow graph; sending the optimized IRs to an HIR generation module, sending an address mapping table containing a basic block list and a control flow chart to an IRt optimization module, and sending the address mapping table containing the basic block list to a dynamic translation function insertion module; the method comprises the following steps:

4.1, dividing basic blocks of IRs to obtain Q basic blocks, and adding Q basic block table entries in an address mapping table, wherein the Q basic block table entries are called basic block lists, each basic block table entry comprises two fields of a basic block serial number and a basic block address, and the address mapping table added with the basic block lists is obtained; q is a positive integer;

4.2 traversing the basic block list in the address mapping table obtained in the step 4.1, and finding out a parent node and a child node corresponding to each basic block for each basic block in the basic block list, namely a precursor and a successor of each basic block; forming a control flow diagram by all basic blocks in the same function according to the relationship between a precursor and a successor; the M functions have M control flow diagrams; sending the M control flow graphs to an IRt optimization module;

4.3, respectively performing data flow analysis on the M control flow diagrams, including active variable analysis and arrival fixed value analysis, constructing a reference-fixed value chain, namely a ud chain, and a fixed value-reference chain, namely a du chain, and calculating active information of each basic block register, wherein the active information comprises data flow information related to a flag bit;

4.4 deleting unused instructions for assigning the zone bits in the IRs according to the data stream information related to the zone bits in the data stream analysis result to obtain optimized IRs;

4.5 sending the optimized IRs to an HIR generation module, sending an address mapping table containing a basic block list and a control flow chart to an IRt optimization module, and sending the address mapping table containing the basic block list to a dynamic translation function insertion module;

fifthly, the HIR generation module receives the optimized IRs from the IRs optimization module, converts the optimized IRs into an intermediate representation (HIR) irrelevant to a source platform, and sends the HIR to the IRt generation module; the method comprises the following steps:

5.1 converting all physical register information related to the source platform in the optimized IRs into a global memory space, enabling a physical register of each source platform to correspond to an independent global memory storage position, recording the attribute of each physical register in the source platform, and adding the attribute of each physical register in the source platform into the primarily optimized IRs to obtain an intermediate representation (HIR) irrelevant to the source platform;

5.2 sending the HIR to an IRt generation module, wherein Q physical registers are shared in the HIR, and Q is a positive integer;

sixthly, the IRt generation module receives the HIR from the HIR generation module, converts the HIR into intermediate representation (IRt) related to the target platform, and sends the IRt to the IRt optimization module, wherein the method comprises the following steps:

6.1 mapping a register which can be mapped to a target platform of a source platform to a register of the target platform to obtain a target platform-independent intermediate representation, wherein P is shared by the target platform-independent intermediate representation and is marked by the platform-independent intermediate representation, and P is a positive integer;

6.2 mapping the intermediate representation irrelevant to the target platform into the intermediate representation IRt relevant to the target platform, and sending the IRt to the IRt optimization module;

seventhly, the IRt optimization module receives an address mapping table and a control flow chart which contain a basic block list from the IRs optimization module, receives the IRt from the IRt generation module, receives a symbol table from the source program analysis module, and optimizes the IRt to obtain the optimized IRt, wherein the method comprises the following steps of:

7.1, according to a control flow diagram received from the IRs optimization module, carrying out arrival fixed value analysis and active variable analysis on the IRt received from the IRt generation module, and constructing a du chain and a ud chain by using analysis results;

7.2, optimizing the IRt according to the results of the arrived fixed value analysis and the active variable analysis to obtain an optimized intermediate representation related to the target platform, namely the optimized IRt;

7.3 sending the optimized IRt to a dynamic translation function insertion module;

eighthly, the dynamic translation function insertion module receives a symbol table from the source program analysis module, receives the optimized IRt from the IRt optimization module, and inserts a jump target label into the symbol table; analyzing the optimized IRt, inserting a dynamic translation function into the optimized IRt to obtain the optimized IRt with the inserted dynamic translation function, sending the optimized IRt with the inserted dynamic translation function to a target program generation module, and sending a symbol table with an inserted jump target tag to the target program generation module, wherein the method comprises the following steps:

8.1 the dynamic translation function insertion module receives the symbol table from the source program analysis module, receives the optimized IRt from the IRt optimization module, and translates the indirect jump instruction in the optimized IRt, the method is: traversing the optimized indirect jump instruction in the IRt, inserting a jump target label, namely label, into a symbol table for the jump instruction capable of statically deducing a jump target, and modifying the indirect jump instruction into a direct jump instruction; marking the jump instruction which cannot statically deduce a jump target in the optimized IRt; obtaining the marked optimized IRt; the method for inserting the label of the jump target into the symbol table comprises the following steps: s jump instructions capable of statically deducing jump targets are provided, S jump target table entries are added into a symbol table, and each table entry comprises a jump target sequence number and a label of the jump target;

8.2 the dynamic translation function inserting module constructs a stack for the dynamic translation function, presses parameters required by the dynamic translation function into the stack, and stores a dynamic and static switching field;

8.3 inserting a dynamic translation function into the optimized IRt, and translating the instruction which can not be translated by the static translation by the dynamic translation function; the flow of the inserted dynamic translation function is as follows:

8.3.1, saving the static translation field, saving all registers of the target platform, and then constructing a call stack; pressing the path of the source binary program file, the path of the address mapping table and the original jump address into a call stack by taking the path of the source binary program file, the path of the address mapping table and the original jump address as parameters, and simultaneously saving the states of all registers of a source platform in the call stack;

8.3.2 the dynamic translation function reads the state of all registers of the source platform from the call stack, and maps the state to the memory space of the dynamic translation function to realize the switching of the state of the registers of the source platform;

8.3.3 storing the target address returned after the dynamic translation function finishes translating the indirect jump instruction in a return value register, and pressing all register states of the source platform into a call stack;

8.3.4 switching the execution flow to a static translation code space, reading the states of all registers of the source platform from the call stack by the static code, storing the states of the registers to the corresponding positions of the static translation code space, completing the data interaction of the source platform in the dynamic and static translation process, then restoring the site, and restoring the registers of the target platform stored in the call stack in the step 8.3.1; after the field recovery is finished, jumping to the corresponding position of the static code, and restarting to execute the static code;

8.4 sending the optimized IRt after the dynamic translation function is inserted and the symbol table of the label inserted with the jump target to a target program generation module;

ninthly, the target program generation module generates a binary program and an address mapping table corresponding to the target platform according to the optimized IRt after the dynamic translation function is inserted;

9.1 the target program generation module receives the optimized IRt inserted with the dynamic translation function and the symbol table inserted with the jump target label from the dynamic translation function insertion module, receives the address mapping table containing the basic block list from the IRs optimization module, and receives the translated data segment from the source program analysis module;

9.2 traversing the optimized IRt inserted with the dynamic translation function, converting each intermediate representation into binary representations of the corresponding instructions of the target platform, wherein the binary representations form a target binary program, and meanwhile, accumulating the sizes of the generated instruction segments in the conversion process; for an instruction needing to access a data segment, inserting a relocation item into a symbol table inserted with a jump target label to obtain a relocation table, and updating a function in a target binary program and an initial address of a basic block into an address mapping table containing a basic block list;

9.4 according to the data segment offset and the relocation table, carrying out address adjustment on the data segment offset in the binary instruction, and updating a corresponding value in the symbol table inserted with the jump target label; and obtaining a target platform binary program and an address mapping table.

2. The dynamic-static combined binary program translation method according to claim 1, wherein the 2.3 steps of translating the data segment of the binary program of the source platform according to the difference between the size ends of the source platform and the target platform are as follows: if the size end modes of the source platform and the target platform are not different, the whole data segment is completely copied to be used as the data segment of the final target binary program; if the source platform and the target platform have opposite big and small end modes, the data segment is converted into a big end and a small end, the sequence of the high order and the low order of the data is exchanged under the condition of not changing the original attribute of the data segment, and the data segment is adjusted to be suitable for the data organization mode of the target platform; the original attribute of the data segment indicates the number of bytes occupied by the data and the actual value of the data.

3. The dynamic-static combined binary program translation method according to claim 1, wherein said flag bits in step 3.2 include operation result flag bits reflecting operation results, including carry flag CF, parity flag PF, auxiliary carry flag AF, sign flag SF, overflow flag OF, zero flag ZF; and the state control flag bits for controlling the operation of the CPU comprise a tracking flag TF, an interrupt permission flag IF and a direction flag DF.

4. The dynamic and static combined binary program translation method according to claim 1, wherein the method for performing basic block segmentation on IRs and adding a basic block list in the address mapping table in step 4.1 comprises: taking a function entry instruction in the IRs, a first instruction at a jump target address of a jump instruction, the jump instruction and a next instruction of a function call instruction as an entry of a basic block; taking a jump instruction, a function call instruction and a program return instruction as the outlets of the basic block; meanwhile, the address of the first instruction of the basic block in the source platform binary program is added into an address mapping table, Q basic block table entries are added into the address mapping table, and each basic block table entry comprises two fields of a basic block sequence number and a basic block address.

5. The dynamic-static combined binary program translation method according to claim 1, wherein the physical registers related to the source platform in step 5.1 refer to all available hardware registers in the instruction set architecture of the source platform, and the attributes of the physical registers in the source platform refer to the usage of the physical registers, including: used as stack pointers, used to store function call return addresses, and used to pass parameters.

6. The dynamic and static combined binary program translation method according to claim 1, wherein said 6.1 step of mapping the registers of the source platform that can be mapped to the target platform to the registers of the target platform is:

6.1.1 letting the variable q be 1;

6.1.3, if Q is equal to or less than Q, then turn to 6.1.2; if Q > Q, it means that the mapping of Q physical registers is completed, resulting in an intermediate representation that is independent of the target platform.

7. The dynamic-static combined binary program translation method according to claim 1, wherein the method of mapping the target platform-independent intermediate representation to the target platform-dependent intermediate representation IRt in step 6.2 is:

6.2.1 let variable p be 1;

6.2.2 operating the p-th item target platform-independent intermediate representation as the current intermediate representation;

6.2.3 judging whether the current intermediate representation operation is a target platform-independent operation directly supported by the target platform; if yes, the current intermediate representation operation does not need to be changed, and the current intermediate representation operation is directly used as intermediate representation related to the target platform, and the operation is switched to 6.2.5; otherwise, turning to 6.2.4;

6.2.4 determining whether the current intermediate representation operation is a target platform independent operation that can be implemented by combination with the target platform instruction; if so, converting the target platform irrelevant operation which can be realized by the target platform instruction through combination into the instruction combination corresponding to the target platform to obtain the target platform relevant intermediate representation IRt, and converting to 6.2.6; otherwise, go to 6.2.5;

6.2.5 inserting function call instruction into the intermediate representation related to the target platform at this time, and implementing the function of the current intermediate representation operation in the form of calling library function in the target platform which has the same function as the current intermediate representation operation, turning to 6.2.6.

6.2.6 changing P to P +1, if P is less than or equal to P, changing to 6.2.2; if P > P, the conversion from the target platform irrelevant intermediate representation to the target platform relevant intermediate representation is completed, and the operation is finished.

8. The dynamic and static combined binary program translation method according to claim 1, wherein the method for optimizing the IRt in step 7.2 is:

7.2.1 traversing the instruction sequence in the IRt, and folding the constant for the calculation of the constant;

7.2.2 traversing the instruction sequence in the IRt, and performing register copy propagation optimization aiming at a target register in the register copy instruction;

7.2.4 traversing the instruction sequence in IRt, and replacing the corresponding instruction in IRt with the instruction more efficient by the target platform;

7.2.5 register allocation is performed for temporary variables in IRt, loop regions are identified, and register allocation is performed preferentially for temporary variables in loop regions.

9. The dynamic-static binary program translating method according to claim 1, wherein 7.2.4 the target platform instructions with higher efficiency refer to instructions with fewer bytes, faster execution speed and higher pipeline throughput than the source platform instructions.

10. The dynamic-static combined binary program translation method according to claim 1, wherein 4 parameters required by the dynamic translation function in the step 8.2 are respectively a source binary program file name, an original jump target address, an address mapping table and all register states of a source platform.