JP2007267539A - Booster circuit, and memory type liquid crystal display device using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a booster circuit for enabling shortening of a boosting time and a memory type liquid crystal display device equipped with such a booster function. <P>SOLUTION: The booster circuit (1) has a first power source line (VDD) having a first level, a second power source line (VSS) having a second level different from the first level, a reference power source line (Vreg) having a reference level different from the first and the second levels, a plurality of boosting capacitors (C1 to C4), connecting at least one of the plurality of boosting capacitors during non-boosting operation between the first and the second power source lines, connecting the plurality of boosting capacitors including the capacitors charged during the non-boosting operation in parallel with the first power source line and the reference power source line during a boosting operation, and connecting in series the plurality of boosting capacitors charged by parallel connection. Furthermore, the booster circuit has a control unit (30) generating voltages having integral times of the reference level or the reciprocal-of-an-integer multiple of the reference level. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a booster circuit and a memory type liquid crystal display device using the booster circuit.

  Conventionally, a booster circuit called a charge pump system is known (for example, Patent Document 1). In a charge pump type booster circuit, a boosting capacitor is charged with a first voltage, and the connection of the charged capacitor is switched to generate a voltage higher than the first voltage.

  However, since the boosting capacitor is charged from zero to the first voltage and the connection of the boosting capacitor needs to be switched again, there is a disadvantage that it takes time to obtain a desired voltage. there were.

  In addition, a liquid crystal display device using a memory liquid crystal having a plurality of optical states and a characteristic (memory characteristic) that maintains a specific state without applying a voltage is known (for example, Patent Document 2). By utilizing such characteristics, in the memory type liquid crystal display device, during the display operation, the scan electrode is driven only to the portion where the display needs to be changed, and the scan electrode is used for the portion where the display does not need to be changed. Therefore, it is possible to control so as not to drive the power and to reduce power consumption.

  For this reason, a booster circuit using a memory-type liquid crystal device needs to be intermittently driven in order to reduce current consumption. However, when the operation of the conventional booster circuit stops, the voltage of the booster capacitor becomes almost zero due to capacitor leakage or the like, so that it takes time for the boosting to rise, and the display rewriting operation is slowed accordingly. .

Japanese Patent No. 3150127 JP-A-2-131286 (pages 11, 12 and 12)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a booster circuit capable of solving the above-mentioned problems and a memory type liquid crystal display device having such a boost function.

  Another object of the present invention is to provide a booster circuit capable of shortening the boosting time and a memory type liquid crystal display device having such a boosting function.

  In order to solve the above problems, a booster circuit according to the present invention includes a first power supply line having a first level, a second power supply line having a second level different from the first level, and first and second levels. A reference power supply line having a different reference level, a plurality of boosting capacitors, and a first switch group for connecting at least one of the plurality of boosting capacitors between the first and second power supply lines during non-boosting operation A second switch group for connecting a plurality of boost capacitors including a capacitor charged during a non-boosting operation during the boost operation to the first power supply line and the reference power supply line in parallel; and a plurality of boost capacitors charged by the parallel connection It has the 3rd switch group which connects a capacitor | condenser in series, It is characterized by the above-mentioned.

  The booster circuit according to the present invention preferably further includes a constant voltage circuit that generates a reference level voltage using a voltage between the first and second power supply lines.

  Furthermore, the booster circuit according to the present invention preferably further includes a fourth switch arranged between the first power supply line or the second power supply line and the constant voltage circuit.

  Further, in the booster circuit according to the present invention, the first, second, and third switch groups are controlled to open and close, and when a plurality of boosting capacitors are connected in series, a voltage that is an integer multiple of the reference level or a fraction of an integer. It is preferable to further have a control unit that generates

  Furthermore, in the booster circuit according to the present invention, it is preferable that the control unit performs control so that the fourth switch is opened during non-boosting.

  In order to solve the above problems, a booster circuit according to the present invention includes a first power supply line having a first level, a second power supply line having a second level different from the first level, and first and second levels. A reference power supply line having a reference level different from that of the first power supply line, a plurality of boosting capacitors, and at least one of the plurality of boosting capacitors connected between the first and second power supply lines during non-boosting operation, and charged. Sometimes, a plurality of boost capacitors including capacitors charged during non-boosting operation are connected in parallel to the first power supply line and the reference power supply line, and a plurality of charged boost capacitors are connected in series to provide a reference. It has a control part which generates the voltage of the integral multiple of a level, or 1 time of an integral number.

  The booster circuit according to the present invention further includes a constant voltage circuit that generates a reference level voltage using the voltage between the first and second power supply lines, and the control unit includes a constant voltage circuit for non-boosting operation. It is preferable to control to stop the operation. This is to reduce power consumption as much as possible.

  Further, in the booster circuit according to the present invention, the plurality of boosting capacitors include a first boosting capacitor and a second boosting capacitor, and the control unit connects the first boosting capacitor to the first power supply line and the reference. A first state in which a second boost capacitor is connected in series to generate a voltage while being connected to the power line and charged; and a second boost capacitor is connected to the first power line and the reference power line. A booster that generates a voltage that is an integral multiple of the reference level or a fraction of an integral number by alternately generating a second state in which a voltage is generated by connecting a first boost capacitor in series while charging. It is preferable to perform the operation.

  Furthermore, in the booster circuit according to the present invention, it is preferable that the control unit varies the boosting operation for alternately generating the first state and the second state according to the state of the load to which the booster circuit supplies a voltage.

  Furthermore, the booster circuit according to the present invention preferably further includes a power source for supplying the first and second levels.

  Furthermore, in the booster circuit according to the present invention, the power source preferably includes a power generation unit and a power storage unit.

  A memory-type liquid crystal display device according to the present invention includes a display unit using a memory-type liquid crystal, a first power supply line having a first level, a second power supply line having a second level different from the first level, And a reference power supply line having a reference level different from the second level, a first boost capacitor, a second boost capacitor, and at least one of the first and second boost capacitors during non-boosting operation. Connect and charge between the first and second power supply lines, connect the first boost capacitor to the first power supply line and the reference power supply line, and charge the second boost capacitor in series. A first state in which a voltage is generated, and a second state in which the first boost capacitor is connected in series while the second boost capacitor is connected to the first power line and the reference power line for charging. Condition and It has a control unit that performs a boosting operation that generates a voltage that is an integral multiple of the reference level or a fraction of an integral number so as to occur alternately. The control unit alternately generates the first state and the second state. The boosting operation to be performed is variable according to the display state of the display portion.

  According to the present invention, before the boosting capacitor is charged, the battery voltage is precharged to a predetermined level, so that the boosting time can be shortened.

  In addition, according to the present invention, the step-up operation is made variable according to the display state of the memory type liquid crystal display device, so that necessary and sufficient power can be generated and power consumption can be reduced. Became possible.

  Hereinafter, a booster circuit according to the present invention and a memory type liquid crystal display device including the booster circuit will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing an outline of a booster circuit according to the present invention.

  The booster circuit 1 includes a power supply 2, a control unit 30 for controlling the booster circuit 1, a constant voltage circuit 3 that generates a reference voltage (Vreg) using a power supply voltage (VSS), and a VDD set to a GND level. Line 4, constant voltage (Vreg) line 5 generated by constant voltage circuit 3, power supply voltage (VSS) line 6, V2 line 7 set to a level twice the reference voltage, set to a level three times the reference voltage V3 line 8, boost capacitors C1 to C4, V3 level stabilization capacitor C5, V2 level stabilization capacitor C6, Vreg level stabilization capacitor C7, and a plurality of switches. Has been.

  The plurality of switches include switches P1 to P4 for controlling connection between the VDD line 4 and C1 to C4, and switches A1 to A4 and A7 for controlling connection between the Vreg line 5 and C1 to C4 and C7. S1 and S3, switches B1 to B7 and Br for controlling the connection between the VSS line 6 and the capacitors C1 to C7 and the constant voltage circuit 3, and a switch D1 for controlling the connection between the V2 line and the capacitors C1 to C4, D3, S2 and S4, switches D2 and D4 for controlling the connection between the V3 line and the capacitors C2 and C4 are included. The plurality of switches are configured to be controlled to be opened and closed in accordance with a timing described later by a control signal from the control unit 30, and are configured by various semiconductor elements such as MOSFETs.

  The power source 2 may be a dry battery or a storage battery. When the power supply 2 charges the storage battery with a power generation means such as a solar battery, the power supply fluctuation is large, and as a result, the boost voltage used for display fluctuates, which adversely affects the display quality. Therefore, a reference voltage is supplied by a constant voltage circuit, a stable boosted voltage is created, and display quality is stabilized.

  The voltage level of the VSS line 6 varies somewhat depending on the capacity of the power supply 2 and the charging status, but the Vreg line 5 is always maintained at a constant voltage level by the constant voltage circuit. Therefore, the V2 line 7 and the V3 line 8 generated based on the Vreg line 5 are always maintained at a constant voltage level. The Vreg line 5, the V2 line 7 and the V3 line 8 are connected to a drive circuit for driving the liquid crystal panel 20 in a memory type liquid crystal display device which will be described later.

  FIG. 2 is a diagram showing the opening / closing timing of the switch of the booster circuit 1.

  2A shows the open / close timing of the switches B1 to B7, FIG. 2B shows the open / close timing of the switches Br and A7, FIG. 2C shows the open / close timing of the switches P1 and P2, and FIG. (D) shows the opening / closing timings of the switches P3 and P4, FIG. 2 (e) shows the opening / closing timings of the switches S3, S4, A1, A2, D3, and D4, and FIG. 2 (f) shows the switches S1, S2, A3. , A4, D1 and D2 open / close timings are shown. The control unit 30 controls a switch included in the booster circuit 1 according to the opening / closing timing shown in FIG.

  2A to 2F, each switch is controlled to be turned on (energized) when it is at “H” level, and is turned off (cut off) when it is at “L” level.

  In FIG. 2, times T0 to T1 indicate the initial operation of the booster circuit 1, and the boosting operation of the booster circuit 1 is started from time T1. In the step-up operation, state 1 from time T1 to T2 (or times T3 to T4) and state 2 from time T2 to T3 (or T4 to T5) are repeatedly executed. When the boosting operation is resumed, the boosting operation in which the state 1 and the state 2 are repeated through the initial state is performed again.

  FIG. 3 is a diagram for explaining the operation of the booster circuit 1 in the initial state.

  FIG. 3 shows an initial state at times T0 to T1 in FIG. In FIG. 3, in order to simplify the description, switches and the like that are turned off at times T0 to T1 are omitted from FIG. 2 except for the switch Br.

  As shown in FIGS. 2A, 2C, and 2D, in the initial state, only the switches B1 to B7 and P1 to P4 are turned on, so that the capacitors C1 to C7 are connected to the VDD line 4 and the VSS line. 6 are connected in parallel, and each is charged by the power source 2. That is, in the initial state, the capacitors C1 to C7 are already charged to the VSS level.

  Further, as shown in FIG. 2B, in the initial state, the switch Br is OFF, so that the constant voltage circuit 3 does not operate and no voltage is generated on the Vreg line 6. In this case, power consumption in the initial state can be reduced by not operating the constant voltage circuit 3.

  In the period from T0 to T1 shown as the initial state in FIG. 2, an appropriate time is allocated while the load to which the booster circuit 1 is connected (for example, the driving device of the memory type liquid crystal display device) is stopped. Therefore, an appropriate period can be set according to the load. In that sense, the times T0 to T1 described in FIG. 2 are examples, and are not limited to such a period.

  FIG. 4 is a diagram for explaining the operation of the booster circuit 1 in the state 1.

  FIG. 4 shows a state 1 at time T1 to T2 or T3 to T4 in FIG. In FIG. 4, switches and the like that are turned off at times T1 to T3 or T3 to T4 are omitted from FIG.

  In state 1, the switches S1 and D1 are turned on and the boosting capacitor C1 is connected between the Vreg line 6 and the V2 line 7, and the switches S2 and D2 are turned on and the boosting capacitor C2 is connected to the V2 line 7 and the V3 line. 8, the switches P 3 and A 3 are turned on and the boosting capacitor C 3 is connected between the VDD line 4 and the Vreg line 6, and the switches P 4 and A 4 are turned on and the boosting capacitor C 4 is connected to the VDD line 4 and Connected between Vreg lines 6. The stabilizing capacitor C5 for the V3 line 8 is connected between the VDD line 4 and the V3 line 8, and the stabilizing capacitor C6 for the V2 line 7 is connected between the VDD line 4 and the V2 line 7, and the switch A7. Is turned on, and the capacitor C7 for stabilizing the Vreg line 5 is connected between the VDD line 4 and the Vreg line 5. Further, the switch Br is turned on to supply a voltage to the constant voltage circuit 3, and the voltage Vreg is supplied to the Vreg line 5.

  In the state 1, the stabilizing capacitor C7 and the boosting capacitors C3 and C4 are connected between the VDD line 4 and the Vreg line 5, so that the voltage of the Vreg line 5 is charged. Immediately after the initial state, the charging voltage is such that the voltage of the VSS line 6> the voltage of the Vreg line 5. This is because the constant voltage circuit 3 has a power supply capability in the charge potential direction of the boost capacitor, but has almost no power supply capability in the discharge potential direction. Therefore, the initial state is the voltage level of the VSS line 6. However, the voltage is gradually lowered to the output level of the constant voltage circuit 3 because charges are consumed by repeating the boosting.

  Further, the boosting capacitor C1 discharges the charge accumulated in the initial state to the V2 line 7 with reference to the Vreg line 5, and works to push up the voltage of the V2 line 7 to twice the voltage of the Vreg line 5. . When the state 1 is changed to the state 1 after the state 2 (for example, times T3 to T4), the boosting capacitor C1 discharges the charge accumulated in the state 2 to the V2 line 7 with reference to the Vreg line 5. Will be. The electric charge discharged from the boosting capacitor C1 is charged into the stabilizing capacitor C6. Since the electrostatic capacitance of the stabilizing capacitor C6 is sufficiently larger than the electrostatic capacitance of the boosting capacitor C1, The V2 line 7 cannot be double the voltage of the Vreg line 5.

  Further, the boosting capacitor C2 discharges the charge accumulated in the initial state to the V3 line 8 with reference to the V2 line 7, and works to push up the voltage of the V3 line 8 to three times the voltage of the Vreg line 5. . When the state 1 is changed to the state 1 after the state 2 (for example, time T3 to T4), the boosting capacitor C2 discharges the charge accumulated in the state 2 to the V3 line 8 with reference to the Vreg line 5. Will be. The electric charge discharged from the boosting capacitor C2 is charged into the stabilizing capacitor C5. Since the electrostatic capacitance of the stabilizing capacitor C5 is sufficiently larger than the electrostatic capacitance of the boosting capacitor C2, V3 line 8 cannot be three times the voltage of Vreg line 5.

  FIG. 5 is a diagram for explaining the operation of the booster circuit 1 in the state 2.

  FIG. 5 shows a state 2 at time T2 to T3 or T4 to T5 in FIG. In FIG. 5, switches and the like that are turned off at times T2 to T3 or T4 to T5 are omitted from FIG.

  In state 2, the switches P1 and A1 are turned on and the boosting capacitor C1 is connected between the VDD line 4 and the Vreg line 6, and the switches P2 and A2 are turned on and the boosting capacitor C2 is connected to the VDD line 4 and the Vreg line. 6, the switches S3 and D3 are turned on and the boosting capacitor C3 is connected between the Vreg line 6 and the V2 line 7, and the switches S4 and D4 are turned on and the boosting capacitor C4 is connected to the Vreg line 6 and Connected between V3 lines 8. The stabilizing capacitor C5 for the V3 line 8 is connected between the VDD line 4 and the V3 line 8, and the stabilizing capacitor C6 for the V2 line 7 is connected between the VDD line 4 and the V2 line 7, and the switch A7. Is turned on, and the capacitor C7 for stabilizing the Vreg line 5 is connected between the VDD line 4 and the Vreg line 5. Further, the switch Br is turned on to supply a voltage to the constant voltage circuit 3, and the voltage Vreg is supplied to the Vreg line 5.

  In the state 2, the stabilization capacitor C <b> 7 and the boost capacitors C <b> 1 and C <b> 2 are connected between the VDD line 4 and the Vreg line 5, so that the voltage of the Vreg line 5 is charged.

  Further, the boosting capacitor C3 discharges the charge accumulated in the state 1 to the V2 line 7 with reference to the Vreg line 5, and works to push up the voltage of the V2 line 7 to twice the voltage of the Vreg line 5. The electric charge discharged from the boosting capacitor C3 is charged into the stabilizing capacitor C6. Since the capacitance of the stabilizing capacitor C6 is sufficiently larger than that of the boosting capacitor C3, The V2 line 7 cannot be double the voltage of the Vreg line 5.

  Further, the boosting capacitor C4 discharges the charge accumulated in the state 1 to the V3 line 8 with reference to the V2 line 7, and works to push up the voltage of the V3 line 8 to three times the voltage of the Vreg line 5. . The electric charge discharged from the boosting capacitor C4 is charged into the stabilizing capacitor C5. Since the capacitance of the stabilizing capacitor C5 is sufficiently larger than the electrostatic capacitance of the boosting capacitor C4, V3 line 8 cannot be three times the voltage of Vreg line 5.

  The controller 30 repeatedly executes the state 1 and the state 2 after the start of the boosting operation (for example, after the time T1 in FIG. 2), the voltage of the V2 line 7 becomes twice the voltage of the Vreg line 5, and the V3 line 8 Is controlled to be three times the voltage of the Vreg line 5. In this example, the set of boosting capacitors C1 and C2 and the set of boosting capacitors C3 and C4 are configured to operate alternately. However, only one set of boosting capacitors may be set. There may be more.

  By the way, in order to appropriately boost the booster circuit 1, it is necessary that the total charge amount before starting the boosting operation is smaller than the total charge amount after starting the boosting operation. Note that the total charge amount before starting the boosting operation can be obtained by VSS × (C1 + C2 + C3 + C4 + C5 + C6 + C7), and the total charge amount after starting the boosting operation can be obtained by Vreg × C7 + V2 × C6 + V3 × C5. Further, when the power source 2 is a storage battery charged by a solar battery or the like, VSS needs to be set to an overcharge prevention voltage.

  In this example, VSS was set to 2.7 [V], Vreg voltage was set to 1.66 [V], V2 voltage was set to 3.32 [V], and V3 voltage was set to 4.98 [V]. The capacitances of the boosting capacitors C1 to C4 are set to 0.068 [μF], the capacitances of the stabilizing capacitors C5 and C6 are set to 0.22 [μF], and the stabilizing capacitor C7 The capacitance was set to 0.33 [μF]. However, the above is an example, and other appropriate values can be set.

  FIG. 6 is a diagram for explaining the boosting operation of the boosting circuit.

  In FIG. 6, a curve L1 shows a change in voltage of the Vreg line 5, a curve L2 shows a change in voltage of the V2 line 7, and a curve L3 shows a change of voltage in the V3 line 8. In FIG. 6, a curve L11 shows an example of transition from the VDD voltage to the voltage of the Vreg line 5, a curve L12 shows an example of transition from the VDD voltage to the voltage of the V2 line 7, and a curve L13 shows the VDD An example of transition from the voltage to the voltage of the V3 line 8 is shown.

  The booster circuit 1 according to the present invention is designed so that the state 1 and the state 2 described above are repeatedly executed from the boost operation start time (T10), and the voltage of each line becomes a desired voltage at the time T11. . On the other hand, when the boosting operation is started from the VDD voltage, a period from the boosting operation start time (T10) to time T12 is required. As described above, such a difference occurs because, in the booster circuit 1, the boosting capacitor is charged with the power supply voltage VSS in the initial state before the start of the boosting operation. Therefore, the voltage can be boosted to a desired voltage in a short time.

  FIG. 7 is a diagram illustrating a configuration example of a memory-type liquid crystal display panel 20 using the memory-type liquid crystal 10.

  The memory liquid crystal refers to a liquid crystal having a plurality of optical states and having a characteristic of maintaining a specific state without applying a voltage, and includes, for example, a ferroelectric liquid crystal and a cholesteric liquid crystal.

  In the liquid crystal panel 20, as shown in FIG. 7, a polarizing plate 15 (transmission axis direction a) and a reflective polarizing plate 16 (transmission axis direction b) are arranged.

  Further, the long axis direction of the molecules of the memory liquid crystal 10 in the second ferroelectric state is arranged so as to coincide with the transmission axis a and the transmission axis b. Further, the major axis direction of the liquid crystal molecules in the first ferroelectric state was set at another position along the liquid crystal cone as shown in FIG.

  The reflective polarizing plate 16 is composed of a multilayer film such as a polyester resin, has a transmission axis b and a reflection axis orthogonal to each other, transmits linearly polarized light having a vibration plane parallel to the transmission axis, and is parallel to the reflection axis. It has a function of reflecting linearly polarized light having a vibration surface.

  FIG. 8 is a cross-sectional view of the liquid crystal panel 20 and the auxiliary light source 60 according to the present invention.

  As shown in FIG. 8, the liquid crystal panel 20 includes a first transparent glass substrate 11a, a second transparent glass substrate 11b, scanning electrodes (scanning lines) 13a provided on the first transparent glass substrate 11a, Signal electrode (signal line) 13b provided on the transparent glass substrate 11b, the polymer alignment film 14a applied on the scanning electrode 13a and subjected to the rubbing treatment, and the high applied on the signal electrode 13b and subjected to the rubbing treatment. Memory alignment liquid crystal 10 sandwiched between the molecular alignment film 14b, the seal member 12, the first and second transparent glass substrates 11a and 11b and sealed by the seal member 12, and provided outside the first transparent glass substrate 11a. The reflection type polarizing plate 16 and the polarizing plate 15 provided outside the second transparent glass substrate 11b are used.

  In consideration of low power consumption and thinness, a backlight using an organic EL cell as a light emitting element is arranged as an auxiliary light source 60 below the reflective polarizing plate 16 of the liquid crystal panel 20. Note that an auxiliary light source using another light-emitting element can also be used.

  In FIG. 8, five scan electrodes 13 a are shown for convenience, but in this embodiment, 33 scan electrodes 13 a configured by a transparent conductive film pattern are arranged over the entire liquid crystal panel 20. Also. Although not clearly shown in FIG. 8, in the present embodiment, 33 signal electrodes 13b formed of a transparent conductive film pattern are arranged over the entire liquid crystal panel 20 so as to be orthogonal to the scanning electrodes 13a. Each point where the scanning electrode 13a and the signal electrode 13b intersect each other is configured to be each pixel (1089 pixels) of the liquid crystal panel 20.

  As the memory liquid crystal 10, “Felix 501” manufactured by Clariant Co. was used and sandwiched between the first and second transparent glass substrates 11a and 11b with a thickness of about 1.7 μm.

  FIG. 9 is a diagram illustrating an example of switching of the memory liquid crystal 10 in the liquid crystal panel 20.

  FIG. 9A shows a state where the auxiliary light source 60 is turned off, and FIG. 9B shows a state where the auxiliary light source 60 is turned on. The horizontal axis of each graph is applied voltage (V) applied between the scanning electrode 13a and the signal electrode 13b with respect to the scanning electrode 13a of the liquid crystal panel 20 (that is, applied to the ferroelectric liquid crystal 10). Applied voltage), and the vertical axis represents the light transmittance of the liquid crystal panel 20.

  In the state where the auxiliary light source 60 is turned off (see FIG. 9A), the polarity of the applied voltage is changed to change the memory liquid crystal 10 to the first ferroelectric state (the molecules of the memory liquid crystal 10 When the major axis direction does not coincide with either the transmission axis a of the polarizing plate 15 or the transmission axis b of the reflective polarizing plate 16), the major axis direction of the liquid crystal molecules is inclined at an angle with respect to the transmission axis a. The light having a vibration plane parallel to the transmission axis a of the polarizing plate 15 incident on the liquid crystal panel 20 has a vibration plane substantially perpendicular to the transmission axis b of the reflective polarizing plate 16 due to the birefringence of the memory liquid crystal 10. And reflected by the reflective polarizing plate 16 (reflection state). Therefore, when the auxiliary light source 60 is turned off, in the first ferroelectric state, the light incident on the liquid crystal panel 20 is reflected by the reflective polarizing plate 16, and white display on the liquid crystal panel 20 (high light transmittance). It becomes.

  In the state where the auxiliary light source 60 is turned off, when the polarity of the applied voltage is changed to shift the memory liquid crystal 10 to the second ferroelectric state, the major axis direction of the molecules of the memory liquid crystal 10 is the polarizing plate. 15 is parallel to the transmission axis a of the reflective polarizing plate 16 and light having a vibration plane parallel to the transmission axis a incident on the liquid crystal panel 20 is transmitted through the liquid crystal panel 20 (transmission state). ) And reflected from the surface of the auxiliary light source 60. Since the surface of the auxiliary light source 60 is usually dark blue or the like, therefore, when the auxiliary light source 60 is turned off, in the second ferroelectric state, the light incident on the liquid crystal panel 20 is reflected by the surface of the auxiliary light source 60. On the liquid crystal panel 20, black display (low light transmittance) is obtained.

  Thus, in the state where the auxiliary light source 60 is turned off (see FIG. 9A), the voltage applied to the memory liquid crystal 10 is increased (the voltage value at which the light transmittance starts to increase exceeds Va). When the voltage value at which the increase in light transmittance is saturated is Vb (positive threshold) or more, the ferroelectric liquid crystal maintains the first ferroelectric state without applying a voltage thereafter (that is, 0 V application) The white display will continue. Similarly, the voltage applied to the memory liquid crystal 10 is decreased (the voltage value at which the light transmittance begins to decrease exceeds Vc), and the voltage value at which the decrease in the light transmittance is saturated is represented by Vd (negative threshold). Assuming the following, the ferroelectric liquid crystal maintains the second ferroelectric state and continues to display black even if no voltage is applied thereafter (that is, 0 V is applied). The transition from one ferroelectric state to the other ferroelectric state is called polarity reversal.

  In a state in which the auxiliary light source 60 is turned on (see FIG. 9B), the polarity of the applied voltage is changed to change the memory liquid crystal 10 to the first ferroelectric state (the molecules of the memory liquid crystal 10 When the major axis direction does not coincide with either the transmission axis a of the polarizing plate 15 or the transmission axis b of the reflective polarizing plate 16), the major axis direction of the liquid crystal molecules is inclined at an angle with respect to the transmission axis a. The light having the vibration plane parallel to the transmission axis b of the reflective polarizing plate 16 incident on the liquid crystal panel 20 from the auxiliary light source 60 is almost perpendicular to the transmission axis a of the polarizing plate 15 due to the birefringence of the memory liquid crystal 10. Has a vibrating surface and is absorbed by the polarizing plate 15. Therefore, when the auxiliary light source 60 is turned on, in the first ferroelectric state, the light from the auxiliary light source 60 is absorbed by the polarizing plate 15 and becomes black display (low light transmittance) on the liquid crystal panel 20.

  In the state where the auxiliary light source 60 is turned on, when the polarity of the applied voltage is changed and the memory liquid crystal 10 is transferred to the second ferroelectric state, the major axis direction of the molecules of the memory liquid crystal 10 is the polarizing plate. Accordingly, light having a vibration plane parallel to the transmission axis b incident on the liquid crystal panel 20 from the auxiliary light source 60 is transmitted through the liquid crystal panel 20. (Transparent state). Therefore, when the auxiliary light source 60 is turned on, in the second ferroelectric state, light incident on the liquid crystal panel 20 from the auxiliary light source 60 is observed on the liquid crystal panel 20 and white display (light transmission) is performed on the liquid crystal panel 20. ).

  Thus, in the state where the auxiliary light source 60 is turned on (see FIG. 9B), the voltage applied to the memory liquid crystal 10 is increased (the voltage value at which the light transmittance starts to increase exceeds Va). When the voltage value at which the increase in light transmittance is saturated is Vb (positive threshold) or more, the ferroelectric liquid crystal maintains the first ferroelectric state without applying a voltage thereafter (that is, 0 V application) The black display will continue. Similarly, the voltage applied to the memory liquid crystal 10 is decreased (the voltage value at which the light transmittance begins to decrease exceeds Vc), and the voltage value at which the decrease in the light transmittance is saturated is represented by Vd (negative threshold). Assuming the following, the ferroelectric liquid crystal maintains the second ferroelectric state and continues white display without applying a voltage thereafter (that is, applying 0 V).

  FIG. 10 is a diagram illustrating a schematic block configuration diagram of the liquid crystal display device 100.

  The liquid crystal display device 100 includes a booster circuit 1, a liquid crystal panel 20, a display control unit 21 for controlling display of the liquid crystal panel 20, and a scanning drive voltage waveform generation for applying a voltage waveform to each scanning electrode (scanning line) 13a. A circuit 22, a signal drive voltage waveform generation circuit 23 for applying a voltage waveform to each signal electrode (signal line) 13b, a control unit 30 for performing overall control of the liquid crystal display device 100, a motor for performing a clock operation, etc. A clock unit 31, a RAM 32, a ROM 33, an auxiliary light source 60 arranged on the reflective polarizing plate 16 side of the liquid crystal panel, an auxiliary light source control unit 61 for controlling ON / OFF of the auxiliary light source, and the like. The

  The control unit 30 controls the booster circuit 1 described above according to a program stored in advance in the ROM 33, creates display data using the time information and the like timed by the control unit 30, and creates the display data on the liquid crystal panel 20 based on the display data. The display control unit 21 is controlled so that time information and the like are displayed.

  In addition, when the user turns on the auxiliary light source switch 62 when the periphery of the liquid crystal display device 100 is dark, the control unit 21 performs control to control the auxiliary light source 61 and turn on the auxiliary light source 60. In addition, although the liquid crystal display device 100 was comprised in the shape of the wristwatch, it is not limited to this.

  FIG. 11 is a diagram showing some pixels (3 × 3) of the liquid crystal panel 20.

In Figure 11, the _X 1 to X ₃ three of the 33 scanning lines 13a, 9 pixels composed of three _Y 1 to Y ₃ of the 33 signal lines 13b (1 , 1) to (3, 3).

  FIG. 12 is a diagram showing an example of a drive voltage waveform supplied when all nine pixels shown in FIG. 7 are rewritten (overall display processing).

FIG. 12 shows a state where the auxiliary power supply is OFF (see FIG. 9A). 12A to 12F include a reset period RS to each of the scanning lines X _{1 to} X ₃ and the signal lines Y ₁ to Y ₃ and _three subsequent selection periods f _{1 to} f ₃ . An applied voltage waveform in one frame period F is shown. The vertical axis represents the voltage (V) supplied from the booster circuit 1, and the horizontal axis represents time (t).

The reset period RS includes a first period RS ₁ and a second period RS ₂ . In the first period RS _1, the V3 (for example,, -5V) to the scanning lines _X 1 to X ₃ is applied to each signal line _Y 1 to Y ₃ VDD (e.g., 0V) so it is applied A potential difference V3 (<Vd) is generated in the liquid crystal of each pixel, and each pixel is inverted to the second ferroelectric state to display black. In the second period RS _2, to each scanning line _X 1 _{~X 3} VDD (e.g., 0V) is applied, the V3 (for example,, -5V) to the signal lines _Y 1 to Y ₃ is applied Therefore, a potential difference −V3 (> Vb) is generated in the liquid crystal of each pixel, and each pixel is inverted to the first ferroelectric state to display white. Thus, in the reset period RS, all the pixels are once driven to display black and white, and the previous history is erased.

The next first selection period f ₁ includes a first period f ₁₁ and a second period f ₁₂ .

In the first period _{f 11,} the scanning line _{X 1} VDD is applied to the scanning lines _{X 2} and _{X 3} Vreg is applied. That is, the selected scan lines _{X 1,} pixels on the scanning line _{X 1} line (1,1), the rewriting of the pixels of the (1,2) and (1,3) are carried out. At this time, since the signal lines _{Y 1} and _Y are ₂ V3 is applied, a potential difference V3 (<Vd) is generated in the pixel (1,1) and (1,2), a second ferroelectric state Inverted to display black. Further, the signal line Y ₃ since Vreg is applied, a potential difference V2 (> Vd) is generated in the pixel (1,3), a dielectric state remains white display not inverted.

In the second period _{f 12,} V3 is applied to the scan lines _{X 1,} since VDD is applied to the signal lines _{Y 1} and _{Y 2,} the potential difference in the pixel (1,1) and (1,2) V3 (<Vd) is generated, the second ferroelectric state is maintained, and black is displayed. Further, since the signal line Y ₃ V2 is applied, a potential difference V2 (> Vd) is generated in the pixel (1,3) remains white display first ferroelectric state is maintained.

Similarly, in the second selection period f ₂ , the scanning line X ₂ is selected, and the pixels are rewritten for the pixels (2, 1), (2, 2), and (2, 3) on the scanning line X _2. Is done. At this time, since the signal lines Y ₁ V3 is applied, a potential difference V3 (<Vd) is generated in the pixel (2,1) is inverted becomes black display in the second ferroelectric state. Further, since Vreg to the signal lines _{Y 2} and _{Y 3} is applied, a potential difference V2 (> Vd) is generated in the pixel (2,2) and (2,3), the dielectric state white display not inverted Remains.

Similarly, in the second selection period f ₃ , the scanning line X ₃ is selected, and the pixels are rewritten for the pixels (3, 1), (3, 2), and (3, 3) on the scanning line X ₃ line. Is done. At this time, since the signal line Y ₃ V3 is applied, a potential difference V3 (<Vd) is generated in the pixel (3,3) is inverted becomes black display in the second ferroelectric state. Further, since Vreg to the signal lines _{Y 1} and _{Y 1} are applied, the potential difference V2 (> Vd) is generated in the pixel (3,1) and (3,2), the dielectric state white display not inverted Remains.

  FIG. 13 is a diagram showing a display state when the drive voltage waveform shown in FIG. 12 is applied.

  As shown in FIG. 13, four pixels of pixels (1, 1), (1, 2), (2, 1) and (3, 3) are displayed in black.

Although FIG. 12 and FIG. 13 show 3 × 3 pixels, since the liquid crystal panel 20 has 33 × 33 pixels, in the case of the entire display process, 33 scanning lines 13a are sequentially selected to rewrite all the pixels. Complete. That is, one frame period F of the liquid crystal panel 20 is composed of the reset periods RS and the selection periods f _{1 to} f _{33 of 33} . If the applied pulse width for causing the liquid crystal to perform one operation shown in FIG. 12 is “w (μs)”, in order to perform the entire display process in the liquid crystal panel 20, (1 + 33) × 2 × w = 68 × Only time w (μs) is required. Note that in the reset period RS, the entire display needs to be completely displayed in white or black, and therefore, the applied pulse width corresponding to the reset period RS takes a value of 1 or more. Further, w varies depending on the ambient temperature of the liquid crystal panel 20 and the applied voltage, as will be described later.

  As described above, in the reset period RS in which the reset operation is performed, a voltage is applied to all the scanning lines and signal lines in order to reset all the pixels, but a period other than the reset period within one frame period (drawing period) Then, a voltage is applied to the scanning line and the signal line corresponding to the pixel that needs to be rewritten.

  FIG. 14 is a diagram illustrating the relationship between the charging operation and the display operation.

  FIG. 14A shows the charging operation, where “H” indicates state 1 and “L” indicates state 2. FIG. 14B shows a display operation, where “H” indicates a display operation period and “L” indicates a non-display operation period.

  14, times T20 to T21 correspond to the initial state at times T0 to T1 in FIG. 2, and during this period, the booster circuit 1 charges the capacitors C1 to C7 with the power supply voltage VSS. In addition, time T21 to T22 is a waiting period, and during this period, the booster circuit 1 starts the boosting operation and repeatedly executes the operations of the state 1 and the state 2 so that each voltage line becomes a predetermined voltage. To do.

  Times T22 to T23 are rest periods, which correspond to between RS1 and RS2 and between f11 and f12 in FIG. 12, and set all the scanning lines 13a and all the signal lines 13b to the VDD (GND) potential, and the applied charge amount as much as possible. It is small. Further, during the idle period, the booster circuit 1 is set to the state 1.

  Times T23 to T24 correspond to immediately after the previous suspension period, and are periods during which charging for a drawing operation (including reset) is performed. Since the electric charge was discharged in the previous pause period, the amount of electric charge consumed is large when performing a new drawing, and the electric charge supply amount is most required during this period. The booster circuit 1 operates so that a sufficient charge is supplied by repeatedly executing the state 2 and the state 1 during the charging period immediately after the suspension period.

  From time T24 to T25, only the charge necessary for maintaining the state of the pixel may be supplied. Accordingly, since a large amount of charge supply is not required in this period compared to the reset period, the booster circuit 1 is controlled by the control unit 30 so that the cycle of repeatedly executing the state 2 and the state 1 is delayed. Is done. As described above, the booster circuit 1 is controlled by the control unit 30 in accordance with the display state (charging operation or holding operation), so that necessary electric charges can be supplied during a necessary period, and the power consumption as a whole is increased. Can be kept low. Thereafter, the pause / charge / hold operation is repeatedly executed.

  As described above, the state of charge operates in accordance with the display cycle (the pause period, the charging period, and the holding period). In other words, the booster circuit 1 is synchronized so that the charging states of the pumping capacitors C1 to C4 used for boosting are in the state 1 during the idle period. In addition, since the period in which the movement of charge is most intense is the charging period at the start of drawing, in the charging period immediately after the suspension period, the boosting operation (repeating state 1 and state 2) is frequently performed, and after a certain period of time has elapsed. The boosting operation cycle is controlled to be delayed or stopped. Note that, when the boosting operation is stopped, the boosting circuit 1 is preferably set to the state 1 because it is sufficiently charged.

1 is a circuit diagram showing an outline of a booster circuit according to the present invention. FIG. 4 is a diagram showing opening / closing timings in switches of the booster circuit 1. It is a figure for demonstrating operation | movement of the booster circuit 1 in an initial state. FIG. 6 is a diagram for explaining the operation of the booster circuit 1 in the state 1; FIG. 6 is a diagram for explaining the operation of the booster circuit 1 in a state 2; It is a figure for demonstrating boosting operation | movement of a booster circuit. 2 is a diagram illustrating a configuration example of a memory-type liquid crystal display panel 20 using a memory-type liquid crystal 10. FIG. It is a figure which shows sectional drawing of the liquid crystal panel and the auxiliary light source 60 which concern on this invention. FIG. 3 is a diagram illustrating an example of switching of the memory liquid crystal 10 in the liquid crystal panel 20. FIG. 2 is a diagram showing a schematic block configuration diagram of a liquid crystal display device 100. FIG. 3 is a diagram showing a part of pixels (3 × 3) of the liquid crystal panel 20. It is the figure which showed the processing flow in the authentication block of a mobile telephone. It is a figure which shows the display condition at the time of applying the drive voltage waveform shown in FIG. It is the figure which showed the relationship between charging operation and display operation.

Explanation of symbols

1 Booster Circuit 2 Power Supply 3 Constant Voltage Circuit 4 VDD Line 5 Vreg Line 6 VSS
7 V2
8 V3
10 memory type liquid crystal 20 liquid crystal panel 30 control unit

Claims (12)

A first power line having a first level;
A second power supply line having a second level different from the first level;
A reference power line having a reference level different from the first and second levels;
A plurality of boost capacitors;
A first switch group for connecting at least one of the plurality of boosting capacitors during the non-boosting operation between the first and second power supply lines;
A second switch group for connecting the plurality of boosting capacitors including a capacitor charged during a non-boosting operation during the boosting operation in parallel to the first power supply line and the reference power supply line;
A third switch group for connecting the plurality of boosting capacitors charged by parallel connection in series;
A booster circuit comprising:   2. The booster circuit according to claim 1, further comprising a constant voltage circuit that generates a voltage of the reference level using a voltage between the first and second power supply lines.   3. The booster circuit according to claim 2, further comprising a fourth switch disposed between the first power supply line or the second power supply line and the constant voltage circuit.   A controller that controls opening and closing of the first, second, and third switch groups, and generates a voltage that is an integral multiple of the reference level or a fraction of an integral number when the plurality of boost capacitors are connected in series; The booster circuit according to any one of claims 1 to 3.   The boosting circuit according to claim 3, wherein the control unit performs control so that the fourth switch is opened at the time of non-boosting. A first power line having a first level;
A second power supply line having a second level different from the first level;
A reference power line having a reference level different from the first and second levels;
A plurality of boost capacitors;
The plurality of boosting capacitors including a capacitor that is charged by connecting at least one of the plurality of boosting capacitors between the first and second power supply lines during the non-boosting operation and charged during the non-boosting operation during the boosting operation. Are connected in parallel to the first power supply line and the reference power supply line, and the plurality of boosted capacitors that are charged are connected in series to obtain a voltage that is an integral multiple of the reference level or a fraction of an integral multiple of the reference level. A control unit for generating
A booster circuit comprising: A constant voltage circuit for generating the reference level voltage using a voltage between the first and second power supply lines;
The booster circuit according to claim 6, wherein the control unit controls to stop the operation of the constant voltage circuit during a non-boosting operation. The plurality of boost capacitors include a first boost capacitor and a second boost capacitor;
The control unit connects the second boost capacitor in series and generates a voltage while charging the first boost capacitor connected to the first power supply line and the reference power supply line. A second state in which a voltage is generated by connecting the first boosting capacitor in series while charging the second boosting capacitor connected to the first power supply line and the reference power supply line. 9. The booster circuit according to claim 6 or 8, wherein a boost operation is performed to generate a voltage that is an integral multiple or a fraction of an integral number of the reference level so as to alternately occur.   9. The booster circuit according to claim 8, wherein the control unit varies a boosting operation for alternately generating the first state and the second state according to a state of a load to which the booster circuit supplies a voltage.   The booster circuit according to claim 1, further comprising a power supply for supplying the first and second levels.   The booster circuit according to claim 10, wherein the power source includes a power generation unit and a power storage unit. A memory type liquid crystal display device,
A display unit using memory liquid crystal, a first power line having a first level,
A second power supply line having a second level different from the first level;
A reference power line having a reference level different from the first and second levels;
A first boost capacitor;
A second boost capacitor;
During the non-boosting operation, at least one of the first and second boosting capacitors is connected between the first and second power supply lines to charge, and the first boosting capacitor is connected to the first power supply line and the first power supply line. A first state in which a voltage is generated by connecting the second boost capacitor in series while being connected to a reference power supply line, and the second boost capacitor is connected to the first power supply line and the reference power supply. A second state in which a voltage is generated by connecting the first boosting capacitors in series while being connected to a line and being alternately generated, is an integer multiple of the reference level or an integer fraction thereof. A control unit that performs a boosting operation that generates a double voltage, and
The control unit varies a boosting operation for alternately generating the first state and the second state according to a display state of the display unit.
A memory-type liquid crystal display device.

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