JP2007266128A - Semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is capable of coping with miniaturization and in which a leakage current is suppressed. <P>SOLUTION: The semiconductor device manufacturing method has a pillar forming step for forming a dummy pillar on a gate insulating film in a first conductive element forming region of a semiconductor substrate, a conductive-layer forming step for forming a conductive layer so as to cover the dummy pillar, an electrode forming step for forming an annular gate electrode around the dummy pillar by etching the conductive layer, a pillar removing step for removing the dummy pillar by etching, and an impurity dispersing step for forming second conductivity-type impurity dispersing regions respectively to the inside and the outside of the gate electrode in the element forming region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a field effect transistor and a method for manufacturing the semiconductor device.

  In recent years, as the demand for mobile devices such as mobile phones has increased, the market size of LSIs for mobile devices has rapidly expanded. Most mobile devices are battery powered, and wasteful power consumption requires a large battery capacity and shortens battery life. For this reason, it is desired that a semiconductor device such as an LSI incorporated in the mobile device has low power consumption in addition to high-speed operation.

  In order to reduce the power consumption of a semiconductor device including a transistor, it is preferable to reduce the leakage current of the transistor. For example, it is preferable to reduce the leakage current during standby.

  FIG. 1 is a diagram for explaining a leakage current during standby of a MOS transistor. Referring to FIG. 1, the MOS transistor has a source region 2 and a drain region 3 formed in an element formation region (active region) 1 of a substrate. On the channel between the source region 2 and the drain region 3, a gate electrode 5 is formed via a gate insulating film 4.

  For example, the leakage current components include subthreshold leakage (IS) flowing from the drain region 3 to the source region 2 side, substrate current (IB) flowing from the drain region 3 to the substrate (element formation region 1) side, and from the substrate side. Three types of gate leak (IG) flowing in the gate region 5 are known. Further, the IB component flowing from the drain region 3 to the substrate side includes a high bias generated at the end of the drain region formed between the reverse bias leak component of the pn junction between the drain region and the substrate and the end of the drain region near the gate. There is a gate induced drain leakage (GIDL) induced by depletion or inversion of the end of the drain region by an electric field.

Suppressing these leakage currents is important for realizing low power consumption of the semiconductor device.
Japanese Patent No. 3203733 JP-A-9-331481 Japanese Patent No. 3276325 US Pat. No. 5,689,129 US Pat. No. 5,355,008

  However, in the conventional MOS transistor, it may be difficult to suppress the leakage current due to a structural problem.

  FIG. 2 is a cross-sectional view of the MOS transistor of FIG. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. Referring to FIG. 2, the element formation region 1 is separated and formed by an element isolation (STI) insulating groove 6. The gate electrode 5 is formed so that a part thereof covers the element isolation insulating groove 6.

  In the above structure, the insulating film may be thinned at the end portion (region B in the drawing) of the element formation region (active region) 1. In addition, there is a problem that the occurrence of leakage current increases at the end portion because electric field concentration may occur.

  In addition, such a leakage current at the end of the element formation region may become a larger problem when the element formation region is narrowed. For this reason, difficulty has arisen in miniaturization of a transistor.

  For example, the IS component and the IB component of the leakage current shown in FIG. 1 are not uniform in the element formation region, but are large at the end of the element formation region. The problem becomes more serious.

  In view of this, the present invention has a general object to provide a new and useful semiconductor device and a method for manufacturing the semiconductor device, which solve the above-described problems.

  A specific problem of the present invention is to manufacture a semiconductor device that can cope with miniaturization and suppresses leakage current, and a semiconductor device that can cope with miniaturization and suppresses leakage current. It is to provide a manufacturing method.

  In the first aspect of the present invention, the above-described problems are solved by a first conductive type element forming region of a semiconductor substrate, an annular gate electrode formed on a gate insulating film on the element forming region, and the element. A first conductivity type first region formed inside the gate electrode in the formation region; a second conductivity type second region formed outside the gate electrode in the element formation region; The semiconductor device has a gate lead-out wiring formed integrally with the gate electrode, and the thickness of the annular portion of the gate electrode is smaller than the width of the gate lead-out wiring.

  According to the present invention, it is possible to provide a semiconductor device that can cope with miniaturization and suppresses a leakage current.

  In the viewpoint of the present invention, the above-described problems are solved by forming a pillar on the gate insulating film in the element formation region of the first conductivity type of the semiconductor substrate, and forming a conductive layer so as to cover the dummy pillar. A conductive layer forming step; an electrode forming step of etching the conductive layer to form an annular gate electrode around the dummy pillar; a pillar removing step of removing the dummy pillar by etching; and This is solved by a method for manufacturing a semiconductor device, comprising: an impurity diffusion step of forming impurity diffusion regions of a second conductivity type on the inside and outside of the gate electrode, respectively.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the manufacturing method which can respond to refinement | miniaturization and manufactures the semiconductor device with which leakage current was suppressed.

  According to the present invention, there are provided a semiconductor device that can cope with miniaturization and suppresses a leakage current, and a manufacturing method for manufacturing a semiconductor device that can cope with miniaturization and suppresses a leakage current. It becomes possible to provide.

  The semiconductor device according to the present invention includes a first conductivity type element forming region of a semiconductor substrate, an annular gate electrode formed on a gate insulating film on the element forming region, and the gate electrode in the element forming region. A first conductivity type first region formed on the inside of the device, a second conductivity type second region formed outside the gate electrode in the element formation region, and the gate electrode. And the thickness of the annular portion of the gate electrode is smaller than the width of the gate lead-out line.

  In the semiconductor device described above, since the gate electrode is formed in an annular shape, the leakage current can be suppressed as compared with the conventional semiconductor device having a structure in which the gate electrode crosses the element formation region.

  For example, in the conventional semiconductor device, since the gate electrode crosses the element formation region (active region), in the vicinity of the end of the gate electrode and the end of the element isolation insulating groove formed outside the element formation region There was a problem that the leakage current increased.

  Therefore, in the semiconductor device according to the present invention, the annular gate electrode is used so that the gate electrode is separated from the element isolation insulating groove formed outside the element formation region. For this reason, it is possible to reduce the leakage current caused by the interface between the gate electrode and the end portion of the element isolation insulating groove (end portion of the element formation region).

  For example, the IS component and the IB component of the leakage current shown in FIG. 1 are not uniform in the element formation region, but are large at the end of the element formation region (near the element isolation insulating groove), and particularly the width of the element formation region. With a small transistor, the problem of leakage current becomes large.

  On the other hand, in the semiconductor device according to the present invention, it is possible to reduce the leakage current related to the IS component and the IB component at the end of the element formation region (near the element isolation insulating groove). Therefore, it is possible to provide a semiconductor device having a fine structure with reduced leakage current.

  In addition, in the above Patent Document 1 to Patent Document 5 (Japanese Patent No. 3203733, Japanese Patent Laid-Open No. 9-331481, Japanese Patent No. 3276325, US Pat. No. 5,689,129, US Pat. A used semiconductor device is disclosed.

  However, the above Patent Documents 1 to 5 do not disclose a specific structure and method for miniaturizing a semiconductor device.

  On the other hand, in the present invention, the thickness of the annular portion of the gate electrode is smaller than the width of the gate lead wiring formed integrally with the gate electrode. For this reason, according to the present invention, it is possible to provide a miniaturized semiconductor device having a finely shaped gate electrode.

  The inventor of the present invention forms the above-described miniaturized gate electrode by forming a film on the dummy pillar using a dummy pillar, and then etching and patterning the formed film. I found out that it would be possible.

  For example, in the semiconductor device, a pillar forming step of forming a dummy pillar on a gate insulating film in an element formation region of a first conductivity type of a semiconductor substrate, and a conductive layer forming step of forming a conductive layer so as to cover the dummy pillar An electrode forming step of etching the conductive layer to form an annular gate electrode around the dummy pillar, a pillar removing step of removing the dummy pillar by etching, and the element forming region inside the gate electrode And an impurity diffusion step for forming an impurity diffusion region of the second conductivity type on the outside, respectively.

  By using the above manufacturing method, it becomes possible to form a finer annular gate electrode than in the case where the annular gate electrode is formed by a normal lithography method. For example, the thickness of the annular portion and the diameter of the annular portion can be reduced as compared with the conventional case, and the semiconductor device can be miniaturized.

  Next, an example of a configuration of the semiconductor device and an example of a manufacturing method thereof will be described below with reference to the drawings.

  FIGS. 3A and 3B are diagrams schematically showing the semiconductor device according to the first embodiment of the present invention, in which FIG. 3A is a plan view and FIG. It is a figure which shows sectional drawing.

  3A and 3B, in the semiconductor device 100 according to the present embodiment, an element formation region (active field) formed in the semiconductor substrate 101 by being separated by an element isolation (STI) insulating groove 102. 103 has a structure in which a MOS transistor is formed. The MOS transistor has a structure described below.

  A gate insulating film 106 is formed on the element region 103 of the first conductivity type, and an annular gate electrode 107 having a sidewall insulating film 108 is formed on the gate insulating film 106.

  In the element formation region 103, an impurity diffusion region of the second conductivity type is formed as follows. First, an impurity diffusion region (drain region) 105 having a low concentration impurity diffusion region (LDD) 105A and a high concentration impurity diffusion region (DDD) 105B is formed inside the gate electrode 107. Similarly, an impurity diffusion region (source region) 104 having a low concentration impurity diffusion region (LDD) 104A and a high concentration impurity diffusion region (DDD) 104B is formed outside the gate electrode 107.

  Further, a gate lead-out wiring (local wiring) 109 connected to the gate electrode 107 is formed integrally with the gate electrode 107. The gate lead-out wiring 109 is used, for example, when connecting a plurality of gate electrodes, and is connected to other gate electrodes (both not shown) of other element formation regions formed adjacent to each other.

  The semiconductor device according to the present embodiment is characterized in that the annular gate electrode 107 is used so that the gate electrode 107 and the element isolation insulating groove 102 (the end of the element formation region 103) are separated from each other. It is. Therefore, leakage current can be suppressed, and a low power consumption type semiconductor device can be realized.

  For example, FIG. 4 shows a plan view of a conventional semiconductor device (MOS transistor). In the MOS transistor shown in FIG. 4, the gate electrode 17 is formed so as to cross the element formation region 13. Therefore, at the end of the element formation region 13 (region L in the figure), in addition to the IG component of the leakage current (gate leakage flowing from the substrate side to the gate electrode 5), the IS component (flowing from the drain region to the source region side). Subthreshold leakage) and IB component (substrate current flowing from the drain to the substrate side) increase.

  On the other hand, in the semiconductor device 100 according to the present embodiment, as shown in FIGS. 3A and 3B, the gate electrode does not cover the end portion (element isolation insulating groove) of the element formation region. Leakage current can be reduced. In this case, for example, a gate lead line to which a gate voltage is applied is outside the element formation region, while a region (channel) in which carriers move between the source region and the drain region is the end of the element formation region. It is separated from the part. For this reason, it is possible to reduce the IS component and the IB component of the leakage current as compared with the conventional semiconductor device.

  Further, in the semiconductor device 100 according to the present embodiment, an impurity diffusion region having the first conductivity type (the same conductivity type as the element formation region) and having an impurity concentration higher than that of the element formation region 103 is provided in the vicinity of the source region 104. A certain pocket region 120 is formed.

  The addition of impurities introduced into the pocket region 120 makes it possible to control the threshold voltage of the transistor. For this purpose, the drain region 105 (the low-concentration impurity) is reduced by reducing the impurity concentration in the vicinity of the drain region 105. It is possible to suppress the leakage current (IB component) generated in the vicinity of the diffusion region 105A).

  In the semiconductor device 100 according to this embodiment, the thickness T of the annular portion of the gate electrode 107 is configured to be smaller than the width W of the gate lead-out wiring 109. Therefore, it is possible to miniaturize the semiconductor device, and it is possible to provide a highly integrated and high performance semiconductor device.

  Conventionally, for example, pattern etching using a mask pattern formed by lithography has made it difficult to form a miniaturized annular gate electrode. In the semiconductor device according to the present embodiment, the thickness of the annular portion of the gate electrode 107 can be less than the lower limit thickness of patterning by photolithography, and the semiconductor device can be miniaturized.

  The miniaturized gate electrode can be formed, for example, by forming a film on the dummy pillar using a dummy pillar, and then etching and patterning the formed film.

  For example, first, after forming a dummy pillar on the gate insulating film on the element formation region, a film that is a material constituting the gate electrode is formed so as to bury the dummy pillar. Next, by removing the film in which the dummy pillar is embedded by anisotropic plasma etching such as RIE, an annular gate electrode can be formed around the dummy pillar. In this case, if the diameter (width) of the dummy pillar is set to a lower limit size that can be patterned by photolithography, the thickness of the annular portion of the formed gate electrode is set to the lower limit size that can be formed by photolithography. It can be less than this.

  That is, according to the above method, it is possible to pattern an annular gate electrode having a finer structure than in a normal photolithography method.

  Next, an example of a method for manufacturing the semiconductor device 100 including the above-described gate electrode patterning step will be described step by step with reference to FIGS. However, in the following drawings, the same reference numerals are given to the parts described above, and the description may be omitted.

First, in the process shown in FIG. 5, the element isolation insulating groove 102 is formed in the substrate 101 made of, for example, silicon, and the gate insulating film 106 is formed on the element forming region 103 isolated by the element isolation insulating groove 102. . The gate insulating film 106 includes, for example, a silicon oxide film (SiO ₂ ), a silicon oxynitride film (SiON), a ferroelectric metal oxide (Hf _x O _y , Zr _n O _m , Hf _x Si _y O _z , _{Zr x Si y O z, Hf} x Si y O z N w, Zr x Si y O z N w), or is formed by a laminated film thereof.

  Next, FIG. 6A is a plan view of the manufacturing process of the semiconductor device subsequent to FIG. 5, and FIG. 6B is a cross-sectional view taken along DD of FIG. In FIG. 6B, the element isolation insulating groove is not shown. Hereinafter, it illustrates similarly in FIGS.

  In the steps shown in FIGS. 6A and 6B, a film serving as a material constituting the dummy pillar is first formed on the gate insulating film 106. Thereafter, a resist pattern is formed by photolithography, and etching using the resist pattern as a mask is performed to form the dummy pillar 110.

  The diameter (width) of the dummy pillar 110 is preferably the minimum diameter (width) formed by a photolithography method. In this case, the gate electrode formed in a later step can be further miniaturized (for example, smaller than a lower limit dimension that is a processing limit of the photolithography method).

  Next, in the steps shown in FIGS. 7A and 7B, a conductive layer 111 made of polysilicon which is a material constituting the gate electrode is formed on the gate insulating film 106 so as to cover the dummy pillar 110. To do. In this case, the conductive layer 111 has a shape that rises around the dummy pillar 110.

  Next, in the steps shown in FIGS. 8A and 8B, a planarizing layer 112 for planarizing the upper surface of the conductive layer 111 is formed by, for example, coating (spin coating or the like). Providing this step facilitates resist patterning in a later step, but this step can be omitted.

  Next, in a process shown in FIGS. 9A and 9B, a resist pattern 113 is formed on the planarizing layer 112 by using a photolithography method.

  Next, in the steps shown in FIGS. 10A and 10B, the conductive layer 111 is etched and patterned by anisotropic etching such as RIE (reactive ion etching), for example. An annular gate electrode 107 is formed around the periphery. Along with the gate electrode 107, a gate lead line 109 is formed by patterning integrally with the gate electrode 107. In this case, the gate lead line 109 is formed in a shape corresponding to the resist pattern 113 formed in the process shown in FIG.

  In this step, when the gate electrode 107 is patterned, a patterned mask is not particularly used, and the shape (thickness) of the gate electrode 107 is controlled according to the etching conditions.

  Next, in the step shown in FIGS. 11A and 11B, the dummy pillar 110 is removed by etching. In this case, it is preferable that the etching selectivity between the gate electrode 107 and the dummy pillar 110 and the etching selectivity between the gate insulating film 106 and the dummy pillar 110 are large. For this reason, it is preferable that the gate insulating film, the gate electrode, and the dummy pillar are made of materials in consideration of these selection ratios.

For example, the gate insulating film 106, the metal oxide is a high-dielectric material _{(Hf x O y, Zr n} O m, Hf x Si y O z, Zr x Si y O z, Hf x Si y O z N _w, when consisting of _{Zr x Si y O z N w} ) , the dummy pillar 110 is preferably made of SiO _2. When the gate insulating film 106 is made of SiO ₂ or SiON, the dummy pillar 110 is preferably made of a metal material (for example, Al).

  In this step, an annular gate electrode 107 and a gate lead line 109 are formed. In the above structure, the thickness T of the annular portion of the gate electrode 107 is smaller than the width W of the gate lead-out wiring 109. Also, the thickness T of the annular portion of the gate electrode 107 is less than the lower limit thickness of patterning by photolithography.

  Further, the gate electrode 107 made of polysilicon may be subjected to self-forming silicide treatment to lower the gate resistance. Further, the gate electrode (gate lead line 109) is not limited to polysilicon, and can be formed using a metal material such as Al.

  Next, in the steps shown in FIGS. 12A and 12B, impurities (ions) having a conductivity type opposite to that of the element formation region 103 are implanted using the gate electrode 107 as a mask. Here, in the element formation region 103, a low concentration impurity diffusion region (LDD) 105A is formed inside the gate electrode 107, and a low concentration impurity diffusion region 104A is formed outside the gate electrode 107.

  Next, in the steps shown in FIGS. 13A and 13B, impurities (ions) having the same conductivity type as that of the element formation region 103 are introduced from the outside of the gate electrode 107 to the element formation region 103 (the gate insulating film). 106). Here, a pocket region 120 is formed, and a threshold voltage is controlled by an impurity introduced into the pocket region 120.

Next, in the steps shown in FIGS. 14A and 14B, a sidewall insulating film 108 is formed on the sidewall of the gate electrode 107. The sidewall insulating film 108 is preferably formed also on the upper end portion of the gate electrode 107. In this case, it is possible to prevent a short circuit between the gate electrode and the wiring that contacts the inside of the gate electrode 107. Further, when forming the sidewall insulating film 108, two insulating films having different compositions (for example, SiO ₂ and SiN) may be used. A method for forming these sidewall insulating films will be described later.

  Next, in the steps shown in FIGS. 15A and 15B, impurities (ions) having a conductivity type opposite to that of the element formation region 103 are implanted using the gate electrode 107 and the sidewall insulating film 108 as a mask. . Therefore, in the element formation region 103, a high concentration impurity diffusion region 105B is formed inside the gate electrode 107, and a high concentration impurity diffusion region 104B is formed outside the gate electrode 107. As a result, a drain region 105 having a low concentration impurity diffusion region 105A and a high concentration impurity diffusion region 105B is formed inside the gate electrode 107. Similarly, a source region 104 having a low concentration impurity diffusion region 104A and a high concentration impurity diffusion region 104B is formed outside the gate electrode 107.

  In this manner, the semiconductor device 100 described with reference to FIGS. 3A and 3B can be manufactured.

  In the case of forming a sidewall insulating film on the gate electrode, the following method shown in FIGS. 16A to 16C may be used.

  FIG. 16A to FIG. 16C are diagrams showing an example of a process corresponding to FIG. 14 in the above manufacturing method, and showing an example of another method of forming a sidewall insulating film on the gate electrode 107. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  First, in the step shown in FIG. 16A, for example, an insulating film 121 made of SiN is formed so as to cover the gate electrode 107.

Next, in a step shown in FIG. 16B, an insulating film 122 made of, for example, SiO ₂ having a composition different from that of the insulating film 121 is formed on the insulating film 121.

  Next, in the step shown in FIG. 16C, the insulating film 122 is mainly etched by, for example, RIE, and a part of the insulating film 122 is removed to form a sidewall insulating film. In this case, it is preferable to perform etching so that the insulating film 121 remains at the upper end of the gate electrode 107. In addition, it is preferable that the etching selectivity between the insulating film 121 and the insulating film 122 is large because it is easy to leave the insulating film 121 on the upper end of the gate electrode 107.

  FIG. 17 is a plan view showing a semiconductor device 300 having a CMOS inverter circuit including the semiconductor device (MOS transistor) described in the first embodiment. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 17, the semiconductor device 300 shown in the figure includes a semiconductor device (PMOS transistor) 100 having the same structure as that of the first embodiment, and a semiconductor device 200 (NMOS transistor) having a polarity different from that of the semiconductor device 100. Are formed adjacent to each other. The semiconductor device 200 has the same structure as that of the semiconductor device 100 of the first embodiment, and has a different polarity (conductivity type). In the semiconductor device 200, a gate electrode 207 corresponding to the gate electrode 107 is formed on an element forming region 203 corresponding to the element forming region 103, and a sidewall insulating film 208 is formed. The gate electrode 107 and the gate electrode 207 are connected by the gate electrode lead line 109. In this case, the semiconductor device 200 can be manufactured by the same manufacturing method as the semiconductor device 100 (FIGS. 5 to 15).

  In the semiconductor device 300 described above, the lead-out line a connected to the input line is connected to the gate lead-out line 109. A common lead line b connected to an output line is connected to the drain region inside the gate electrode 107 of the semiconductor device 100 and the drain region inside the gate electrode 207 of the semiconductor device 200. Yes.

  In addition, in the source region outside the gate electrode 107 of the semiconductor device 100, a lead line c connected to a power supply line is connected to the ground line in the source region outside the gate electrode 207 of the semiconductor device 200. The connected lead lines d are connected to each other.

  As described above, the semiconductor device according to the present invention can be configured by combining various polarities.

  FIG. 18 is a plan view showing a semiconductor device 400 having a NAND circuit including the semiconductor device (MOS transistor) described in the first embodiment. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 18, a semiconductor device 400 shown in the drawing includes two semiconductor devices (PMOS transistors) 100 and two semiconductor devices 200 (NMOS transistors). In the case of this embodiment, two structures in which the gate electrode 107 and the gate electrode 207 are connected by the gate electrode lead-out line 109 are formed.

  In the semiconductor device 400, the two gate lead lines 109 are connected to the lead line e1 connected to the first input line and the lead line e2 connected to the second input line, respectively.

  In addition, a common lead line f connected to an output line is connected to a region inside the gate electrode 107 of two semiconductor devices 100 and a region of the gate electrode 207 of one semiconductor device 200. Yes.

  A lead line h connected to a ground line is connected to a region inside the gate electrode 207 of the semiconductor device 200 to which the lead line f is not connected. In addition, a lead line g connected to a power supply line is connected to a region outside the gate electrode 107 of the semiconductor device 100.

  FIG. 19 is a plan view of a semiconductor device 500 which is a modification of the semiconductor device 400 described above. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 19, in the semiconductor device 500, the gate electrode 107A corresponding to the gate electrode 107 has an elliptical ring shape when seen in a plan view, and the sidewall insulating film 108A also has a shape corresponding thereto. It has become. Further, the gate electrode 207A corresponding to the gate electrode 207 has an elliptical annular shape different from the gate electrode 107A in plan view, and the sidewall insulating film 208A also has a shape corresponding thereto. .

  Thus, the gate electrode is not limited to an annular shape corresponding to a substantially perfect circle, and can be formed in various shapes such as an ellipse and other polygons when viewed in plan. When such a gate electrode is formed, a dummy pillar having a shape corresponding to each gate electrode may be used.

  Further, a circuit using a semiconductor device is not limited to the above, and it is apparent that various structures can be employed. For example, the number of MOS transistors (gate electrodes), their connection form, or arrangement can be variously changed.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications and changes can be made within the scope described in the claims.
(Appendix 1)
An element formation region of a first conductivity type of a semiconductor substrate;
An annular gate electrode formed on the gate insulating film on the element formation region;
A first region of a second conductivity type formed inside the gate electrode of the element formation region;
A second region of the second conductivity type formed outside the gate electrode in the element formation region;
A gate lead wiring formed integrally with the gate electrode,
The semiconductor device according to claim 1, wherein a thickness of the annular portion of the gate electrode is smaller than a width of the gate lead-out wiring.
(Appendix 2)
2. The semiconductor device according to claim 1, wherein a thickness of the annular portion of the gate electrode is less than a lower limit thickness of patterning by a photolithography method.
(Appendix 3)
3. The semiconductor device according to claim 1, wherein a pocket region of a first conductivity type for controlling a threshold voltage is formed in the vicinity of the second region of the element formation region.
(Appendix 4)
The semiconductor device according to claim 2, wherein the first region is a drain region, and the second region is a source region.
(Appendix 5)
In the semiconductor substrate, another element formation region that is separated from the element formation region by an element isolation insulating groove is formed,
On the other gate insulating film in the other element isolation formation region, another annular gate electrode is formed,
5. The semiconductor device according to claim 1, wherein the gate electrode and the another gate electrode are connected by the gate lead-out line. 6.
(Appendix 6)
A pillar forming step of forming a dummy pillar on the gate insulating film in the first conductivity type element forming region of the semiconductor substrate;
A conductive layer forming step of forming a conductive layer so as to cover the dummy pillar;
Etching the conductive layer to form an annular gate electrode around the dummy pillar; and
A pillar removing step of removing the dummy pillar by etching;
A method of manufacturing a semiconductor device, comprising: forming an impurity diffusion region of a second conductivity type inside and outside the gate electrode of the element formation region.
(Appendix 7)
After the conductive layer forming step, the method further includes a mask forming step of forming a resist pattern that serves as an etching mask for the conductive layer,
7. The method of manufacturing a semiconductor device according to claim 6, wherein in the etching step, a gate lead line connected to the gate electrode is formed corresponding to the resist pattern.
(Appendix 8)
After the conductive layer forming step, the method further includes a step of forming a planarization layer for planarizing the conductive layer on the conductive layer, and the resist pattern is formed on the planarization layer. Item 8. The method for manufacturing a semiconductor device according to appendix 7, which is characterized by the following.
(Appendix 9)
The method further includes the step of forming a pocket region of the first conductivity type for controlling the threshold voltage by implanting ions obliquely from the outside of the gate electrode to the element formation region. The manufacturing method of the semiconductor device of any one of 6 thru | or 8.
(Appendix 10)
An insulating film forming step of forming an insulating film on the side wall and the upper end of the gate electrode;
The insulating film forming step includes
Forming a first insulating film on the gate electrode;
Forming a second insulating film having a composition different from that of the first insulating film on the first insulating film;
The method of manufacturing a semiconductor device according to any one of appendices 6 to 9, further comprising: etching the second insulating film.
(Appendix 11)
11. The method of manufacturing a semiconductor device according to appendix 10, wherein the first insulating film is made of a silicon nitride film, and the second insulating film is made of a silicon oxide film.
(Appendix 12)
12. The method of manufacturing a semiconductor device according to any one of appendices 6 to 11, wherein the conductive layer is made of polysilicon and includes a step of siliciding the polysilicon.
(Appendix 13)
A plurality of the element formation region and the gate electrode are formed,
13. The method of manufacturing a semiconductor device according to any one of appendices 7 to 12, wherein a plurality of the gate electrodes are connected by the gate lead line.

  According to the present invention, there are provided a semiconductor device that can cope with miniaturization and suppresses a leakage current, and a manufacturing method for manufacturing a semiconductor device that can cope with miniaturization and suppresses a leakage current. It becomes possible to provide.

It is a figure which shows the leakage current of a MOS transistor. It is a figure which shows the cross section of the gate of a MOS transistor. (A), (B) is a figure which shows the semiconductor device by Example 1. FIG. It is a figure which shows the problem of the conventional MOS transistor. FIG. 3 is a diagram (No. 1) for illustrating a method for manufacturing a semiconductor device according to Example 1; (A), (B) is a figure (the 2) which shows the manufacturing method of the semiconductor device by Example 1. FIG. (A), (B) is a figure (the 3) which shows the manufacturing method of the semiconductor device by Example 1. FIG. (A), (B) is a figure (the 4) which shows the manufacturing method of the semiconductor device by Example 1. FIG. (A), (B) is a figure (the 5) which shows the manufacturing method of the semiconductor device by Example 1. FIG. (A), (B) is a figure (the 6) which shows the manufacturing method of the semiconductor device by Example 1. FIG. (A), (B) is a figure (the 7) which shows the manufacturing method of the semiconductor device by Example 1. FIGS. (A), (B) is a figure (the 8) which shows the manufacturing method of the semiconductor device by Example 1. FIG. (A), (B) is a figure (the 9) which shows the manufacturing method of the semiconductor device by Example 1. FIG. (A), (B) is a figure (the 10) which shows the manufacturing method of the semiconductor device by Example 1. FIG. (A), (B) is a figure (the 11) which shows the manufacturing method of the semiconductor device by Example 1. FIG. FIG. 11 is a diagram (No. 1) illustrating a modification of the method for fabricating a semiconductor device according to the first embodiment; FIG. 11 is a diagram (No. 2) illustrating a modification of the semiconductor device manufacturing method according to the first embodiment; FIG. 11 is a third diagram illustrating a variation of the method for fabricating a semiconductor device according to the first embodiment; 6 is a diagram showing a semiconductor device according to Example 2. FIG. 6 is a diagram showing a semiconductor device according to Example 3. FIG. 18 is a modification of the semiconductor device of FIG.

Explanation of symbols

100, 200, 300, 400, 500 Semiconductor device 101 Semiconductor substrate 102 Element isolation insulating groove 103, 203 Element formation region 104 Source region 104A Low concentration impurity diffusion region 104B High concentration impurity diffusion region 105 Drain region 105A Low concentration impurity diffusion region 105B High concentration impurity diffusion region 106 Gate insulating film 107, 107A, 207, 207A Gate electrode 108, 108A, 208, 208A Side wall insulating film 109 Gate lead line 110 Dummy pillar 111 Conductive layer 112 Planarizing layer 113 Resist pattern 120 Pocket region 121, 122 Insulation film

Claims (5)

An element formation region of a first conductivity type of a semiconductor substrate;
An annular gate electrode formed on the gate insulating film on the element formation region;
A first region of a second conductivity type formed inside the gate electrode of the element formation region;
A second region of the second conductivity type formed outside the gate electrode in the element formation region;
A gate lead wiring formed integrally with the gate electrode,
The semiconductor device according to claim 1, wherein a thickness of the annular portion of the gate electrode is smaller than a width of the gate lead-out wiring. In the semiconductor substrate, another element formation region that is separated from the element formation region by an element isolation insulating groove is formed,
On the other gate insulating film in the other element isolation formation region, another annular gate electrode is formed,
2. The semiconductor device according to claim 1, wherein the gate electrode and the another gate electrode are connected by the gate lead-out line. A pillar forming step of forming a dummy pillar on the gate insulating film in the first conductivity type element forming region of the semiconductor substrate;
A conductive layer forming step of forming a conductive layer so as to cover the dummy pillar;
Etching the conductive layer to form an annular gate electrode around the dummy pillar; and
A pillar removing step of removing the dummy pillar by etching;
A method of manufacturing a semiconductor device, comprising: forming an impurity diffusion region of a second conductivity type inside and outside the gate electrode of the element formation region. After the conductive layer forming step, the method further includes a mask forming step of forming a resist pattern that serves as an etching mask for the conductive layer,
4. The method of manufacturing a semiconductor device according to claim 3, wherein in the etching step, a gate lead line connected to the gate electrode is formed corresponding to the resist pattern. A plurality of the element formation region and the gate electrode are formed,
5. The method of manufacturing a semiconductor device according to claim 3, wherein the plurality of gate electrodes are connected by the gate lead lines.

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