JP2007265239A - Electronic equipment and data communication equipment thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide data communication equipment capable of highly accurately adjusting an amount of delay inexpensively, that is, performing timing adjustment. <P>SOLUTION: The data communication equipment for transmitting and receiving data synchronized with a clock to/from an external device 2 is provided with a reference clock generating means 12 for dividing the frequency of a source clock of a high frequency and generating and outputting a reference clock, a clock delaying means 13 for capturing the reference clock and composed of shift registers 13a to 13m of a plurality of cascaded steps and generating and outputting a delay reference clock delayed by the predetermined amount of delay, a clock outputting means 14 for outputting to the external device 2 a clock output from one of the means 12 and 13, and a data inputting means 15 operated by a clock output from the other of the means 12 and 13 to receive data read from the external device 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data communication apparatus that performs data transmission / reception interface processing between a data processing unit of an electronic device and an external device.

  Recent electronic devices such as mobile phones, digital cameras, personal computers, PDAs (personal digital assistants), and television receivers are equipped with a memory card loading unit to read data stored in the memory card and store new data in memory. You can write on the card.

  For this reason, such an electronic device is provided with a data communication device that transmits and receives data while synchronizing with a memory card that is an external device. If the data communication device has only one type of memory card to be installed, a timing adjustment circuit corresponding to the clock delay amount or data delay amount specific to the memory card may be provided.

  However, there are multiple types of memory cards (SD cards, MMC cards, xD cards, memory sticks, smart media, compact flash, etc., identified by registered trade names) among current memory cards, and there are many types of electronic devices. It is necessary to correspond to each of the memory cards. However, different types of memory cards have slightly different clock delay amounts, and there are differences that cannot be ignored even between memory cards that are considered compatible.

  For this reason, in the prior art described in Patent Document 1, a plurality of stages of time constant circuits (delay circuits) made up of resistive elements and capacitive elements are provided in a data communication device made up of a semiconductor integrated circuit, and the amount of clock delay is used. Adjustment is made with the number of stages of the time constant circuit.

JP 2004-355163 A

  A circuit that is finely formed in a semiconductor integrated circuit and performs an analog operation is generally unstable in operation, and semiconductor elements constituting the circuit also have large variations in characteristics. For this reason, in order to obtain a stable delay amount with a delay circuit made of a resistor element and a capacitor element in the semiconductor integrated circuit, it is necessary to manufacture the semiconductor integrated circuit with high accuracy, and the manufacturing cost increases.

  An object of the present invention is to provide a data communication apparatus capable of adjusting a delay amount, that is, a timing adjustment accurately and inexpensively, and an electronic apparatus including the data communication apparatus.

  A data communication apparatus according to the present invention includes a reference clock generation means for generating and outputting a reference clock by dividing a high-frequency original clock in a data communication apparatus that performs data transmission / reception synchronized with a clock with an external device, and a cascade A clock delay unit configured by a plurality of shift registers connected to generate and output a delayed reference clock obtained by taking in the reference clock and delayed by a predetermined delay amount; and output from one of the reference clock generation unit and the clock delay unit A clock output means for outputting the reference clock or the delayed reference clock to the external device, and the reference clock or the delayed reference clock output from the other of the reference clock generating means and the clock delay means. Data to receive data read from external equipment Characterized in that it comprises a power means.

  The data communication apparatus of the present invention is characterized by comprising selector means for taking in parallel the outputs of the shift registers constituting the clock delay means and selecting one of them and outputting it as the delay reference clock.

  The data communication apparatus of the present invention is characterized in that the shift register is driven by the original clock.

  The data communication apparatus according to the present invention includes data output means for delaying data to be transmitted to the external device and transmitting the data to the external device.

  The data communication apparatus of the present invention is characterized in that output data is delayed by driving the data output means with an output clock of the clock delay means.

  In the data communication apparatus of the present invention, the output data is delayed by delaying the reference clock by a delay means different from the clock delay means, and driving the data output means by an output clock of the delay means. Features.

  The data communication apparatus according to the present invention is characterized in that the clock output means outputs the delay reference clock to the external device.

  The data communication apparatus according to the present invention includes a monitor terminal for the reference clock.

  The data communication apparatus according to the present invention is characterized in that the clock output means outputs the reference clock to the external device.

  An electronic apparatus according to the present invention includes any of the data communication apparatuses described above in an input / output interface unit.

  The electronic apparatus according to the present invention is characterized in that the external device is a memory card.

  According to the present invention, since the delay amount control is performed by the shift register, even if there is a variation in the characteristics of the individual circuit elements constituting the shift register, the operation of the shift register is not affected by the variation, and the accuracy is improved. High delay amount control is possible. In addition, even when a data communication device is constituted by a semiconductor integrated circuit, it can be manufactured while allowing variation in characteristics of circuit elements, and the manufacturing cost is reduced.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a main part configuration diagram of an electronic device according to a first embodiment of the present invention. This electronic device includes a data processing device main body 1 and a data communication device 3 that performs data transmission / reception interface processing between a memory card 2 that is detachably attached to a card attachment portion (not shown) of the electronic device.

  The data communication device 3 divides an original clock supply source 11 formed of a PLL (phase locked loop) circuit and a high-frequency original clock output from the original clock supply source 11 into 1 / N and uses the divided clock as a reference clock. A frequency dividing circuit 12 for outputting, a delay circuit 13 for generating and outputting a delay reference clock by giving a predetermined delay amount to the reference clock, and an output for outputting the delay reference clock output from the delay circuit 13 to the memory card 2 The driver 14 includes an input register 15 that receives data read from the memory card 2 in synchronization with the received delay reference clock and outputs the data to the data processing apparatus main body 1.

  The frequency of the interface reference clock may be changed. For this reason, the high-frequency original clock is divided by the frequency dividing circuit 12 to generate the reference clock.

  The delay circuit 13 of this embodiment is configured by cascading a predetermined number, for example, m (m is a positive integer) shift registers 13a, 13b,..., 13m, and each shift register 13a, 13b,. Driven by a high frequency original clock.

  When the reference clock input to the delay circuit 13 is output from the first-stage shift register 13a, it is delayed by one original clock and taken into the second-stage shift register 13b, and the second-stage shift register 13b. The process of further delaying by one original clock is repeated.

  Therefore, the reference clock output from the m-th shift register 13m is a clock in which a delay amount of m original clocks is given to the input reference clock (output clock of the frequency dividing circuit 12).

  The input register 15 captures data at the timing of the reference clock before the delay by the delay circuit 13, that is, the frequency-divided clock output from the frequency-dividing circuit 12, and outputs the received data to the data processing device main body 1 side.

  With such a configuration, a reference clock delayed from the data communication device 3 is given to the memory card 2 which is an external device of the electronic device, and data is read from the memory card 2 in synchronization with the delay reference clock. The data read from the memory card 2 is taken into the input register 15 and output from the input register 15 to the data processing device main body 1.

  If the output clock of the frequency dividing circuit 12 is given to the memory card 2 without providing the delay circuit 13, the input register 15 operated by the output clock of the frequency dividing circuit 12 takes in the data read from the memory card 2. It becomes impossible to do.

  This is because there is a “delay” in the memory card 2 itself, the clock wiring, and the data wiring, and the data reception timing of the input register 15 and the memory card 2 transmitted to the input terminal of the input register 15. This is because there is a deviation from the timing of the data.

  However, in the data communication device 3 of the present embodiment, a predetermined amount of delay is given to the reference clock (divided clock) by the delay circuit 13, and this delayed reference clock is output to the memory card 2, so that the reference clock before the delay is used. The input register 15 that operates in this manner can capture data read from the memory card 2 in synchronization with the delay reference clock at the timing of the reference clock.

  The delay amount of the delay circuit 13, that is, the number m of stages of the shift registers 13a,... Is the delay amount of the memory card 2 itself, the delay amount of the clock wiring to the memory card 2, and the delay amount of the data wiring from the memory card 2. Determined by

  According to the configuration of the present embodiment, since the drive clock of the input register 15 can be fixed to the reference clock output from the frequency divider circuit 12, the data input timing is fixed, and the data processing performed by the data processing apparatus body 1 is easy. It becomes.

  Reference numeral 30 shown in FIG. 1 is a monitor terminal for a reference clock output from the frequency divider circuit 12. The designer of the electronic device may need to know the timing of the reference clock before the delay when incorporating the data communication device 3 of the present embodiment in the form of an IC chip into the electronic device. For this case, a monitor terminal 30 is provided.

(Second Embodiment)
FIG. 2 is a main part configuration diagram of an electronic device according to a second embodiment of the present invention. The configuration of the electronic device of the present embodiment is basically the same as that of the first embodiment, except that the delay amount in the data communication device can be variably set. Since the other points are the same as those of the first embodiment, the same components are denoted by the same reference numerals and the description thereof is omitted.

  The data communication apparatus 3 of this embodiment includes a selector 16 and a CPU 17 in addition to the original clock supply source 11, the frequency divider circuit 12, the delay circuit 13, the output driver 14, and the input register 15. The function of the CPU 17 can be replaced by the CPU of the data processing apparatus main body 1.

  The delay circuit 13 of this embodiment includes m stages of shift registers 13a, 13b,..., 13m that are cascade-connected as in the first embodiment. Further, the outputs of the shift registers 13a, 13b,..., 13m are taken out in parallel and inputted to the selector 16. The selector 16 selects any one shift register output according to the setting instruction of the CPU 17 and outputs the selected output to the output driver 14.

  For example, the CPU 17 determines the type of the memory card 2 attached to the memory card insertion slot, and determines the type of the memory card 2 to the selector 16 based on the delay amount corresponding to the type of the memory card 2 and the delay amounts of the data wiring and the clock wiring. A selector signal is output.

  Thus, the selector 16 selects the output of the third-stage shift register and outputs it to the output driver 14 according to the type of the memory card 2, or selects the output of the fourth-stage shift register and outputs the output driver. 14 can be output.

(Third embodiment)
FIG. 3 is a main part configuration diagram of an electronic device according to the third embodiment of the present invention. In addition to the configuration of the first embodiment shown in FIG. 1, the electronic device of this embodiment has a configuration in which the data processing body 1 writes data to the memory card 2.

  That is, an output register 18 that receives data from the data processing device main body 1 and outputs the data to the memory card 2 and a delay circuit 19 that delays the reference clock output from the frequency dividing circuit 12 to drive the output register 18 are provided. .

  The configuration of the delay circuit 19 is the same as that of the delay circuit 13 shown in FIG. 1, and is configured by cascading a predetermined number of shift registers, and each shift register is driven by an original clock.

  In the present embodiment, the delay circuit 19 and the delay circuit 13 are separately provided and the delay amount control is performed separately, so that data transmission at various timings requested by the memory card 2 side is possible. However, if the data transmission delay amount and the clock delay amount are the same, the delay circuit 19 may not be provided, and the output of the delay circuit 13 may be branched and input to the output register 18.

(Fourth embodiment)
FIG. 4 is a main part configuration diagram of an electronic device according to the fourth embodiment of the present invention. In addition to the configuration of the second embodiment shown in FIG. 2, the electronic device of this embodiment has a configuration in which the data processing body 1 writes data to the memory card 2.

  That is, an output register 18 that receives data from the data processing device main body 1 and outputs the data to the memory card 2, a delay circuit 19 that delays the reference clock output from the frequency divider circuit 12 to drive the output register 18, and a delay A selector 20 is provided which takes in each shift register output of the circuit 13 in parallel and selects one of them in accordance with a setting instruction from the CPU 17 and outputs it to the output register 18.

  In the present embodiment, a set of the delay circuit 13 and the selector 16 and a set of the delay circuit 19 and the selector 20 are provided separately, and the CPU 17 controls the respective delay amounts, and at various timings required by the memory card 2 side. Data transmission is possible.

  However, if the data transmission delay amount and the clock delay amount are the same, the delay circuit 19 and the selector 20 may be omitted, and the output of the selector 16 may be branched and input to the output register 18.

  Further, without providing the delay circuit 19, each shift register output of the delay circuit 13 may be branched and input to the selector 20, and the selection of the selector 16 and the selector 20 may be controlled separately by the CPU 17. is there.

(Fifth embodiment)
FIG. 5 is a main part configuration diagram of an electronic device according to a fifth embodiment of the present invention. In each embodiment described above, the clock signal output to the memory card 2 is configured to be delayed by the delay circuit.

  On the other hand, in the present embodiment, the delay reference clock selected by the selector 16 is used as the drive clock for the input register 15, and the clock output to the memory card 2 is used as the output clock for the frequency divider circuit 12. Even in this configuration, the input register 15 can capture the data read from the memory card 2 in synchronization with the output clock to the memory card 2 in accordance with the delay amount of the data.

  As described above, according to each embodiment of the present invention, the shift amount is controlled by the number of stages of the shift register using the shift register. Therefore, even if the characteristics of the individual circuit elements constituting the shift register vary, the shift is performed. The register operation is not affected by the variation, and the delay amount can be controlled with high accuracy. In addition, even when a data communication device is constituted by a semiconductor integrated circuit, it can be manufactured while allowing variation in characteristics of circuit elements, and the manufacturing cost is reduced.

  In the above-described embodiment, the original clock, which is a high-frequency clock, is generated by the PLL circuit provided in the data communication apparatus. However, the original clock may be input from an external clock circuit.

  Although the case where the external device is a memory card has been described, each of the above-described embodiments can be used for all data interfaces synchronized with a clock. For example, the present invention can be applied to data half-duplex communication where the influence of wiring delay is large. Further, it is applicable not only to serial transmission but also to parallel transmission with a plurality of data bits.

  The data communication device according to the present invention is useful when applied to various electronic devices because inexpensive and highly accurate data communication is possible. For example, the present invention is useful when applied to electronic devices such as digital cameras and mobile phones that use various memory cards as external storage devices.

It is a principal part block diagram of the electronic apparatus which concerns on the 1st Embodiment of this invention. It is a principal part block diagram of the electronic device which concerns on the 2nd Embodiment of this invention. It is a principal part block diagram of the electronic device which concerns on the 3rd Embodiment of this invention. It is a principal part block diagram of the electronic device which concerns on the 4th Embodiment of this invention. It is a principal part block diagram of the electronic device which concerns on the 5th Embodiment of this invention.

Explanation of symbols

1 Data processor 2 Memory card (external device)
3 Data communication device 11 Original clock supply source 12 Frequency divider (reference clock generator)
13, 19 Delay circuit 13a,... Shift register 14 output driver 15 input register 16, 20 selector 17 CPU
30 Reference clock monitor terminal

Claims (11)

  Reference clock generating means for generating and outputting a reference clock by dividing a high-frequency original clock in a data communication device that performs data transmission / reception synchronized with a clock with an external device, and a cascade-connected multi-stage shift register A clock delay means configured to take in the reference clock and generate and output a delayed reference clock delayed by a predetermined delay amount; and the reference clock or the delay output from one of the reference clock generation means and the clock delay means Clock output means for outputting a reference clock to the external device, and data read from the external device operated by the reference clock or the delayed reference clock output from the other of the reference clock generation means and the clock delay means Data input means for receiving And the data communication device.   2. The data communication apparatus according to claim 1, further comprising selector means for receiving in parallel the outputs of the shift registers constituting the clock delay means and selecting one of them to output as the delay reference clock.   The data communication apparatus according to claim 1, wherein the shift register is driven by the original clock.   4. The data communication apparatus according to claim 1, further comprising data output means for delaying data to be transmitted to the external device and transmitting the data to the external device.   5. The data communication apparatus according to claim 4, wherein output data is delayed by driving the data output means with an output clock of the clock delay means.   5. The output data is delayed by delaying the reference clock by a delay means different from the clock delay means, and driving the data output means by an output clock of the delay means. Data communication equipment.   7. The data communication apparatus according to claim 1, wherein the clock output unit is configured to output the delay reference clock to the external device.   The data communication apparatus according to claim 7, further comprising a monitor terminal for the reference clock.   7. The data communication apparatus according to claim 1, wherein the clock output unit is configured to output the reference clock to the external device.   An electronic device comprising the data communication device according to claim 1 in an input / output interface unit.   The electronic device according to claim 10, wherein the external device is a memory card.

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