JP2007264468A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To contribute to improvement of display quality of an image display device by not only clarifying a cause of phase deviation between a first clock signal CKH1 and a second clock signal CKH2 but also providing a means for eliminating the phase deviation. <P>SOLUTION: A line cross capacity caused by that a first clock signal line overlaps and crosses a power line in a first area and a line cross capacity caused by that a second clock signal line overlaps a power line are substantially equalized to eliminate the phase deviation between the clock signals CKH1 and CKH2, whereby the occurrence of vertical stripes is prevented. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a drive circuit in a video display device.

  In recent years, video display devices have strong market needs as monitors for flat-screen TVs, mobile phones and the like, such as liquid crystal display devices (LCDs) and organic EL (Electro Luminescence) display devices (or Organic Light Emitting Diodes; OLEDs). Research and development is actively conducted. The driving methods of these display devices are basically the same, and can be roughly classified into a passive matrix type and an active matrix type. Among these, an active matrix video display device performs switching by providing a switching element in each pixel and applying a voltage corresponding to a video signal to each pixel or passing a current.

  Here, the configuration of a conventional active matrix organic EL display device will be described with reference to FIG.

  An active matrix organic EL display device as shown in FIG. 11 includes a plurality of gate signal lines 51 connected to a vertical driver 50 for supplying a gate signal onto a substrate 10 and a horizontal driver 60 for supplying a drain signal. The sampling transistors SPT1, SPT2,..., SPTn are sequentially turned on according to the timing of the output sampling pulse, and a plurality of drain signal lines 61 to which the data signal (video signal) Sig of the data signal line 62 is supplied accordingly. In addition, current is supplied to the organic EL element 73 by the power supply lines 80, 82, 101, and 107 for supplying power supply voltages VVSS, VVDD, HVSS, and HVDD necessary for driving the vertical driver 50 and the horizontal driver 60, and the power supply voltage PVDD. A power line 74 is arranged. An organic EL element 73, a selection transistor 70, a drive transistor 71, and a storage capacitor 72 are arranged in each pixel corresponding to each intersection of the gate signal line 51 and the drain signal line 61.

  A panel driving LSI is provided on the external circuit board 20, which is a separate board from the board 10. The first and second clock signals CKH1 and CKH2 are supplied from the circuit board 20 provided outside. These clock signals CKH1 and CKH2 are clock signals having opposite phases, and are reference signals for generating a timing signal HSW, which will be described later, which determines the timing at which the sampling transistors SPt1, SPt2,..., SPtn latch the video signal. . Further, the panel driver LSI supplies a start signal STV for the vertical driver, a start signal STH for the horizontal driver, and a video signal Sig.

  Next, the operation principle of the organic EL display device will be described with reference to FIG. First, in FIG. 11, clock signals CKH1 and CKH2 input from the external circuit board 20 are respectively input to the level shifter (L / S) 100 and boosted. Thereafter, the clock signals CKH 1 and CKH 2 are input to the buffer circuit unit 102 including a plurality of stages of buffer circuits 103, and input to the shift registers 25 constituting the horizontal driver 60.

  Each shift register 25 sequentially outputs a timing signal HSW based on a horizontal start signal STH. Based on the timing signal HSW, the sampling transistor SPT selected at that timing is turned on, the corresponding drain signal line 61 and the data signal line 62 are connected, and the video signal Sig input from the outside is the drain signal line 61. To be supplied.

  A gate signal is input from a predetermined gate signal line 51 to the gate electrode of the selection transistor 70, and the selection transistor 70 in the row is turned on. Thereby, the video signal Sig is supplied to the gate electrode of the driving transistor 71 via the selection transistor 70. At the same time, the holding capacitor 72 is charged or discharged to a voltage corresponding to the video signal Sig, and the video signal (data potential) Sig is held. Thus, the data potential is stably held by the holding capacitor even after the selection transistor 70 is turned off. The held data potential matches the gate potential of the drive transistor 71, and a current corresponding to the data potential is supplied to the organic EL element 73 through the drive transistor 71 by the power supply voltage PVDD. The organic EL element 73 emits light with a luminance corresponding to the amount of current supplied, and a display as a display device can be obtained.

  Here, a theoretical mechanism in which the timing signals HSW are sequentially generated from the shift registers 25 based on the start signal STH and the video signal Sig is supplied to the drain signal line 61 in accordance with the timing signals HSW is shown in FIG. This will be specifically described with reference to a timing chart.

  A case where the horizontal start signal STH input to the first-stage shift register 25 has a pulse width corresponding to two pulses of the clock signal will be described. When the horizontal start signal STH input to the first stage shift register 25 is H (High) and the first clock signal CKH1 is H, the timing signal HSW1 output from the first stage shift register 25 is H. Simultaneously with the output of the timing signal HSW1, the inverted signal XHSW1 is also output, the sampling transistor SPT1 which is a CMOS is turned on, the data signal line 62 and the drain signal line 61 are connected, and the video signal Sig is supplied to the drain signal line 61. Is done. Here, only the case where HSW1 is H is illustrated, but actually, a signal (XHSW) obtained by inverting the timing signal HSW1 is also output at the same time. In the following description, only the timing signal HSW is shown, and the inverted signal XHSW is omitted.

Thereafter, when the horizontal start signal STH becomes L (Low) and the second clock signal CKH2 becomes L, the timing signal HSW1 output from the first-stage shift register 25 becomes L. As a result, the sampling transistor SPT1 is turned off, the data signal line 62 and the drain signal line 61 are disconnected, and the potential of the drain signal line 61 is determined. The first-stage shift register 25 outputs the shift pulse signal SHP ₁ having the same waveform as the timing signal HSW ₁ to the second-stage shift register 25 simultaneously with the output of the timing signal HSW ₁ .

  The shift pulse SHP1 output from the first-stage shift register 25 to the second-stage shift register 25 plays the same role as the start signal STH input to the first-stage shift register 25. When SHP1 becomes H and the second clock signal CKH2 becomes H, the timing signal HSW2 output from the second-stage shift register 25 becomes H. As a result, the sampling transistor SPT2 is turned on, and the video signal Sig is supplied to the drain signal line 61.

  Thereafter, when SHP1 becomes L and the first clock signal CKH1 becomes L, the timing signal HSW2 output from the second-stage shift register 25 becomes L. As a result, the sampling transistor SPT2 is turned off, the data signal line 62 and the drain signal line 61 are disconnected, and the potential of the drain signal line 61 is determined. The second-stage shift register 25 outputs a shift pulse SHP2 having the same waveform as the timing signal HSW2 to the third-stage shift register 25 simultaneously with the output of the timing signal HSW2.

  By repeating the above operation, timing signals HSW1, HSW2, HSW3,... Are sequentially generated, and a video signal is supplied to each pixel according to these signals.

  When the horizontal start signal STH input to the first-stage shift register 25 has a pulse width corresponding to two pulses of the clock signal, the timing signal HSW1 output from the first-stage shift register 25 is H During this period, the timing signals HSW2 to HSW4 sequentially rise, and the timing signal HSW5 rises simultaneously with the fall of the timing signal HSW1. That is, SPT2 to SPT4 are turned on while the sampling transistor SPT1 is turned on, and SPT5 is turned on at the same time as SPT1 is turned off.

  However, in the conventional organic EL display device, theoretically, the first clock signal CKH1 and the second clock signal CKH2 that should be input to each shift register 25 in the same phase as shown in FIG. The shift register 25 may be input in a shifted state. FIG. 10 shows a case where the phase of the second clock signal CKH2 is delayed by Δt compared to the first clock signal CKH1.

  Due to the phase delay of the second clock signal CKH2, the pulse width of the odd-numbered timing signals HSW1, HSW3, HSW5,... Whose timing signal HSW falls at the fall (L) of the second clock signal CKH2 is Δt. Will spread. As a result, for example, the periods in which the timing signals HSW1 and HSW5 are High may overlap. That is, there is a situation in which the timing signal HSW5 output from the fifth stage shift register 25 rises immediately before the timing signal HSW1 output from the first stage shift register 25 falls. Due to the rise of the fifth stage timing signal HSW5, the video signal may temporarily have noise. When the first stage timing signal HSW1 falls in a state where noise is added to the video signal, the potential of the drain signal line 61 in the first column is determined by the video signal in the state of noise, and is desired. Video signal may not be obtained. In the case shown in FIG. 10, since this phenomenon occurs in the odd number columns of each row, there has been a problem that the display has a vertical stripe every other pixel. Here, one pixel is made up of RGBW, and one pixel RGBW shares one drain signal line 61.

  Therefore, in the present invention, the cause of the phase shift between the first clock signal CKH1 and the second clock signal CKH2 is elucidated, and a solution is provided to contribute to the improvement of display quality. With the goal.

  The phase shift that occurs between the first clock signal CKH1 and the second clock signal CKH2 is caused by the two clocks that transmit the first clock signal CKH1 and the second clock signal CKH2 due to the circuit arrangement in FIG. Of the clock signal lines 105 and 106, only the second clock signal line 106 is connected to the first power supply line 101 that supplies the power supply voltage HVSS to the horizontal driver circuit 60 between the level shifter circuit 100 and the buffer circuit unit 102, and A It has been found that the crossing occurs at a point, a difference in line cross capacitance occurs between the first and second clock signal lines 105 and 106, and the phase of only the second clock signal is delayed. That is, since a phase delay occurs only in the second clock signal, a phase shift has occurred with the first clock signal that should be at the same timing.

  FIG. 11 shows an example in which the first power supply line 101 and the second clock signal line 106 intersect at the point A, but it is necessary to supply the power supply voltages HVSS and HVDD to the buffer circuit 103 in each stage. This intersection cannot be eliminated by easy layout change.

  Therefore, an object of the present invention is to solve the phase shift caused by the above-described phase delay.

  The display device of the present invention includes a plurality of pixels arranged in a matrix, a driver circuit 60 that outputs a display signal for displaying an image on the pixels, and a first power supply voltage that is supplied to the driver circuit 60. Power supply line 101, first clock signal line 105 for transmitting a first clock signal for controlling the output timing of the display signal to driver circuit 101, and second that the first clock signal is inverted to driver circuit 60. In the display device including the second clock signal line 106 that transmits the first clock signal line 106, the second clock signal line 106 overlaps the first power supply line 101 in a first area, The clock signal line 105 includes a signal delay adjustment unit 104 that overlaps with the first power supply line 101 but does not intersect.

  With this configuration, the signal delay adjusting unit 104 has the same first phase delay as that of the second clock signal generated at the portion where the second clock signal line 106 intersects the first power supply line 101 at the point A. The clock signal can be delayed. As a result, there is no phase shift between the clock signals CKH1 and CKH2, and the timing signal HSW5 does not rise immediately before the timing signal HSW1 falls, that is, it can be determined by a noisy video signal. In addition, a desired video signal can be supplied to the drain signal line 61. Thereby, the occurrence of vertical stripes is prevented, and a high-quality display device can be obtained. That is, in the present application, instead of eliminating the phase delay of the clock signal generated in the second clock signal line 106, both of them are intentionally generated in the first clock signal line 105 by intentionally generating the phase delay. The timings of the clock signals of the clock signal lines are aligned.

  In addition, the first and second clock signal lines 105 and 106 are formed in the same layer, and the area of the signal delay adjustment unit 104 where the first clock signal line 105 overlaps the first power supply line 101 is the second level. The clock signal line 106 is configured to have the same area as that of the portion intersecting with the first power supply line 101. When the first and second clock signal lines 105 and 106 are formed in the same layer, in order to make the line cross capacitance generated between the respective signal lines and the first power supply line 101 substantially equal, Only the area where each signal line overlaps with the first power supply line 101 may be made substantially equal. In other words, when the first and second clock signal lines 105 and 106 are formed in different layers, an interlayer insulating film between the clock signal lines 105 and 106 and the first power supply line 101 is used. In consideration of the thickness and the dielectric constant of the interlayer insulating film, the area of the signal delay adjustment unit 104 where the first clock signal line 105 overlaps the first power supply line 101 may be determined.

  The first clock signal line 105 extends in parallel with the first power supply line 101, and a part of the first clock signal line 105 is connected to the first clock signal line 105 of the first power supply line 101. The signal delay adjusting unit 104 is formed by overlapping with the first power supply line 101 by entering from the first side on the extending side and exiting from the first side. As a result, the phases of the first and second clock signals CKH1 and CKH2 are delayed due to the same power supply line 101, so that the delay values can be easily matched.

  In the region surrounded by the first side of the first power supply line 101 and the side of the first clock signal line 105, the maximum width of the region in the first side direction is the first side. The configuration may be wider than the maximum width of the vertical region. Thus, the redundant length of the first clock signal line 105 can be shortened.

In another embodiment of the present invention, the signal delay adjustment unit 104 has a power supply line protruding part from which a part of the first power supply line 101 protrudes, and the first clock signal line 105 overlaps with the power supply line protruding part. Therefore, the signal delay adjustment unit 104 without changing the wiring length of the first clock signal line 105.
The pattern change when the present invention is carried out can be minimized.

  Further, with the above configuration, even when a mask shift occurs in the process of forming the first power supply line 101 or the first and second clock signal lines 105 and 106, the clock signal lines 105 and 106 and the power supply lines are connected to each other. It is possible to keep a constant area where and intersect. That is, since the respective line cross capacitances can be kept equal, vertical stripes do not occur even when mask displacement occurs, and a high-quality display device can be provided.

  The display device according to the present invention further includes a level shifter circuit 100 that converts the voltage levels of the first and second clock signals CKH1 and CKH2, and a buffer circuit unit 102 that includes a plurality of buffer circuits 103 having different current driving capabilities. The signal delay adjustment unit 104 is provided between the level shifter circuit 100 and the buffer circuit unit 102.

  Further, the signal delay adjustment unit 104 may be provided between the buffer circuit 103 at a predetermined stage and the buffer circuit 103 at the next stage. As a result, the signal delay adjusting unit 104 is formed after at least one stage of the buffer circuit 103, so that the clock signal is less likely to be distorted and signal attenuation can be prevented. Further, since it is not always necessary to form after all the buffer circuits 103, the layout can be prioritized.

  In addition, the width of the first and second clock signal lines 105 and 106 is narrower than the width of the first power supply line 101.

  In another embodiment of the present invention, a plurality of pixels arranged in a matrix, a driver circuit 60 that outputs a display signal for displaying an image on the pixels, and a first and second driver circuit 60 are provided. First and second power supply lines 101 and 107 for supplying power supply voltage, a first clock signal line 105 for transmitting a first clock signal for controlling output timing of a display signal to the driver circuit 60, and a driver circuit 60 In the display device, the second clock signal line 106 transmits a second clock signal in which the first clock signal is inverted, and the second clock signal line 106 is connected to the first power supply line and the first clock signal line 106. The first clock signal line has a signal delay adjustment unit that overlaps with the second power supply line with an area equal to the first area without intersecting with the second power supply line.

  With this configuration, no phase shift occurs between the clock signals CKH1 and CKH2, and when the timing signal HSW1 falls, a desired video signal is supplied to the data line without picking up a noisy video signal. And a high-quality display device can be obtained. In particular, the degree of freedom in layout is greatly improved by overlapping with the second power supply line 107.

  The first and second clock signal lines 105 and 106 are formed in the same layer, the first and second power supply lines 101 and 107 are formed in the same layer, and the first clock signal line 105 is the first layer. The area of the signal delay adjustment unit 104 that overlaps the second power supply line 107 is set to be equal to the area of the portion where the second clock signal line 106 intersects the first power supply line 101. By forming the first and second power supply lines 101 and 107 in the same layer and the first and second clock signal lines in the same layer, the first clock signal line 105 overlaps with the second power supply line 107. In order to make the line cross capacitance generated by this and the line cross capacitance generated when the second clock signal line 106 intersects the first power supply line 101 substantially equal, It is sufficient that the area where the second clock signal line 106 intersects with the first power supply line 101 is substantially equal.

In addition, the signal delay adjustment unit 104 extends in parallel with the second power supply line 107, and a part of the first clock signal line 105 extends from the first clock signal line 105 of the second power supply line 107. A signal delay adjustment unit is formed by overlapping with the second power supply line 107 by entering from the second side on the existing side and exiting from the second side. Accordingly, the first clock signal line 105 and the second clock signal line 106 can be overlapped or intersected with different power supply lines, so that the degree of freedom in layout is further improved.

  In the region surrounded by the second side of the second power supply line 107 and the side of the first clock signal line 105, the maximum width of the region in the second side direction is the second side. It may be wider than the maximum width of the vertical region. Thus, the redundant length of the first clock signal line 105 can be shortened.

  In addition, the signal delay adjustment unit 104 has a power supply line protruding part from which a part of the second power supply line 107 protrudes, and the first clock signal line 105 overlaps the power supply line protruding part. With this configuration, it is possible to provide the signal delay adjustment unit 104 that can cope with mask displacement.

  Further, the level shifter circuit 100 for converting the voltage levels of the first and second clock signals and a buffer circuit unit 102 including a plurality of buffer circuits 103 having different current driving capabilities are further provided. Provided between the circuit 100 and the buffer circuit portion 102.

  Further, the signal delay adjustment unit 104 may be provided between the buffer circuit 103 at a predetermined stage and the buffer circuit 103 at the next stage. Thus, by providing the signal delay adjusting unit 104 after the buffer circuit 103, the rounding of the clock signal can be suppressed and the attenuation of the clock signal can be prevented.

  In addition, the width of the first and second clock signal lines 105 and 106 is narrower than the width of the first power supply line 101.

  According to the present invention, the clock signal CKH1 supplied to each shift register 25 is provided by providing the signal delay adjusting unit 104 in the first clock signal line 105 in accordance with the phase delay generated in the second clock signal line 106. And CKH2 can be prevented from shifting in phase. Accordingly, a high-quality display device without display unevenness such as vertical stripes can be provided.

  Further, by providing the signal delay adjusting unit 104 between the buffer circuit 103 at the predetermined stage and the buffer circuit 103 at the next stage, the signal of both the first and second clock signals can be obtained without the clock signal becoming distorted. Delay can be prevented.

  In addition, by providing a configuration in which the first clock signal line 105 in the signal delay adjustment unit 104 overlaps the protruding portion of the first power supply line 101, a high-quality display device without display unevenness such as vertical stripes is provided. It is possible to cope with mask displacement. Further, the redundant length of the first clock signal line can be shortened by the above configuration.

  Further, the first clock signal line 105 is overlapped with the second power supply line 107 in accordance with a phase delay caused by the second clock signal line 106 intersecting the first power supply line 101, whereby the clock signal CKH1 is overlapped. And CKH2 can be prevented from shifting in phase. Accordingly, a high-quality display device without display unevenness such as vertical stripes can be provided.

  Further, since the first and second clock signal lines 105 and 106 can be overlapped or intersected with different power supply lines, the degree of freedom in layout is improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic view showing an example of an active matrix organic EL display device. Note that the present invention is not limited to an organic EL display device, and can be used for a liquid crystal display device and an active matrix display device using other display elements.

  In FIG. 1, the configuration other than the potential conversion circuit unit 110 having the signal delay adjustment unit 104 is the same as that in FIG. That is, a plurality of drain signal lines 61 extending in the column direction and gate signal lines 51 extending in the row direction are arranged in the display region in the panel region 10. Near the intersection of the drain signal line 61 and the gate signal line 51, a switching selection transistor 70, a storage capacitor 72 connected thereto, a drive transistor 71 whose gate electrode is connected to the drain electrode of the selection transistor 70, and The organic EL element 73 connected to the drain electrode of the driving transistor is disposed to form a display pixel. That is, a plurality of pixels are arranged in a matrix by a plurality of gate signal lines 51 extending in the row direction and a plurality of drain signal lines 61 extending in the row direction.

  Around the display area, a horizontal driver 60 to which a plurality of drain signal lines 61 are commonly connected and a vertical driver 50 to which a plurality of gate signal lines 51 are commonly connected are arranged. A display signal for supplying a video signal to the pixels is output from the horizontal driver 60, and a display signal for turning on the selection transistor 70 is output from the vertical driver 50.

  The horizontal driver 60 includes a level shifter circuit 100, a plurality of buffer circuits 103, a signal delay adjustment unit 104, first and second clock signal lines 105 and 106, and first and second power supply lines 101 and 107. Clock signals CKH 1 and CKH 2 and power supply voltages HVSS and HVDD are supplied from the circuit unit 110. Here, the clock signals CKH1 and CKH2 are clock signals having inverted signal waveforms. That is, the two clock signals are in-phase signals, but the rising or falling edges of the signals are opposite. Although not shown, a potential conversion circuit unit having a similar configuration is also provided around the vertical driver 50.

  An external circuit board 20 on which a panel driving LSI is mounted is provided outside the panel region 10. The panel driving LSI includes power supply voltages HVSS, HVDD, VVSS, VVDD for operating the horizontal and vertical drivers 60 and 50 and the buffer circuit 103, and clock signals CKH1, CKH2, and CKV1, for operating the horizontal and vertical drivers. CKV2, timing signals STH and STV, and a video signal Sig are generated.

  Further, the horizontal driver 60 is provided with a plurality of shift registers 25 and a plurality of sampling transistors SPT1, SPT2, SPT3,... Power supply lines 101 and 107 and clock signal lines 105 and 106 for supplying clock signals CKH1 and CKH2 are connected. Here, for example, the power supply voltage HVSS of the first power supply line 101 is set to the ground level, and the power supply voltage HVDD of the second power supply line 107 is set to 10.5V. Each shift register 25 sequentially transfers a horizontal start signal STH and a shift pulse signal SHP to the next-stage shift register 25 based on the clock signals CKH1 and CKH2, and outputs a timing signal HSW. The output timing of the display signal output from the horizontal driver to the pixel is controlled by the timing signal HSW output in synchronization with the first clock signal CKH1 and the second clock signal CKH2. That is, the output timing of the display signal is controlled by the first clock signal CKH1 and the second clock signal CKH2.

  What is characteristic in FIG. 1 is that the first clock signal line 105 in the potential conversion circuit unit 110 includes a signal delay adjustment unit 104. Thereby, the phase shift between CKH1 and CKH2 can be prevented.

  Hereinafter, embodiments of the signal delay adjustment unit 104 that are characteristic of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment will be described with reference to FIG. FIG. 2 is an enlarged view of a main part of the potential conversion circuit unit 110 in FIG. 2 includes a signal delay adjusting unit 104, a level shifter (L / S) 100 to which the first and second clock signal lines 105 and 106 are connected, a plurality of buffer circuits 103, a horizontal driver 60, and the like. The first and second power supply lines 105 and 106 for supplying a power supply voltage to the plurality of buffer circuits 103 are configured. A part of the first power supply line 101 extends in the extending direction of the first and second clock signal lines 105 and 106. Here, the first power supply line 101 functions as a power supply for the plurality of buffer circuits 103 and the horizontal driver 60 (HVSS), and is connected to the ground level, for example.

  A second clock signal line 106 having a line width W1 extending from the level shifter circuit 100 overlaps the first power supply line 101 having a line width W2 with a first area overlapping between the level shifter 100 and the buffer circuit 103. That is, the second clock signal line 106 enters from the first side of the first power supply line 101, that is, the side on which the first clock signal line 106 extends, and the first power supply line 101. The first power supply line 101 is crossed by coming out from the other side. Crossing in this application means entering from the first side and exiting from the opposite side. At that time, an area where the second clock signal line 106 and the first power supply line 101 overlap is defined as a first area. Further, the first clock signal line 105 having a line width W1 extending from the level shifter circuit 100 is bent between the level shifter circuit 100 and the buffer circuit unit 102 without intersecting the first power supply line 101, and has a first area. And overlaps the first power supply line 101 in an area substantially equal to In other words, the first clock signal line 105 enters from the first side of the first power supply line 101, bends in the direction in which the first power supply line 101 extends on the first power supply line 101, and again enters the first power supply line 101. By exiting from the first side of one power line 101, the first power line 101 overlaps without intersecting. At that time, the first clock signal line 105 overlaps the first power supply line 105 so that the area overlapping the first power supply line 101 is substantially equal to the first area described above.

  According to the first embodiment, a line cross capacitance generated between the second clock signal line 106 and the first power supply line 101 and a line generated between the first clock signal line 105 and the first power supply line 101 are used. The cross capacitance is substantially equal. Thereby, a phase shift occurring between the clock signals CKH1 and CKH2 can be prevented. In other words, the phase shift between the clock signals CKH1 and CKH2 is prevented by delaying the phase of the first clock signal CKH1 in accordance with the phase delay of the second clock signal CKH2.

  A more preferable form in the first embodiment is the maximum width in the first side direction in the region surrounded by the first side of the first power supply line 101 and the side of the first clock signal line 105. L1 is wider than the maximum width L2 in the direction perpendicular to the first side. That is, it is preferable that L1 and L2 satisfy L1> L2.

Further, in order for the area where the first clock signal line 105 overlaps the first power supply line 101 to be substantially equal to the first area, the relation that the widths W2 and L2 of the power supply lines satisfy W2 / 2> L2. It is necessary to satisfy. Here, it is assumed that the line widths W1 of the first and second clock signal lines 105 and 106 are equal. The reason why the above relationship needs to be satisfied is that the length in the direction perpendicular to the first side of the region where the second clock signal line 106 overlaps the first power supply line 101 is approximately the length of the first power supply line 101. Since the width of the first clock signal line 105 is W2 and the first clock signal line 105 is folded back on the first power supply line 101, the first clock signal line 105 is connected to the first power supply line 101 when L2 becomes L2> W2 / 2. This is because the overlapping area becomes larger than the first area and is not equal.

  Here, the widths of the first and second clock signal lines 105 and 106 are described as being equal to W1, but in the present invention, the widths of the signal lines 105 and 106 may be different. The first area where the first clock signal line 106 overlaps the first power supply line 101 and the area where the first clock signal line 105 overlaps the first power supply line 101 may be substantially the same. For example, only the line width of the portion where the first clock signal line 105 overlaps the first power supply line 101 may be increased, and the overlapping length may be shortened.

  Further, when the first clock signal line 105 and the second clock signal line 106 are formed in different layers, the phase delay amount changes depending on the thickness of the interlayer insulating film and the dielectric constant even if the area is the same. Since it is difficult to align the phases, it is easy to form the first clock signal line 105 and the second clock signal line 106 in the same layer so that the areas are equal.

  2 shows an embodiment in which the first clock signal line 105 is bent in a rectangular shape, but the present invention is not limited to this form. For example, the configuration shown in FIG. Good. That is, the first clock signal line 105 may enter from the first side, bend at an acute angle on the first power supply line 101, and exit from the first side again. That is, the present invention does not depend on the shape of the first clock signal line 105, and the first clock signal line and the first area where the second clock signal line 106 intersects the first power supply line 101 and overlaps with each other. The area where 105 and the first power supply line 101 overlap may be substantially the same.

  The material such as the power supply line and the signal line is a conductive wiring such as Al, Mo, polysilicon or the like. The width of the power supply line is preferably 100 to 120 μm, and the width of the clock signal line is preferably about 10 μm, although it depends on the area occupied by the drive circuit that can be built in the display panel.

(Second Embodiment)
A second embodiment will be described with reference to FIG. The first power supply line 101 in the potential conversion circuit unit 110 of the second embodiment has a power supply line protruding portion in which the first power supply line 101 protrudes between the level shifter 100 and the buffer circuit 103. The second clock signal line 106 and the first power supply line 101 intersect with the first power supply line 101 so as to have an area substantially equal to the first area that overlaps and overlaps with the first power supply line 101. One clock signal line 105 overlaps with a power supply line protruding portion.

  Also according to the second embodiment, a line cross capacitance generated between the second clock signal line 106 and the first power supply line 101 and between the first clock signal line 105 and the first power supply line 101 are generated. The line cross capacitance becomes substantially equal, and the phase shift that occurs between the clock signals CKH1 and CKH2 can be prevented.

  Furthermore, according to the second embodiment, even when mask displacement occurs, the first clock signal line 105 and the first area where the second clock signal line 106 and the first power supply line 101 intersect and overlap each other are overlapped. And the overlapping area of the power line protrusions can be kept substantially the same.

Next, the advantages of the second embodiment will be described in comparison with FIG. 2 showing the first embodiment. In FIG. 2, for example, consider a case where a mask shift occurs in the process of forming the first power supply line 101, and the first power supply line 101 is formed shifted to the left or right. In this case, even if the first power supply line 101 is formed to be slightly shifted from left to right, the area where the second clock signal line 106 and the first power supply line 101 overlap does not change. However, when the first power supply line 101 is formed to be shifted to the right side, that is, the side where the second clock signal line 106 extends, the area where the first clock signal line 105 and the first power supply line 101 overlap. Becomes smaller. In addition, when the first power supply line 101 is formed to be shifted to the left side, that is, the side where the first clock signal line 105 extends, the area becomes large. That is, in the first embodiment, when a mask shift occurs, the first area where the second clock signal line 106 and the first power supply line 101 overlap does not change, but the first clock signal line 105 The area where the first power supply line 101 overlaps may change.

  On the other hand, in FIG. 4 showing the second embodiment, a mask shift occurs in the process of forming the first power supply line 101, and the first power supply line 101 is shifted to the left or right. Even so, the area where the second clock signal line 106 and the first power supply line 101 overlap does not change, and the area where the first clock signal line 105 and the first power supply line 101 overlap does not change. Even when a mask shift occurs in the direction in which the two clock signal lines extend, the area where each of the first and second clock signal lines 105 and 106 overlaps the first power supply line 101 is substantially equal. It does not change.

  Therefore, according to the second embodiment, the first clock signal line 105 and the first area where the second clock signal line 106 and the first power supply line 101 cross each other even when mask displacement occurs. The area where the first power supply line 101 overlaps can be kept the same, and no phase shift occurs. That is, it is possible to provide the signal delay adjustment unit 104 corresponding to mask displacement.

  Moreover, in 2nd Embodiment, it is preferable that length L3 in FIG. 4 is 1 micrometer or more. This is because the maximum value of the mask displacement is about 1 μm, so if the L3 is designed to be 1 μm or more, the second clock signal line 106 and the first power supply line 101 intersect and overlap each other. The area and the area where the first clock signal line 105 and the power supply line protrusion overlap can be reliably kept the same.

(Third and fourth embodiments)
The third and fourth embodiments will be described with reference to FIGS. In the third embodiment shown in FIG. 5, the intersection of the second clock signal line 106 and the first power supply line 101 and the signal delay adjustment unit 104 in the first embodiment are the first stage buffer circuit. 103 and the second-stage buffer circuit 103. Thereby, the signal delay of both the clock signals CKH1 and CKH2 can be prevented as compared with the first embodiment. In the first embodiment, the clock signals CKH 1 and CKH 2 immediately after being output from the level shifter circuit 100 may be distorted by the intersection with the first power supply line 101 and the signal delay adjustment unit 104. As a result, the clock signals CKH1 and CKH2 may be delayed. In other words, there is no phase shift between the clock signals, but the clock signals CKH1 and CKH2 may be delayed at the same time.

  In contrast, in the third embodiment, after the output of the buffer circuit, the intersection of the second clock signal line 106 and the first power supply line 101 and the signal delay adjustment unit 104 of the first clock signal line 105 are provided. Therefore, the clock signals CKH1 and CKH2 after buffering can be further prevented from being delayed by both the clock signals CKH1 and CKH2 without the signal being lost by the crossing portion and the signal delay adjusting unit 104.

Here, an example in which the signal delay adjustment unit is arranged between the first-stage buffer circuit 103 and the second-stage buffer circuit 103 is shown, but the present invention is not limited to this. That is, the intersection and the signal delay adjustment unit 104 may be disposed between the buffer circuits 103 subsequent to the second stage. However, since the circuit elements of the buffer circuit 103 become larger in the later stage, the signal delay adjustment unit 104 is disposed between the first stage and the second stage buffer circuit 103 from the viewpoint of flexibility in layout design. Is more preferable.

  In the fourth embodiment shown in FIG. 6, the intersection of the second clock signal line 106 and the first power supply line 101 and the signal delay adjustment unit 104 in the second embodiment are the first stage buffer circuit 103. And the second-stage buffer circuit 103. As a result, signal delay of both the clock signals CKH1 and CKH2 due to signal rounding can be prevented as in the third embodiment.

Further, the present invention is not limited to the crossing and signal delay adjustment unit 104 being provided between the first-stage buffer circuit 103 and the second-stage buffer circuit 103, and the second and subsequent stages. May be provided between the buffer circuits 103.
(Fifth embodiment)
A fifth embodiment will be described with reference to FIG. The potential conversion circuit unit 110 in the fifth embodiment includes a level shifter circuit 100 and a plurality of buffer circuits 103 connected to the first and second clock signal lines 105 and 106, and two clock signal lines 105. , 106 extend in the direction in which the first power supply line 101 and the second power supply line 107 extend. Here, the first power supply line 101 is set to a ground level (HVSS), for example, and the second power supply line 107 is set to a high potential (HVDD) of 10.5V. In the first to fourth embodiments, the second clock signal line 106 intersects with the first power supply line 101, and the first clock signal line 105 overlaps without intersecting with the first power supply line 101. Alternatively, the signal delay adjustment unit 104 is formed so as to overlap the protruding portion of the first power supply line 101. On the other hand, in the fifth embodiment, the second clock signal line 106 intersects with the first power supply line 101, and the first clock signal line 105 intersects with the first and second power supply lines 105, 107. The second power supply line 107 is not overlapped.

  That is, the second clock signal line 106 enters from the first side of the first power supply line 101, exits from the other side, intersects the first power supply line 101, and is connected to the first clock signal line 101. Reference numeral 105 denotes a second side of the second power supply line 107 on the side where the first clock signal line 105 extends from the second power supply line 107 without crossing the first and second power supply lines 101 and 107. It enters from the side, exits from the second side again, and overlaps with the second power supply line 107.

  The same effects as those of the first to fourth embodiments can be obtained by the signal delay adjustment unit 104 according to the fifth embodiment. In other words, the signal delay adjustment unit 104 of the first clock signal line 105 performs the first delay according to the phase delay of the second clock signal generated by the second clock signal line 106 intersecting the first power supply line 101. The first clock signal and the second clock signal can be prevented from shifting in phase. As a result, display unevenness such as vertical stripes can be prevented.

  The first and second clock signal lines 105 and 106 are preferably formed in the same layer, and the first and second power supply lines 101 and 107 are preferably formed in the same layer. This is because the signal delay adjusting unit is configured so that the phase delay generated when the second clock signal line 106 intersects the first power supply line 101 is substantially equal to the phase delay generated by the signal delay adjusting unit 104. This is because the area 104 and the area where the second clock signal line 106 intersects the first power supply line 101 may be made equal.

In FIG. 7, the first clock signal line 105 is bent into a rectangular shape to form the signal delay adjusting unit 104. However, the present invention is not limited to this, and the first clock signal line 105 as shown in FIG. The line 105 may enter from the second side of the second power supply line 107 and the folded signal delay adjustment unit 104 may be formed at an acute angle on the second power supply line 107.

  7 shows an example in which the signal delay adjusting unit 104 is provided between the first-stage buffer circuit 103 and the second-stage buffer circuit 103. However, the present invention is not limited thereto. It is not limited. That is, it may be provided between the level shifter circuit 100 and the buffer circuit unit 102 or between the buffer circuits 103 in the second and subsequent stages.

(Sixth embodiment)
A sixth embodiment will be described with reference to FIG. In the sixth embodiment, as in the fifth embodiment, the potential conversion circuit unit 110 includes the level shifter circuit 100 connected to the first and second clock signal lines 105 and 106 and a plurality of buffer circuits 103. However, the first power supply line 101 and the second power supply line 107 extend in the direction in which the first and second clock signal lines 105 and 106 extend. The difference from the fifth embodiment is that the second power supply line 107 has a power supply line protrusion. Then, the first clock signal line 105 overlaps with the power supply line protruding portion, thereby forming the signal delay adjusting unit 104.

  When the first clock signal line 105 overlaps the protruding portion of the power supply line of the second power supply line 107, the second clock signal generated by the second clock signal line 106 intersecting the first power supply line 101 is generated. According to the phase delay, the first clock signal can be delayed to prevent a phase shift between the first and second clock signals. As a result, display unevenness such as vertical stripes can be prevented.

  Further, the first clock signal line 105 overlaps with the power supply line protruding portion of the second power supply line 107, so that even when a mask shift occurs, the first clock signal line 105 is between the first clock signal CKH1 and the second clock signal CKH2. No phase shift occurs.

  8 shows an example in which the signal delay adjusting unit 104 is provided between the first-stage buffer circuit 103 and the second-stage buffer circuit 103. However, the present invention is not limited thereto. It is not limited. That is, it may be provided between the level shifter circuit 100 and the buffer circuit unit 102 or between the buffer circuits 103 in the second and subsequent stages.

  In the first to sixth embodiments, HVSS is exemplified as the first power supply line 101, but it may be HVDD or other than that. If the first and second power supply lines 101 and 107 are HVSS and HVDD, they are normally arranged close to each other, so that layout design is easy, and HVSS and HVDD are usually formed in the same layer. Easy to align.

In addition, the second clock signal line 107 intersects with the first power supply line 101 and the first clock signal line 105 includes the signal delay adjustment unit 104. However, the first clock signal line 105 and the second clock signal line 105 The clock signal line 106 may be switched.
(How to create timing signals)
As described above, according to the first to fifth embodiments of the present invention, since the first clock signal line 105 includes the signal delay adjustment unit 104 in the potential conversion circuit 110, the theory shown in FIG. A typical timing signal HSW can be obtained.

In FIG. 8, the case where the horizontal start signal STH input to the first-stage shift register 25 has a pulse width corresponding to two pulses of the clock signal will be specifically described. When the horizontal start signal STH input to the first-stage shift register 25 is H (High) and CKH1 is H, the timing signal HSW1 output from the first-stage shift register 25 is H. Simultaneously with the output of the timing signal HSW1, the inverted signal XHSW1 is also output. With these signals, the sampling transistor SPT1, which is a CMOS, is turned on, and the video signal is supplied to the data signal line 61. Here, only the case where HSW1 is H is illustrated, but actually, a signal (XHSW) obtained by inverting the timing signal HSW1 is also output at the same time. In the following description, only the timing signal HSW is shown, and the inverted signal XHSW is omitted.

  Thereafter, when STH becomes L (Low) and CKH2 becomes L, the timing signal HSW1 output from the first-stage shift register 25 becomes L. As a result, the sampling transistor SPT1 is turned off, the video signal line 62 and the data signal line 61 are disconnected, and the potential of the data signal line is determined. Simultaneously with the output of the timing signal HSW1, the first-stage shift register 25 outputs a shift pulse signal SHP1, which is a signal having the same waveform as the timing signal HSW1, to the second-stage shift register 25.

  The shift pulse SHP1 output from the first-stage shift register 25 to the second-stage shift register 25 plays the same role as the start signal STH input to the first-stage shift register 25. When SHP1 becomes H and CKH2 becomes H, the timing signal HSW2 output from the second-stage shift register 25 becomes H. As a result, the sampling transistor SPT2 is turned on, and the video signal is supplied to the data signal line 61. Thereafter, when SHP1 becomes L and CKH1 becomes L, the timing signal HSW2 output from the second-stage shift register 25 becomes L. As a result, the sampling transistor SPT2 is turned off, the video signal is not supplied to the data signal line 61, and the potential of the data signal line is determined. Simultaneously with the output of the timing signal HSW2, the second-stage shift register 25 outputs a shift pulse SHP2 having the same waveform as the timing signal HSW2 to the third-stage shift register 25.

  By repeating the above operation, timing signals HSW1, HSW2, HSW3,... Are generated, and a video signal is supplied to each pixel in accordance with these signals.

  As described above, according to the present invention, the signal delay adjusting unit 104 can input the phase difference between the clock signals CKH1 and CKH2 to the shift register 25 in the same phase. As a result, for example, a desired video signal is output from the first-stage shift register 25 without HSW5 rising immediately before HSW1 falls. Accordingly, a high-quality display device can be provided without display unevenness such as vertical stripes.

  Note that there may be a slight phase shift between the clock signals CKH1 and CKH2 due to variations in the buffer circuit and the like, but the phase shift may be about 5 to 10 ns (nanoseconds) or less.

  Further, here, an example in which the STH has a pulse width corresponding to two pulses of the clock signal has been described, but the present invention is not limited to this. Generally, when the STH has a pulse width corresponding to M pulses of the clock signal, that is, when the clock signal rises or falls M times from the rising edge to the falling edge of the STH, the Nth stage shift register The (N + 2M) -th timing signal HSW (N + 2M) output from the (N + 2M) -th shift register 25 immediately before the fall of the N-th timing signal HSW (N) output from 25 ) Does not rise, a desired video signal is output from the Nth stage shift register 25.

The equivalent circuit diagram at the time of applying the display apparatus which concerns on embodiment of this invention to an organic electroluminescence display. FIG. 2 is an equivalent circuit diagram of the potential conversion circuit unit in FIG. 1. The equivalent circuit diagram of the electric potential conversion circuit part which concerns on this invention. The equivalent circuit diagram of the electric potential conversion circuit part which concerns on this invention. The equivalent circuit diagram of the electric potential conversion circuit part which concerns on this invention. The equivalent circuit diagram of the electric potential conversion circuit part which concerns on this invention. The equivalent circuit diagram of the electric potential conversion circuit part which concerns on this invention. The equivalent circuit diagram of the electric potential conversion circuit part which concerns on this invention. The timing chart figure of the horizontal driver in theory or this invention. The timing chart figure of the horizontal driver in the conventional organic electroluminescence display. The equivalent circuit diagram in the conventional organic electroluminescence display.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display panel 20 External circuit board 25 Shift register 50 Vertical driver 51 Gate signal line 60 Horizontal driver 61 Data signal line 62 Video signal line 70 Selection transistor 71 Drive transistor 72 Retention capacity 73 Organic EL element 80 VVSS
82 VVDD
100 level shifter 101 first power line (HVSS)
102 buffer circuit section 103 buffer circuit 104 signal delay adjustment section 105 first clock signal line 106 second clock signal line 107 second power supply line (HVDD)
110 Potential conversion circuit section

Claims (16)

A plurality of pixels arranged in a matrix;
A driver circuit that outputs a display signal for displaying an image on the pixel;
A first power supply line for supplying a first power supply voltage to the driver circuit;
A first clock signal line for transmitting a first clock signal for controlling the output timing of the display signal to the driver circuit;
A second clock signal line that transmits a second clock signal obtained by inverting the first clock signal to the driver circuit;
The second clock signal line intersects with the first power supply line,
The display device, wherein the first clock signal line includes a signal delay adjustment unit that overlaps with the first power supply line but does not intersect. The first and second clock signal lines are formed in the same layer,
The area of the signal delay adjustment unit in which the first clock signal line overlaps the first power supply line is equal to the area of the portion where the second clock signal line intersects the first power supply line. The display device according to claim 1. The first clock signal line extends in parallel with the first power supply line, and a part of the first clock signal line extends from the first clock signal line of the first power supply line. 2. The signal delay adjustment unit is formed by overlapping with the first power supply line by entering from a first side on an existing side and exiting from the first side. 3. The display device according to any one of 2. In a region surrounded by the first side of the first power supply line and the side of the first clock signal line, the maximum width of the region in the first side direction is the first width. The display device according to claim 3, wherein the display device is wider than a maximum width of the region in a direction perpendicular to the side. The first power supply line has a power supply line protrusion from which a part of the first power supply line protrudes,
The display device according to claim 1, wherein the signal delay adjustment unit is formed by overlapping the first clock signal line with the protruding part of the power supply line. A level shifter circuit for converting voltage levels of the first and second clock signals;
A buffer circuit unit composed of a plurality of buffer circuits having different current drive capabilities, and
The display device according to claim 1, wherein the signal delay adjustment unit is provided between the level shifter circuit and the buffer circuit unit. The display device according to claim 1, wherein the signal delay adjustment unit is provided between the buffer circuit at a predetermined stage and the buffer circuit at the next stage. The display device according to claim 1, wherein a width of the first and second clock signal lines is narrower than a width of the first power supply line. A plurality of pixels arranged in a matrix;
A driver circuit that outputs a display signal for displaying an image on the pixel;
First and second power supply lines for supplying first and second power supply voltages to the driver circuit;
A first clock signal line for transmitting a first clock signal for controlling the output timing of the display signal to the driver circuit;
A second clock signal line that transmits a second clock signal obtained by inverting the first clock signal to the driver circuit;
The second clock signal line intersects with the first power supply line,
The display device, wherein the first clock signal line includes a signal delay adjustment unit that overlaps with the second power supply line but does not intersect. The first and second clock signal lines are formed in the same layer,
The first and second power supply lines are formed in the same layer,
The area of the signal delay adjustment unit where the first clock signal line overlaps with the second power supply line is equal to the area of the portion where the second clock signal line intersects the first power supply line. The display device according to claim 9. The first clock signal line extends in parallel with the second power supply line, and a part of the first clock signal line extends from the first clock signal line of the second power supply line. 11. The signal delay adjustment unit is formed by overlapping with the second power supply line by entering from a second side on an existing side and exiting from the second side. The display apparatus in any one of. In a region surrounded by the second side of the second power supply line and the side of the first clock signal line, the maximum width of the region in the second side direction is the second width. The display device according to claim 11, wherein the display device is wider than a maximum width of the region in a direction perpendicular to the side. The second power supply line has a power supply line protruding portion from which a part of the second power supply line protrudes, and the first clock signal line overlaps with the power supply line protruding portion, so that the signal delay adjustment section The display device according to claim 9, wherein the display device is formed. A level shifter circuit for converting the voltage levels of the first and second clock signals, and a buffer circuit unit including a plurality of buffer circuits having different current driving capabilities,
The display device according to claim 9, wherein the signal delay adjustment unit is provided between the level shifter circuit and the buffer circuit unit. The display device according to claim 9, wherein the signal delay adjustment unit is provided between the buffer circuit at a predetermined stage and the buffer circuit at the next stage. 16. The display device according to claim 9, wherein a width of the first and second clock signal lines is narrower than a width of the first power supply line.

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