JP2007261095A - Data transmission apparatus, integrated circuit and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transmission apparatus for controlling a clock frequency indicating a transmission period of image data to a laser light source with respect to each of one or more laser light sources, wherein data transmission is prevented from being delayed. <P>SOLUTION: The data transmission apparatus 1 comprises a logic circuit 30 for processing image data, a writing means 41a for writing the image data processed in the logic circuit in a memory 40, and a reading means 42 for reading the image data written in the memory 40 to transmit it to a laser light source 10, with respect to each of laser light sources, wherein a frequency of a clock signal indicating a transmission period in the reading means 42 can be controlled with respect to each of two reading means and a frequency of a clock signal indicating an operation period of the logic circuit 30 is set in common in all logic circuits in which image data transmitted to the laser light source exposing a common photosensitive drum is processed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transmission apparatus that is mounted on an image forming apparatus including a plurality of exposure units and transmits image data to each of the plurality of exposure units.

  Most recent electrophotographic printers are of the type provided with a plurality of laser light sources. For example, in a printer adopting the multi-beam method, a plurality of laser light sources are configured for each photosensitive drum (for each color component). Therefore, a plurality of laser light sources are configured regardless of color / monochrome. Will be. Further, in a printer employing the single beam method, there is one laser light source per photosensitive drum, but in the case of a four-tandem color printer, there are four photosensitive drums. Four laser light sources are configured.

  In addition, as the multi-beam method described above, a two-beam method in which two laser light sources are provided for each photosensitive drum, or four laser light sources are provided for each photosensitive drum 4. There is a beam system. In the 2-beam method, two line images (latent images) are formed on the photosensitive member by one scanning, and in the four-beam method, four line images (latent images) are formed on the photosensitive member by one scanning. Image) is formed. That is, in the multi-beam method, the laser light source has a function of forming one line image per scan.

  In such a printer, image data is supplied to each of a plurality of laser light sources in accordance with the period indicated by the clock signal, and each laser light source emits a beam when the image data is supplied, and is emitted. The beam is guided to the photosensitive drum via an optical system (an optical unit including a polygon mirror, an Fθ lens, etc.), and dots (latent images) are formed on the photosensitive drum.

  In such a printer, dot misalignment may occur due to design conditions such as the arrangement of the laser light sources and the arrangement of the optical system, and environmental conditions (for example, temperature). Therefore, in order to correct such positional deviation (registration correction), it is possible to adjust the transmission cycle of image data by adjusting the frequency of the clock signal for each laser light source or for each of two or more laser light sources. Many. For example, Patent Document 1 and Patent Document 2 disclose a technique for correcting dot positional deviation in the main scanning direction by adjusting the frequency of the video clock for each laser light source.

  An example of a conventional data transmission circuit that transmits image data to a plurality of lasers is shown in FIG. The data transmission circuit 100 in FIG. 1 is a circuit used in a printer that needs to adjust the frequency of a clock signal for each of two laser light sources.

  Further, the data transmission circuit 100 of FIG. 1 can be shared with a 2-beam color printer and a 4-beam color printer.

  More specifically, when the data transmission circuit 100 of FIG. 1 is used in the two-beam system, the frequency of the clock signal is adjusted for each of two laser light sources having the same color component.

  Further, even when the data transmission circuit 100 of FIG. 1 is used in the four-beam system, the frequency of the clock signal is adjusted for each of two laser light sources having the same color component. That is, even in a 4-beam printer, the frequency of the clock signal may need to be adjusted for each of two laser light sources having the same color component. For example, in a 4-beam printer in which one optical system is shared by two laser light sources having the same color component, and different optical systems are used for each of the two laser light sources having the same color component, In order to correct the deviation of the dot formation position due to the difference in the optical system, the adjustment as described above is necessary.

  Next, the configuration of the data transmission circuit 100 will be described. As shown in FIG. 1, the data transmission circuit 100 transmits image data to laser light sources 101, 102, 103, and 104.

  When the data transmission circuit 100 is used in a two-beam color printer, the laser light sources 101 and 102 are yellow laser light sources, and the laser light sources 103 and 104 are black laser light sources. In this case, the data transfer circuit for supplying the image data to the two magenta laser light sources and the two cyan laser light sources is merely omitted, and actually, it is not included in the color printer. Is provided.

  When the data transmission circuit 100 is used in a four-beam color printer, the laser light sources 101, 102, 103, and 104 are black laser light sources. In this case, a data transmission circuit that transmits image data to the magenta laser light source, a data transmission circuit that transmits image data to the cyan laser light source, and data that transmits image data to the yellow laser light source. The transmission circuit is not shown, and is actually provided in the color printer.

  As shown in FIG. 1, the data transmission circuit 100 includes FIFOs 111, 112, 113, and 114, logic circuits 121, 122, 123, and 124, and PLLs 130 and 131. In addition, an oscillator 140 that oscillates a clock signal is provided outside the data transmission circuit 100.

  In the color printer, image data processed by an image processing unit (not shown) is once inputted to the data transmission circuit 100 and transmitted to the laser light sources 101, 102, 103, and 104 by the data transmission circuit 100. ing.

  More specifically, among image data input to the data transmission circuit 100, image data to be supplied to the laser light source 101 is transmitted in the order of a FIFO (First In First Out) 111 and a logic circuit 121 in order. After being subjected to image processing by 121, it is transmitted to the laser light source 101. Of the image data input to the data transmission circuit 100, image data to be supplied to the laser light source 102 is transmitted in the order of the FIFO 112 and the logic circuit 122, and after image processing is performed by the logic circuit 122, the laser light source 102. To be transmitted.

  Of the image data input to the data transmission circuit 100, image data to be supplied to the laser light source 103 is transmitted in the order of the FIFO 113 and the logic circuit 123, and after image processing is performed by the logic circuit 123, the laser data It is transmitted to the light source 103. Of the image data input to the data transmission circuit 100, image data to be supplied to the laser light source 104 is transmitted in the order of the FIFO 114 and the logic circuit 124, subjected to image processing by the logic circuit 124, and then the laser light source 104. To be transmitted.

  In FIG. 1, each of PLL (Phase-Locked Loop) 130 and 131 is for adjusting the frequency of the clock signal output from the oscillator 140.

  Here, the PLL 130 transmits the frequency-adjusted clock signal to the FIFOs 111 and 112 and the logic circuits 121 and 122, and the PLL 131 transmits the frequency-adjusted clock signal to the FIFOs 113 and 114 and the logic circuits 123 and 124. It is like that.

  Then, the FIFOs 111 and 112 execute transmission of image data to the logic circuits 121 and 122 at a cycle indicated by the clock signal transmitted from the PLL 130. Further, the logic circuits 121 and 122 execute image processing on the image data at a cycle indicated by the clock signal transmitted from the PLL 130, and execute transmission of the image data to the laser light sources 101 and 102. .

  The FIFOs 113 and 114 execute transmission of image data to the logic circuits 123 and 124 at a cycle indicated by the clock signal transmitted from the PLL 131. The logic circuits 123 and 124 execute image processing on the image data at a cycle indicated by the clock signal transmitted from the PLL 131, and execute transmission of the image data to the laser light sources 103 and 104. .

That is, according to the data transmission circuit 100 described above, the frequency of the clock signal adjusted by the PLL 130 indicates the operation cycle of each circuit in the previous stage of the laser light sources 101 and 102, and the clock signal adjusted by the PLL 131 The frequency indicates the operation cycle of each circuit in the previous stage of the laser light sources 103 and 104. Therefore, if the frequency in the PLL 130 and the frequency in the PLL 131 are separately adjusted, the transmission period of the image data to the laser light source can be adjusted for each of the two laser light sources.
JP 2000-221758 A (publication date: August 11, 2000) JP 10-62700 A (publication date: March 6, 1998)

  However, according to the data transmission circuit 100 shown in FIG. 1, although the transmission cycle of image data to the laser light source can be made different for each of the two laser light sources, the operation cycle of the circuit portion in the previous stage of the laser light source is asynchronous. become.

  Specifically, although the operation cycle of the logic circuit 121 and the logic circuit 122 is synchronized and the operation cycle of the logic circuit 123 and the logic circuit 124 is synchronized, the logic circuits 121 and 122 and the logic circuits 123 and 124 are synchronized. The operation cycle becomes asynchronous.

  Therefore, in the data transmission circuit 100, when performing image processing in which it is necessary to synchronize the transmission cycle and processing cycle of image data with the logic circuits 121 to 124, an input waiting time and a processing waiting time are generated. Data transmission is delayed in the circuit 100.

  An object of the present invention is to provide a data transmission circuit capable of suppressing a delay in data transmission in a data transmission apparatus that adjusts a frequency of a clock indicating a transmission cycle of image data to an exposure unit for each of one or more exposure units. .

  In order to achieve the above object, the present invention is provided in an image forming apparatus including a plurality of exposure units that expose a common image carrier, and data that transmits image data to the plurality of exposure units. In the transmission apparatus, a processing circuit for processing the image data, a writing unit for writing the image data processed by the processing circuit to the memory, and a transmission unit for reading the image data written in the memory and transmitting the data to the exposure unit. An operation clock provided for each exposure unit and configured to be able to adjust the frequency of the transmission clock indicating the transmission period in the transmission means for each of the one or more transmission means, and indicating the operation period of the processing circuit. The frequency is set in common in each processing circuit that processes image data transmitted to a plurality of exposure units that expose the common image carrier.

  According to the above configuration, even if the transmission cycle of the image data with respect to the exposure unit becomes asynchronous for each of the one or more exposure units by adjusting the frequency of the transmission clock for each of one or more transmission units, the above operation Since the frequency of the clock is common to each processing circuit that processes image data transmitted to a plurality of exposure units that expose a common image carrier, the operation cycle can be synchronized in each processing circuit. Therefore, even when performing image processing in which an input waiting time or a processing waiting time is generated unless the transmission cycle or processing cycle of the image data is synchronized with each processing circuit, such an input waiting time or There is no processing waiting time, and data transmission delay can be suppressed.

  Further, it is preferable that the frequency of the transmission clock can be adjusted within a range equal to or lower than the frequency of the operation clock.

  Thereby, the reading speed of the image data in the memory does not become faster than the writing speed. Therefore, it is possible to reduce the development man-hours by not starting the writing of the image data to the memory slightly earlier than the reading, but causing the data reading to overtake the data writing in the memory.

  In the data transmission device of the present invention, the frequency oscillated from the oscillator is used as the operation clock, the frequency of the clock oscillated from the oscillator is adjusted, and the adjusted clock is used as the transmission clock. The adjusting means is preferably provided for each of the one or more transmission means.

  According to the above configuration, the oscillation source of the operation clock and the transmission clock can be a common oscillator, the number of necessary oscillators can be reduced, and the manufacturing cost can be reduced.

  Furthermore, in the data transmission apparatus of the present invention, it is preferable that frequency adjusting means for adjusting the frequency of the clock oscillated from the oscillator and outputting the adjusted clock as the operation clock is provided.

  According to the above configuration, the frequency of the operation clock indicating the operation cycle of the processing circuit can be adjusted, and the cardboard mode can be supported.

  In the data processing apparatus of the present invention, the frequency adjusting means for adjusting the frequency of the clock oscillated from the oscillator and outputting the adjusted clock as the transmission clock is provided for each of the one or more transmission means. Preferably, there is provided selection means for selecting a transmission clock having a higher frequency from among the transmission clocks output from each frequency adjusting means and outputting the selected transmission clock as the operation clock.

  According to the above configuration, since the transmission clock having the higher frequency among the transmission clocks output from each frequency adjusting unit is used as the operation clock, it is not necessary to provide an oscillator that oscillates only the transmission clock. The number of oscillators can be reduced, which can contribute to a reduction in manufacturing cost.

  Furthermore, in the data transmission apparatus of the present invention, the data transmission device includes a determination unit that determines a transmission clock having the highest frequency among the transmission clocks output from each frequency adjustment unit, and the selection unit determines the determination result of the determination unit. It is preferable to make the above selection according to the above.

  According to the above configuration, the transmission clock having the highest frequency is identified by the determination unit, and the load on the selection unit can be reduced.

  In the data transmission apparatus of the present invention, a mirror for mirror image reversal processing may be used as the memory.

  When a mirror for mirror image reversal processing is provided, this RAM may be used as the memory. In this case, the number of memories in the data transmission apparatus can be reduced.

  Further, the data transmission device described above may be configured by an integrated circuit, and the data transmission device described above may be provided in the image forming apparatus.

  As described above, the data transmission apparatus according to the present invention includes a processing circuit that processes image data, a writing unit that writes the image data processed by the processing circuit to the memory, and an exposure by reading the image data written to the memory. A transmission means for transmitting to each of the exposure sections, and a frequency of a transmission clock indicating a transmission cycle in the transmission means is set to be adjustable for each of the one or more transmission means. In this configuration, the frequency of the operation clock indicating the operation cycle is set in common in each processing circuit that processes image data transmitted to a plurality of exposure units that expose a common image carrier.

  Therefore, even when performing image processing in which an input waiting time or a processing waiting time is generated unless the transmission cycle or processing cycle of the image data is synchronized with each processing circuit, such an input waiting time or There is no processing waiting time, and data transmission delay can be suppressed.

  An embodiment of a data transmission apparatus of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram illustrating a circuit configuration of the data transmission apparatus according to the present embodiment. Although not shown, the data transmission apparatus 1 of the present embodiment is mounted on a color printer (image forming apparatus) including a cyan photosensitive drum, a magenta photosensitive drum, a yellow photosensitive drum, and a black photosensitive drum. It is what is done. The data transmission apparatus 1 according to the present embodiment is a circuit applicable to both a so-called two-beam color printer and a four-beam color printer.

  The data transmission device 1 is used for a printer that needs to adjust the transmission cycle of image data to the laser light source (exposure unit) for each of the two laser light sources, among the printers described above. .

  The data transmission device 1 is configured by a control integrated circuit board, and receives image data from an external image processing circuit (not shown) and transmits the image data to the laser light sources 10a, 10b, 10c, and 10d. To do.

  When the data transmission apparatus 1 is applied to a two-beam color printer, the laser light sources 10a and 10b are yellow laser light sources for exposing the yellow photosensitive drum, and the laser light sources 10c and 10d are And a black laser light source for exposing the black photosensitive drum. In this case, the laser light sources of other colors (magenta and cyan) and the data transfer circuit for supplying image data to the laser light sources are merely omitted, and in reality, a color printer It shall be provided in the inside.

  When the data transmission apparatus 1 is applied to a four-beam color printer, it is assumed that any of the laser light sources 10a, 10b, 10c, and 10d is a black laser light source. Also in this case, the laser light sources of other colors (magenta, cyan, yellow) and the data transmission circuit for transmitting image data to the laser light sources are merely omitted, and in actuality color It is assumed that it is provided in the printer.

  Next, details of the configuration of the data transmission apparatus 1 will be described. As shown in FIG. 1, the data transmission apparatus 1 includes FIFOs 20a, 20b, 20c, and 20d, logic circuits 30a, 30b, 30c, and 30d, and memories 40a, 40b, 40c, and 40d.

  In the following description, the FIFO 20 is simply referred to as the FIFO 20a, 20b, 20c, 20d, and the same applies to the laser light source 10, the logic circuit 30, and the memory 40.

  In the present embodiment, a transmission path that passes through the FIFO 20a, the logic circuit 30a, the memory 40a, and the laser light source 10a in this order is referred to as a first transmission path, and transmission that passes through the FIFO 20b, the logic circuit 30b, the memory 40b, and the laser light source 10b in order. The path is referred to as a second transmission path, and a transmission path that passes through the FIFO 20c, the logic circuit 30c, the memory 40c, and the laser light source 10c in this order is referred to as a third transmission path, and passes through the FIFO 20d, the logic circuit 30d, the memory 40d, and the laser light source 10d in order. This transmission path is referred to as a fourth transmission path.

  That is, the image data supplied to the laser light source 10a is transmitted in the first transmission path, the image data supplied to the laser light source 10b is transmitted in the second transmission path, and the laser is transmitted in the third transmission path. The image data supplied to the light source 10c is transmitted, and the image data supplied to the laser light source 10d is transmitted in the fourth transmission path.

  Next, each configuration included in each transmission path will be described in detail.

  The FIFO 20a inputs image data to be supplied to the laser light source 10a from the outside, and transmits this image data to the logic circuit 30a. The FIFO 20b inputs image data to be supplied to the laser light source 10b from the outside, and transmits this image data to the logic circuit 30b. The FIFO 20c inputs image data to be supplied to the laser light source 10c from the outside, and transmits this image data to the logic circuit 30c. The FIFO 20d inputs image data to be supplied to the laser light source 10d from the outside, and transmits this image data to the logic circuit 30d.

  The logic circuit 30 is a circuit that performs image processing on the transmitted image data and transmits the image data subjected to the image processing to the memory 40. Here, examples of the image processing include gamma correction, density correction, and mark addition processing (addition processing such as a watermark).

  The logic circuit 30 has the same function, but the logic circuit 30a transmits image data to the memory 40a, the logic circuit 30b transmits image data to the memory 40b, and the logic circuit 30c transmits to the memory 40c. The logic circuit 30d transmits the image data to the memory 40d.

  In the logic circuit 30, a horizontal synchronization signal (BD signal) (not shown) is input, and processing for synchronizing the transmission start timing of image data to the memory 40 with the timing indicated by the horizontal synchronization signal is performed.

  Each of the memories 40 is provided with writing means (writing controller) and reading means (reading controller). Then, the image data transmitted to the memory 40 is written into the memory 40 by the writing means. Then, the image data written in the memory 40 is read by the reading means and transmitted to the laser light source 10 by the reading means.

  Specifically, the memory 40a is provided with a writing means 41a and a reading means 42a. The image data from the logic circuit 30a is written by the writing means 41a, and the written image data is read by the reading means 42a. It is emitted and transmitted to the laser light source 10a. The memory 40b is provided with writing means 41b and reading means 42b. The image data from the logic circuit 30b is written by the writing means 41b, and the written image data is read by the reading means 42b. Are transmitted to the laser light source 10b.

  Further, the memory 40c is provided with writing means 41c and reading means 42c. The image data from the logic circuit 30c is written by the writing means 41c, and the written image data is read by the reading means 42c. Are transmitted to the laser light source 10c. The memory 40d is provided with writing means 41d and reading means 42d. The writing means 41d writes the image data from the logic circuit 30d, and the written image data is read by the reading means 42d. Then, it is transmitted to the laser light source 10d.

  In the following, when the writing means 41 is simply referred to, the writing means 41a, 41b, 41c, and 41d are referred to, and the same applies to the reading means 42.

  With the circuit configuration as described above, image data input to the first transmission path from the outside is supplied to the laser light source 10a, image data input to the second transmission path is supplied to the laser light source 10b, and the third transmission path Is input to the laser light source 10c, and image data input to the fourth transmission path is supplied to the laser light source 10d.

  Further, as shown in FIG. 1, oscillators 61 and 62 are provided outside the data transmission apparatus 1, and PLLs 51 and 52 are provided inside the data transmission apparatus 1.

  The oscillator 61 oscillates a clock having a frequency X [MHz] and inputs this clock to the PLLs 51 and 52.

  Each of the PLLs 51 and 52 adjusts and outputs the frequency of the clock input from the oscillator 61. The clock output from the PLL 51 is transmitted to the reading means 42a and 42b, and the clock output from the PLL 52 is transmitted to the reading means 42c and 42d. In the present embodiment, the frequency of the clock output from each of the PLLs 51 and 52 is adjusted in the range of 0.97X to 1.03X [MHz]. The PLLs 51 and 52 are adjusted by a CPU (Central Processing Unit) (not shown).

  The reading means 42a and 42b read and transmit image data at a cycle indicated by the clock transmitted from the PLL 51. Further, the reading means 42c and 42d read and transmit the image data at a cycle indicated by the clock transmitted from the PLL 52.

  That is, the clock frequency indicating the transmission period of the image data for the laser light sources 10a and 10b is adjusted by the PLL 51, and the clock frequency indicating the transmission period of the image data for the laser light sources 10c and 10d is adjusted by the PLL 52. .

  Therefore, the transmission cycle of the image data for the laser light sources 10a and 10b is common and the transmission cycle of the image data for the laser light sources 10c and 10d is the same, but the transmission cycle of the image data for the laser light sources 10a and 10b and the laser light source 10c. -It becomes possible to make the transmission cycle of image data different from 10d. In the data transmission device 1 of the present embodiment, the transmission cycle of image data to the laser light source is adjusted for each of the two laser light sources in this way.

  The oscillator 62 oscillates a clock having a frequency of 1.03X [MHz] or higher. The oscillator 62 transmits the oscillated clock to all the FIFOs 20 shown in FIG. 2, all the logic circuits 30 shown in FIG. 2, and all the writing means 41 shown in FIG. . That is, the oscillator 62 processes (input / output) all the image data (image data of the same color component) that transmits the oscillated clock to at least a laser light source that exposes a common photosensitive drum. Transmit to the writing means 41.

  All of the FIFOs 20 shown in FIG. 2 transmit image data at a cycle indicated by a clock sent from the oscillator 62. Further, all the logic circuits 30 shown in FIG. 2 perform image processing and image data transmission at a period indicated by a clock sent from the oscillator 62. Further, all the writing means 41 shown in FIG. 2 write image data to the memory 40 at a period indicated by a clock sent from the oscillator 62.

  That is, in any transmission path, the operation cycles of the circuits preceding the reading unit 42, that is, the FIFO 20, the logic circuit 30, and the writing unit 41 are all synchronized.

  According to the configuration described above, the logic circuit 30 that processes the image data, the writing unit 41 that writes the image data processed by the logic circuit 30 to the memory 40, and the image data written to the memory 40 are read. Reading means 42 for transmitting to the laser light source 10 is provided for each laser light source. The frequency of a clock (transmission clock, one-dot chain line in FIG. 2) indicating the cycle of transmission of image data by the reading unit 42 is configured to be adjustable for each of the two reading units, and the operation cycle of the logic circuit 30 The frequency of the clock (operation clock, broken line in FIG. 2) indicating is set in common in all the logic circuits 30 shown in FIG.

  According to such a configuration, the frequency of the clock (transmission clock) indicating the transmission period of the image data by the reading unit 42 is adjusted for each of the two reading units, whereby the transmission cycle of the image data to the laser light source 10 is achieved. 2 becomes asynchronous with respect to each of the two laser light sources, the frequency of the clock (operation clock) indicating the operation cycle of the logic circuit 30 is common to all the logic circuits 30 shown in FIG. The operation cycles can be synchronized in all the logic circuits 30 shown in FIG. Therefore, if the transmission cycle and the processing cycle of the image data are not synchronized with all the logic circuits 30 that process the image data transmitted to the laser light source that exposes the common photosensitive drum, an input waiting time and a processing waiting time are generated. Even when such image processing is performed, such an input waiting time or processing waiting time does not occur, and a delay in data transmission can be suppressed.

  Next, image processing that causes a delay in data transmission unless the transmission cycle and processing cycle of the image data are synchronized by all the logic circuits 30 that process the image data transmitted to the laser light source that exposes the common photosensitive drum. This will be described in Examples 1 to 3 shown below.

Example 1
When the data transmission apparatus 1 is applied to a four-beam printer, the laser light sources 10a, 10b, 10c, and 10d are all light sources for exposing the black photosensitive drum.

  In one scan, the laser light sources 10a, 10b, 10c, and 10d irradiate the beam, so that four line images (latent images) are formed on the photosensitive drum. That is, one laser light source 10 forms one line image in one scan, but four line images are formed by simultaneously operating the four laser light sources 10 in one scan. become.

  In such a configuration, when a black image is corrected to be shifted in the sub-scanning direction relative to the other color image (hereinafter referred to as “sub-scanning registration correction”), the logic circuit 30 is used, and the image data If the transmission cycle and the processing cycle are not synchronized with all the logic circuits 30 that process image data transmitted to a laser light source that exposes a common photosensitive drum, a data transmission delay occurs.

  Specifically, when sub-scanning registration correction is performed, the image data transmitted from the FIFO 20a must be transmitted to the logic circuit 30 other than the logic circuit 30a without being transmitted to the logic circuit 30a. For example, as shown in FIG. 3, when performing sub-scanning registration correction in which a black image is formed by shifting by two lines in the sub-scanning direction, image data output from the FIFO 20a is transmitted to the logic circuit 30c instead of the logic circuit 30a. . That is, image data that should be originally transmitted to the logic circuit 30a (image data transmitted from the FIFO 20a) is transmitted to the logic circuit 30c.

  Therefore, if the logic circuit 30a and the logic circuit 30c are asynchronous, a waiting time occurs when image data is input from the FIFO 20a to the logic circuit 30c, and data transmission is delayed.

  In this regard, according to the data transmission apparatus 1 of the present embodiment, the operation cycles are synchronized in all the logic circuits 30 and all the FIFOs 20 that process image data transmitted to the laser light source that exposes the common photosensitive drum. . Therefore, for example, even when image data is transmitted from the FIFO 20a to any logic circuit 30a, 30b, 30c, or 30d, there is no waiting time in the asynchronous case, so that data transmission is not caused. It can be performed.

  Further, according to the configuration of the present embodiment, the operation cycles are synchronized in all the FIFOs 20 and all the logic circuits 30 that process image data transmitted to a laser light source that exposes a common photosensitive drum. Data can be directly transmitted from the FIFO 20a to any of the logic circuits 30a, 30b, 30c, and 30d. In this regard, according to the configuration of FIG. 1 (conventional configuration), for example, when image data is transmitted from the FIFO 111 to the logic circuits 123 and 124, the operation cycle of the FIFO 111 and the operation cycle of the logic circuits 123 and 124 are asynchronous. Therefore, a logic circuit for absorbing the difference in operation cycle must be provided between the FIFO 111 and the logic circuit 123 or between the FIFO 111 and the logic circuit 124, which increases the number of gates and the design man-hours. The problem arises.

(Example 2)
When a printer including the data transmission apparatus 1 inputs image data scanned at a resolution different from the resolution of the printer and performs printing based on the image data, simple interpolation processing (resolution resolution) is performed on the input image data. Conversion).

  For example, it is assumed that there is image data scanned at a resolution of 600 DPI as shown in FIG. When this image data is input to a printer having a resolution of 1200 DPI, the image data is as shown in FIG. For example, when performing simple interpolation processing for converting the image data of FIG. 4B from 600 DPI to 1200 DPI and performing sub-scanning registration correction for one line, the image data is as shown in FIG. c).

  Here, the case where the simple interpolation process and the sub-scanning registration correction shown in FIG. 4 are executed by the data transmission apparatus 1 provided in the 4-beam printer will be described below. It is assumed that the simple interpolation process is executed by the logic circuit 30.

  In this simple interpolation processing and sub-scanning registration correction, for example, the image data of the first line in FIG. 4B is obtained by simple interpolation of the image data of the second line and the image data of the third line in FIG. Will be referenced to generate.

  Therefore, when executing the simple interpolation process and the sub-scanning registration correction of FIG. 4 in the data transmission apparatus 1 of FIG. 2, it is necessary to transmit the image data output from the FIFO 20a to the logic circuits 30b and 30c. That is, when performing simple interpolation as described above, it is necessary to transmit image data output from one FIFO 20 to a plurality of logic circuits 30. Therefore, if each of the plurality of logic circuits 30 serving as transmission destinations is not synchronized, a waiting time occurs during the transmission, and data transmission is delayed.

  By the way, according to the data transmission apparatus 1 of the present embodiment, as described above, the operation cycle is synchronized in all the logic circuits 30 that process the image data transmitted to the laser light source that exposes the common photosensitive drum. Has been. Therefore, when performing image processing such that image data output from one FIFO 20 is transmitted to a plurality of logic circuits 30, since each transmission destination logic circuit is synchronized, a waiting time is brought about in the asynchronous case. Therefore, data transmission can be performed without causing a delay.

  In addition, according to such a data transmission device 1, there is an advantage that it is possible to save the trouble of asynchronous verification at the time of design, and that there is an advantage that development efficiency is improved, and there is an advantage that bugs are hardly generated at the time of operation. .

(Example 3)
In a printer, an image is printed based on image data. By calculating the density value of each pixel in the image data, it is possible to estimate and calculate a toner consumption amount when printing the image.

  Further, for example, as shown in FIG. 6, it is also possible to estimate and calculate the toner consumption amount when printing the small area by integrating the density values in the small area of 4 × 4 pixels in the image data. . In the following, a description will be given of a mode in which, in the data transmission apparatus 1 of the present embodiment, the toner consumption amount estimation calculation is performed when printing the small area.

  In order to integrate density values in a small area of 4 × 4 pixels, it is necessary to input line image data for four continuous lines to the density addition circuit. Therefore, as shown in FIG. 5, in the data transmission apparatus 1, a density addition circuit 70 is configured so that image data output from the logic circuits 30 a, 30 b, 30 c, and 30 d is input to the density addition circuit 70. . The density adding circuit 70 can integrate the density values in the small area of 4 × 4 pixels by referring to all the input image data, and can calculate the toner consumption amount when printing the small area. An estimation calculation can be performed.

  Here, if the image data transmission cycle in the logic circuits 30a, 30b, 30c, and 30d is asynchronous, a waiting time occurs when the image data is input to the density addition circuit 70, and data transmission is delayed.

  On the other hand, according to the data transmission apparatus 1 of the present embodiment, as described above, the operation cycle is performed in all the logic circuits 30 that process the image data transmitted to the laser light source that exposes the common photosensitive drum. Are synchronized. Accordingly, the transmission cycle of the image data from each logic circuit 30 to the density addition circuit 70 is synchronized, and no waiting time is brought about in the case of being asynchronous, so the density from each logic circuit 30 does not cause a delay. Data transmission to the adder circuit 70 can be realized.

(Modification 1)
Next, a modification of the data transmission apparatus of this embodiment will be described. FIG. 8 is a block diagram showing a modification of the data transmission apparatus in the present embodiment.

  In the data transmission apparatus 1 shown in FIG. 2, the clock signal oscillated by the oscillator 61 and the clock signal oscillated by the oscillator 62 are inputted. According to the data transmission apparatus 1a shown in FIG. Only the clock signal oscillated by the oscillator 63 is inputted.

  Then, according to the data transmission device 1 a shown in FIG. 8, the clock signal (frequency X [MHz]) oscillated by the oscillator 63 is input to each of the PLLs 51 and 52. Each of the PLLs 51 and 52 adjusts and outputs the frequency of the clock input from the oscillator 63. The clock output from the PLL 51 is transmitted to the reading means 42a and 42b, and the clock output from the PLL 52 is transmitted to the reading means 42c and 42d. In the data transmission device 1a, the frequency of the clock signal output from each of the PLLs 51 and 52 is adjusted in the range of 0.94X to 1.00X [MHz]. Thereby, the transmission period of the image data with respect to a laser light source can be adjusted for every two laser light sources.

  The clock signal (frequency X [MHz]) oscillated by the oscillator 63 is used for all FIFOs 20 for processing image data to be transmitted to a laser light source for exposing a common photosensitive drum, all logic circuits 30, and all writing. The information is directly input to the means 41. Thereby, it is possible to synchronize the operation cycles of the circuits preceding the reading unit 42, that is, the FIFO 20, the logic circuit 30, and the writing unit 41 in all transmission paths.

  According to the above data transmission device 1a, all the FIFOs 20, all the logic circuits 30, and all the writing means that process the image data transmitted to the laser light source for exposing the common photosensitive drum by the single oscillator 63. 41, since the clocks are supplied to the PLLs 51 and 52, the number of installed oscillators can be reduced as compared with the data transmission apparatus 1 of FIG. 2, and the manufacturing cost can be reduced.

  In the data transmission device 1a, a dual port RAM (Random Access Memory) is used as the memory 40. According to the dual port RAM, writing and reading of image data can be performed simultaneously (in parallel), so that a large amount of image data is not developed in the memory 40, and the capacity of the memory 40 can be suppressed. .

  Further, according to the data transmission device 1a, the frequency of the clock input to the writing means 41 in the memory 40 is X [MHz], whereas the frequency of the clock input to the reading means 42 is X [MHz] to 0.94X. Adjusted in the [MHz] range.

  Therefore, the reading speed of the reading means 42 in the memory 40 does not become faster than the writing speed of the writing means 41. Therefore, only by starting writing image data for one line by the writing unit 41 one pixel earlier than reading by the reading unit 42, there is no problem that the data reading overtakes the data writing. Development man-hours can be reduced.

  As shown in FIG. 7A, for one line of image data, the writing speed of the writing means 41 is up to 6% faster than the reading speed of the reading means 42 (adjusted by the PLLs 51 and 52). (If the writing speed is 1, the reading speed is 0.94).

  Therefore, as shown in FIG. 7A, when writing by the writing unit 41 and reading by the reading unit 42 are started simultaneously, 6% of the image data of one line of image data is obtained at the end of writing. It is expanded in the memory 40. Therefore, it is necessary not only to start writing by the writing means 41 one pixel earlier than reading by the reading means 42 but also to design a dual port RAM having a capacity capable of developing the above 6% image data as the memory 40. is there.

  8 may be designed such that the writing speed of the writing means 41 is slower than the reading speed of the reading means 42 (in FIG. 8, the frequency adjusted by the PLLs 51 and 52 is 1). Larger than .00X).

  However, in this case, as shown in FIG. 7B, the writing by the writing unit 41 is started earlier than the reading by the reading unit 42 to such an extent that the reading of the data overtakes the writing of the data. There is a need to. When the frequency adjusted by the PLLs 51 and 52 is changed, the speed ratio between the writing speed of the writing means 41 and the reading speed of the reading means changes. It is also necessary to perform control to adjust. Furthermore, when a small-capacity dual port RAM is used as the memory 40, if the write start timing by the writing means 41 is set too early, the capacity of the memory 40 is sufficient before the reading by the reading means 42 is started. Since the data before being read out may be overwritten, the remaining capacity of the memory 40 is monitored and control for avoiding the overwriting becomes necessary.

  In the data transmission device 1a described above, the dual port RAM is used as the memory 40. However, the present invention is not limited to such a configuration, and a single port RAM may be used as the memory 40.

  Further, for example, as shown in FIG. 2 of JP-A-2005-74638, there is a printer in which the main scanning direction is opposite between the black laser light source and the yellow laser light source. As described above, when the data transmission device 1a is applied to a printer in which the main scanning directions of the laser light sources are different from each other with different color components, the single port RAM for performing the mirror image inversion processing in the main scanning direction is used as the data. It becomes necessary to configure the transmission apparatus 1a. Therefore, if the single port RAM for this mirror image inversion process is used as the memory 40, the number of RAMs configured in the data transmission device 1a can be reduced.

(Modification 2)
Next, a second modification of the data transmission apparatus according to this embodiment will be described. FIG. 9 is a block diagram showing another modification of the data transmission apparatus in the present embodiment.

  The data transmission device 1b shown in FIG. 9 differs from the data transmission device 1a shown in FIG. 8 in that a PLL 53 is provided, and this PLL 53 transmits a clock to the FIFO 20, the logic circuit 30, and the writing means 41. Is different.

  The PLL 53 receives a clock oscillated by the oscillator 63, adjusts the frequency of this clock, and transmits the clock whose frequency is adjusted to the FIFO 20, the logic circuit 30, and the writing means 41. Each of the PLLs 51, 52, and 53 is controlled by a CPU (not shown).

  According to such a configuration, the operation cycle in the logic circuit 30 can be adjusted. In particular, the frequency of the clock input to the logic circuit 30 can be reduced by the multiplication function of the PLL 53, and it is easy to cope with the cardboard mode and the like.

(Modification 3)
Next, a third modification of the data transmission apparatus according to this embodiment will be described. FIG. 10 is a block diagram showing a third modification of the data transmission apparatus in the present embodiment.

  The data transmission device 1c shown in FIG. 10 differs from the data transmission device 1a shown in FIG. 8 in that a selector 55 is provided. The selector 55 is also provided with the FIFO 20, the logic circuit 30, and the writing means 41. Is different in that a clock is transmitted.

  The selector 55 is controlled by a CPU (not shown), inputs a clock output from the PLL 51 and a clock output from the PLL 52, compares the frequencies of both clocks, and selects the clock with the larger frequency from the FIFO 20, the logic circuit 30, Transmit to the writing means 41. Also with such a configuration, like the configuration of FIG. 8, it is only necessary to provide a single oscillator 63, and there is an advantage that the number of oscillators can be reduced.

  In addition to the selector 55 described above, a frequency comparator 56 may be provided as in the data transmission device 1d in FIG. The frequency comparator 56 is a circuit having a function of comparing the frequency of the clock output from the PLL 51 with the frequency of the clock output from the PLL 52 and selecting the clock having the larger frequency.

  Then, the frequency comparator 56 transmits identification information for identifying the selected clock to the selector 55. The selector 55 selects the clock indicated by the identification information from the clocks sent from the PLL 51 and the clock sent from the PLL 53, and sends the selected clocks to the FIFO 20, the logic circuit 30, and the writing means 41. Send. Thereby, in the selector 55, the frequency comparison process can be omitted, and the load on the CPU that controls the selector 55 can be reduced.

  Next, a configuration example of the frequency comparator 56 will be described. FIG. 12 is a block diagram showing the internal configuration of the frequency comparator 56.

  The frequency comparator 56 includes counters 91, 92, 93 and a comparator 94. When the counter 91 receives the CNTEN signal, the counter 91 transmits the CNTEN signal to the counters 92 and 93. The counter 92 starts counting the clock frequency from the PLL 51 when the CNTEN signal is transmitted, and the counter 93 starts counting the clock frequency from the PLL 52 when the CNTEN signal is transmitted.

  Further, the counter 91 counts the SYSCLK signal, and when the count number becomes equal to or greater than a predetermined value, transmits the end of counting to the counters 92 and 93. The counter 92 that has received the end of counting finishes counting the clock frequency from the PLL 51, and the counter 93 that has received the end of counting finishes counting the clock frequency from the PLL 52. Then, the comparator 94 compares the count number of the counter 92 with the count number of the counter 93. Further, based on the comparison result, the comparator 94 determines which one of the clock frequency from the PLL 51 and the clock frequency from the PLL 52 is higher, and identification information for identifying the higher frequency clock. Is transmitted to the selector 55.

  According to the above embodiment, the frequency of the clock (clock input to the reading unit) indicating the data transmission period in the reading unit is configured to be adjustable for each of the two reading units. It is only necessary that the frequency can be adjusted for each means, and the present invention is not limited to the configuration of this embodiment. For example, when the frequency of the clock input to the reading means can be adjusted for each reading means, it is necessary to individually configure a corresponding PLL for each of the reading means 42a, 42b, 42c, and 42d (that is, , Configure four PLLs).

  The data transmission apparatus 1 of the present embodiment can be applied to both a 2-beam color printer and a 4-beam color printer, but a printer capable of switching between a multi-beam method and a single-beam method. (For example, it is applicable also to the printer of FIG. 3 disclosed by Unexamined-Japanese-Patent No. 2003-114563).

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the embodiments can be obtained by appropriately combining the respective technical means disclosed in the above-described embodiments. The form is also included in the technical scope of the present invention.

  The data transmission apparatus of the present invention is suitably used for an image forming apparatus having a plurality of light sources for exposing a photosensitive material (photosensitive drum, photographic paper, etc.).

It is the block diagram which showed the circuit structure of the conventional data transmission apparatus. It is the block diagram which showed the circuit structure of the data transmission apparatus which concerns on one Embodiment of this invention. It is a figure for demonstrating subscanning registration correction | amendment. It is a figure for demonstrating a simple interpolation process. FIG. 3 is a block diagram illustrating an example of a data transmission device that includes a density addition circuit for calculating toner consumption. It is the schematic diagram which showed the small area | region of 4x4 pixel in image data. It is a figure for demonstrating the writing speed and reading speed with respect to memory about the image data for 1 line, (a) is a figure which showed the case where the writing speed is faster than the reading speed, (b) is reading It is the figure which showed the case where the speed is faster than the writing speed. It is the block diagram which showed the 1st modification of the data transmission apparatus which concerns on one Embodiment of this invention. It is the block diagram which showed the 2nd modification of the data transmission apparatus which concerns on one Embodiment of this invention. It is the block diagram which showed the 3rd modification of the data transmission apparatus which concerns on one Embodiment of this invention. It is the block diagram which showed the 4th modification of the data transmission apparatus which concerns on one Embodiment of this invention. It is the block diagram which showed the internal structure of the frequency comparator comprised by the data transmission apparatus shown in FIG.

Explanation of symbols

1 Data transmission device 10 Laser light source (exposure section)
20 FIFO
30 logic circuit (processing circuit)
40 memory 41 writing means 42 reading means 51 PLL (frequency adjusting means)
52 PLL (frequency adjusting means)
53 PLL (frequency adjusting means)
55 Selector (selection means)
56 Frequency comparator (determination means)
61 Oscillator 62 Oscillator 63 Oscillator

Claims (9)

In a data transmission apparatus provided in an image forming apparatus including a plurality of exposure units that expose a common image carrier, and transmitting image data to the plurality of exposure units,
A processing circuit that processes image data, a writing unit that writes image data processed by the processing circuit to a memory, and a transmission unit that reads the image data written in the memory and transmits the image data to the exposure unit, for each exposure unit With
The transmission clock frequency indicating the transmission cycle in the transmission means is configured to be adjustable for each of the one or more transmission means, and the frequency of the operation clock indicating the operation cycle of the processing circuit is the common image carrier. A data transmission apparatus characterized in that it is commonly set in each processing circuit for processing image data transmitted to a plurality of exposure units for exposing a body.   2. The data transmission apparatus according to claim 1, wherein the frequency of the transmission clock is adjustable within a range equal to or lower than the frequency of the operation clock. The clock oscillated from the oscillator is the above operation clock,
2. The frequency adjusting means for adjusting the frequency of a clock oscillated from the oscillator and outputting the adjusted clock as the transmission clock is provided for each of the one or more transmission means. Or the data transmission apparatus of 2.   3. The data transmission apparatus according to claim 1, further comprising frequency adjusting means for adjusting a frequency of a clock oscillated from an oscillator and outputting the adjusted clock as the operation clock. . Frequency adjusting means for adjusting the frequency of the clock oscillated from the oscillator and outputting the adjusted clock as the transmission clock is provided for each of the one or more transmission means,
2. A selection means for selecting a transmission clock having a higher frequency from among the transmission clocks output from each frequency adjusting means and outputting the selected transmission clock as the operation clock. Or the data transmission apparatus of 2. Among the transmission clocks output from each frequency adjustment means, having a determination means for determining the transmission clock having the highest frequency,
6. The data transmission apparatus according to claim 5, wherein the selection unit performs the selection according to a determination result of the determination unit.   7. The data transmission apparatus according to claim 1, wherein a mirror for mirror image reversal processing is used as the memory.   8. An integrated circuit comprising the data transmission device according to claim 1. An image forming apparatus comprising the data transmission apparatus according to claim 1.

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