JP2007259431A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which can absorb vibration of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band. <P>SOLUTION: The PLL circuit comprises, at the succeeding stage of a phase comparator, a first register 6 for storing a first parameter for controlling the loop gain, a first multiplier 7 for multiplying the output of the phase comparator 4 by a first parameter, a second register 12 for storing a second parameter for controlling the response characteristic, a second multiplier 13 for multiplying the output of the first multiplier by a second parameter, and a CPU 20 for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit used as a frequency synthesizer, and in particular, prevents deterioration of phase noise due to temperature changes and individual differences between devices, and provides stable phase noise suppression characteristics in a wide frequency band. The present invention relates to a PLL circuit.

One of the standard signal generators is a frequency synthesizer (hereinafter referred to as “PLL circuit”) using a PLL.
The PLL circuit is widely used in base stations such as mobile communication and digital terrestrial broadcasting, and has a low and stable phase noise in order to reduce the frequency interval at the time of carrier arrangement and reduce interference between adjacent carriers. Characteristics are required.

  For example, in the OFDM (Orthogonal Frequency Division Multiplexing) system, a wideband signal is transmitted by a large number of subcarriers orthogonal to each other. Therefore, if the phase noise characteristic of the OFDM signal deteriorates, it becomes frequency fluctuation as it is. As a result, the orthogonality of the subcarriers may be lost and the carrier cannot be identified.

A conventional PLL circuit will be described with reference to FIG. FIG. 7 is a schematic block diagram of a conventional PLL circuit.
As shown in FIG. 7, the conventional PLL circuit divides the output frequency branched from the VCO (Voltage Controlled Oscillator) 1 that oscillates the frequency according to the control voltage by 1 / N. 1 / N frequency divider 2, A / D converter 3 for A / D (analog / digital) conversion of the divided frequency, reference oscillator 5 for oscillating a fixed reference frequency, and A / D conversion A phase comparator 4 for comparing the phase difference between the output from the unit 3 and a reference frequency, a digital filter 10 'as a loop filter for time-integrating the phase difference by an integrating circuit and outputting a pulse as a control voltage value; It comprises a D / A converter 8 that D / A (digital / analog) converts the control voltage value, and an analog filter 9 that smoothes the signal and outputs the control voltage.
The phase comparator 4 is usually realized by a PLLIC. The frequency divider 2 uses a normal counter.

  In the PLL circuit having the above-described configuration, the oscillation frequency output from the VCO 1 is branched, frequency-divided to 1 / N by the 1 / N frequency divider 2, and converted to a digital signal by the A / D converter 3. The phase comparator 4 compares the phase with the reference frequency from the reference oscillator 5 and outputs a phase difference.

  Then, the detected phase difference is integrated for a certain time by the digital filter 10 ′ to output an integrated value, converted to an analog signal by the D / A converter 8, smoothed by the analog filter 9, and the control voltage is Generated and provided to VCO1. The VCO 1 oscillates at a frequency corresponding to the input control voltage. In this way, the PLL circuit performs feedback control to match the phase of the oscillation frequency of the VCO 1 with the phase of the reference frequency.

  In general, the natural frequency fN in the PLL circuit is obtained by fN = (√K0) / 2π. Here, K0 is a loop gain. The phase noise characteristic is obtained by optimizing the loop gain to obtain a desired amount of suppression.

  The parameters affecting the loop gain are the parameters shown in (1) to (4) of FIG. 8, (1) Kp: phase detection conversion gain, (2) A (s): loop filter transfer function, ( 3) B: Weight per bit at the output of the D / A converter 8; (4) Kv: VCO conversion gain (VF sensitivity).

The value of each parameter is calculated based on the following formula.
(1) Kp = (2πA ₀ ² / fs × N) × fs / 2π [V / radian]
(2) A (s) = fs / N _L [V / V]
(3) B: Output voltage width / number of bits of D / A converter 8 (4) Kv is an eigenvalue of VCO [Hz / V]
Here, A ₀ is a half value of the amplitude of the I and Q signals subjected to quadrature detection, fs is the sampling frequency, N is a frequency division ratio by the frequency divider 2, and N _L is a frequency division ratio at the time of integration. is there.

The loop gain K0 is obtained by multiplying the parameters (1) to (4) shown in FIG.
That is, K0 = (1) × (2) × (3) × (4) = Kp × A (s) × B × Kv
As a result, K0 becomes a fixed value, and the suppression amount of phase noise is also constant.

As a conventional technique related to the PLL circuit, Japanese Patent Application Laid-Open No. 2003-168975 “Phase Locked Loop Circuit and Clock Recovery Circuit” (Applicant: NEC Corporation, Inventor: Eimi Noguchi) published on June 13, 2003 is disclosed. Yes (see Patent Document 1).
This prior art uses an analog type phase comparator, a first control loop that performs oscillation control based on the phase difference detection output, and a signal in which the component near the direct current of the phase difference detection output is increased. A phase-locked loop circuit and a clock recovery circuit including a second control loop that performs oscillation control in response to the first control loop and performs lower-speed control than the first control loop, thereby increasing jitter while increasing the lock range. The jitter tolerance can be increased by suppressing.

As another prior art, Japanese Patent Application Laid-Open No. 2005-33581 “Fractional-N Phase-Locked Loop Synthesizer” (Applicant: Mitsubishi Electric Corporation, Inventor: Kenichi Tajima) published on February 3, 2005 (See Patent Document 2).
In this prior art, a feedback circuit that generates a synchronization signal from a high-frequency signal from a voltage-controlled oscillator corresponds to a plurality of variable frequency dividers that divide a high-frequency signal and output a synchronization signal, and a variable frequency divider. This is a fractional-N type phase-locked loop type frequency synthesizer equipped with a modulation circuit that outputs a control signal for each variable frequency divider in accordance with a clock signal, thereby enabling high-speed and stable operation. is there.

JP 2003-168975 A (page 4-7, FIG. 1) Japanese Patent Laying-Open No. 2005-33581 (page 4-7, FIG. 1)

  However, the conventional PLL circuit has a problem that the suppression characteristic of the phase noise is easily influenced by the environmental temperature, and a stable suppression characteristic cannot be obtained at an installation place where the temperature fluctuation is large.

  Further, in the conventional PLL circuit, the suppression characteristic is also affected by the characteristic variation of each component constituting the PLL circuit, and there is a problem that individual differences occur for each device.

  Further, the conventional PLL circuit has a problem that it is difficult to obtain a stable suppression characteristic over a wide frequency band.

  The present invention has been made in view of the above-described circumstances, and is a PLL circuit that can absorb fluctuations in phase noise characteristics due to temperature changes and component characteristic variations, and can obtain stable phase noise suppression characteristics in a wide frequency band. The purpose is to provide.

  The present invention for solving the problems of the conventional example includes a voltage controlled oscillator that oscillates a frequency according to a control voltage, a reference frequency oscillator that oscillates a constant frequency, an output frequency of the voltage controlled oscillator, and a reference frequency oscillator A phase comparator that compares the output frequency and outputs a phase difference, and a loop filter that generates a control voltage based on the phase difference. The present invention is characterized by comprising loop gain variable means for making the loop gain of the circuit variable.

  Further, the present invention for solving the problems of the above-described conventional example includes a voltage controlled oscillator that oscillates a frequency according to a control voltage, a reference frequency oscillator that oscillates a constant frequency, an output frequency of the voltage controlled oscillator, and a reference A PLL circuit comprising a phase comparator that compares the output frequency of a frequency oscillator and outputs a phase difference, and a loop filter that generates a control voltage based on the phase difference. Further, there is provided a response characteristic varying means for varying the response characteristic of the circuit.

  Further, the present invention for solving the problems of the above-described conventional example includes a voltage controlled oscillator that oscillates a frequency according to a control voltage, a reference frequency oscillator that oscillates a constant frequency, an output frequency of the voltage controlled oscillator, and a reference A PLL circuit comprising a phase comparator that compares the output frequency of a frequency oscillator and outputs a phase difference, and a loop filter that generates a control voltage based on the phase difference. The circuit includes a loop gain variable means for changing the loop gain value of the circuit and a response characteristic variable means for changing the response characteristic of the circuit.

  Further, the present invention for solving the problems of the conventional example is that, in the PLL circuit, the loop gain varying means includes a first register for storing the first parameter and an output from the phase comparator. And a first multiplier that multiplies the first parameter output from the first register, and includes a control unit that sets the first parameter in the first register based on the state of the apparatus and usage conditions. It is characterized by that.

  Further, the present invention for solving the problems of the above conventional example is that, in the PLL circuit, the response characteristic variable means includes a second register for storing the second parameter and an output from the phase comparator. And a second multiplier that multiplies the second parameter output from the second register, and includes a control unit that sets the second parameter in the second register based on the state of the apparatus and usage conditions. It is characterized by that.

  Further, the present invention for solving the problems of the conventional example is that, in the PLL circuit, the loop gain varying means includes a first register for storing the first parameter and an output from the phase comparator. A first multiplier that multiplies the first parameter output from the first register, and the response characteristic variable means stores the second register that stores the second parameter, and the output of the first multiplier. And a second multiplier that multiplies the output from the first multiplier by the second parameter output from the second register, and is based on the state of the device and the usage conditions The first register is set in the first register, and the second register is provided with a control unit for setting the second parameter.

  Further, the present invention for solving the problems of the above conventional example is the first default as a parameter set in the first and second registers in order to compensate for individual differences in the PLL circuit. Temperature table for storing the first temperature parameter and the second temperature parameter as correction values for correcting the parameter, the second default parameter, and the first and second default parameters according to the temperature, corresponding to the temperature And a temperature sensor for detecting the temperature, and the control unit refers to the temperature table according to the detected temperature from the temperature sensor, and sets the first default parameter and the detected temperature. The sum of the corresponding first temperature parameter is set as the first parameter in the first register, and the second default parameter and the first temperature parameter corresponding to the detected temperature are set. It is characterized by setting the sum of the temperature parameters of the second register as the second parameter.

  Further, according to the present invention for solving the problems of the conventional example described above, in the PLL circuit, the correction value memory includes a temperature table corresponding to a plurality of use frequency bands, and the control unit has a use frequency band from the outside. When set, the temperature table corresponding to the set use frequency band is referred to.

  According to the present invention, the voltage controlled oscillator that oscillates the frequency according to the control voltage, the reference frequency oscillator that oscillates a constant frequency, the output frequency of the voltage controlled oscillator and the output frequency of the reference frequency oscillator are compared and compared. A PLL circuit comprising a phase comparator that outputs a phase difference and a loop filter that generates a control voltage based on the phase difference, wherein the loop gain of the circuit is variable at the output stage of the phase comparator Since the PLL circuit includes the gain varying means, there is an effect that the loop gain can be adjusted to stabilize the phase noise suppression characteristic in a wide frequency band.

  Further, according to the present invention, the voltage controlled oscillator that oscillates the frequency according to the control voltage, the reference frequency oscillator that oscillates a constant frequency, the output frequency of the voltage controlled oscillator and the output frequency of the reference frequency oscillator are compared. A phase comparator that outputs a phase difference and a loop filter that generates a control voltage based on the phase difference, and the response characteristic of the circuit is variable at the output stage of the phase comparator. Since the PLL circuit is provided with the response characteristic varying means, there is an effect that the response characteristic can be adjusted to stabilize the phase noise suppression characteristic in a wide frequency band.

  Further, according to the present invention, the voltage controlled oscillator that oscillates the frequency according to the control voltage, the reference frequency oscillator that oscillates a constant frequency, the output frequency of the voltage controlled oscillator and the output frequency of the reference frequency oscillator are compared. PLL circuit composed of a phase comparator that outputs a phase difference and a loop filter that generates a control voltage based on the phase difference, and a loop gain value of the circuit is set to the output stage of the phase comparator. Since the PLL circuit includes a variable loop gain variable means and a response characteristic variable means for changing the response characteristic of the circuit, the loop gain and the response characteristic are adjusted to optimize the phase noise suppression characteristic. The phase noise suppression characteristic can be stabilized over a wide frequency range.

  According to the invention, the loop gain variable means multiplies the first register that stores the first parameter and the output from the phase comparator by the first parameter output from the first register. Since the PLL circuit includes a control unit configured to set the first parameter in the first register based on the state and use conditions of the device, the device state and use conditions are configured. The loop gain is adjusted according to the above, and the phase noise suppression characteristic can be optimized in a wide frequency range.

  According to the present invention, the response characteristic varying means multiplies the second register storing the second parameter and the output from the phase comparator by the second parameter output from the second register. Since the PLL circuit includes a control unit configured to set a second parameter in the second register based on the state and use conditions of the device, the device state and use conditions are configured. The response characteristic is adjusted according to the above, and the phase noise suppression characteristic can be optimized in a wide frequency range.

  According to the invention, the loop gain variable means multiplies the first register that stores the first parameter and the output from the phase comparator by the first parameter output from the first register. And a response characteristic varying means for branching and inputting the second register for storing the second parameter and the output of the first multiplier, and from the first multiplier. And a second multiplier that multiplies the output by the second parameter output from the second register, and sets the first parameter in the first register based on the state of the apparatus and usage conditions In addition, since the PLL circuit is provided with a control unit for setting the second parameter in the second register, the loop gain and the response characteristics are adjusted according to the state of the apparatus and the use conditions, and the phase noise is suppressed. Optimize properties, There is an effect that it is possible to obtain a stable suppression characteristic in the stomach frequency range.

  In addition, according to the present invention, the first default parameter and the second default parameter as parameters set in the first and second registers to compensate for individual differences between the devices, and the first and second parameters. A correction value memory that stores a temperature table that stores the first temperature parameter and the second temperature parameter corresponding to the temperature as correction values for correcting the default parameter according to the temperature, and a temperature for detecting the temperature And a control unit refers to a temperature table in accordance with a detected temperature from the temperature sensor, and calculates a sum of a first default parameter and a first temperature parameter corresponding to the detected temperature as a first The parameter is set in the first register, and the sum of the second default parameter and the second temperature parameter corresponding to the detected temperature is set as the second parameter. Since the PLL circuit set in the register is used, the default parameter compensated for individual device differences can be further corrected according to the temperature and set in the first register and the second register. This has the effect of reducing the influence, realizing the optimum loop gain and response characteristics, and stabilizing the phase noise suppression characteristics in a wide frequency band.

  According to the present invention, the correction value memory includes a temperature table corresponding to a plurality of use frequency bands, and the control unit corresponds to the set use frequency band when the use frequency band is set from the outside. Since the PLL circuit referring to the temperature table is used, it is possible to perform temperature correction according to the used frequency band, and to perform correction with higher accuracy to stabilize the phase noise suppression characteristics in a wide frequency band. effective.

Embodiments of the present invention will be described with reference to the drawings.
The PLL circuit according to the embodiment of the present invention includes a first register that stores a first parameter for adjusting a loop gain, and a first parameter multiplied by an output from the phase comparator, following the phase comparator. A second multiplier for storing a second parameter for adjusting a damping factor (response characteristic), and a second multiplier for multiplying the output of the first multiplier by the second parameter And a control unit for setting optimum parameters in the first and second registers according to the use frequency band / ambient temperature / individual difference of the device, and the use frequency band / ambient temperature / device. By adjusting the loop gain and damping factor to optimum values based on the individual differences, stable phase noise suppression characteristics can be obtained in a wide frequency band.

FIG. 1 is a block diagram showing the configuration of a PLL circuit according to an embodiment of the present invention. In addition, the same code | symbol is attached | subjected and demonstrated about the part which has the structure similar to FIG.
As shown in FIG. 1, the PLL circuit (this device) according to the present embodiment includes a VCO 1, a 1 / N frequency divider 2, an A / D, and the like as the conventional PLL circuit shown in FIG. A converter 3, a phase comparator 4, a reference oscillator 5, an A / D converter 8, and an analog filter 9 are provided. As a characteristic part of this apparatus, a first register (“register (1) in the figure) ], A first multiplier 7, a digital filter 10 as a loop filter, a CPU (Central Processing Unit) 20, a correction value memory 21, and a temperature sensor 22.
The digital filter 10 further includes an integration circuit 11, a second register (“register (2)” in the figure) 12, and a multiplier 13.

The characteristic part of this apparatus is demonstrated.
The first register 6 stores a first parameter to be multiplied by the output from the phase comparator 4. The first parameter is a frequency correction coefficient for making the frequency band in which a good suppression characteristic can be obtained variable, and an optimum value is set by the CPU 20 according to the operating frequency band, the ambient temperature, and the individual difference of the device. Is done. The operation of the CPU 20 will be described later.

  The first multiplier 7 multiplies the phase difference output from the phase comparator 4 by the first parameter output from the first register.

  In this apparatus, the first register 6 and the first multiplier 7 are provided as means for making the loop gain variable, and the output from the first multiplier 7 is set by appropriately setting the first parameter from the CPU 20. It is possible to change the loop gain of the PLL according to the frequency band and temperature used, and to adjust to the appropriate loop gain in a wide frequency band to obtain stable phase noise suppression characteristics Is.

  The second register 12 stores a second parameter to be multiplied by the output from the first multiplier 7. The second parameter adjusts a damping factor (response characteristic), and an optimum value is set by the CPU 20 according to the operating frequency band, the ambient temperature, and the individual difference of the device. The operation of the CPU 20 will be described later.

  The second multiplier 13 multiplies the output from the first multiplier 7 by the second parameter output from the second register 12. Then, the multiplication result in the second multiplier is added to the output of the integration circuit 11 and becomes the output of the digital filter 10.

  In this apparatus, the second register 12 and the second multiplier 13 are provided as means for making the damping factor variable, and the damping factor can be changed by appropriately setting the second parameter from the CPU 20. Thus, the individual difference in the response time of the device is compensated so that stable phase noise suppression characteristics can be obtained. In particular, it is possible to suppress the rise of suppression characteristics due to excessive loop gain.

The temperature sensor 22 periodically detects the temperature around the apparatus and outputs it to the CPU 20.
Further, the correction value memory 21 stores various data used when the CPU 20 generates the first and second parameters set in the first register 6 and the second register 12. The stored data includes a default parameter that compensates for individual differences, information on a used frequency band, and a temperature correction value corresponding to the used frequency band.

Before specifically describing the data stored in the correction value memory 21, the calculation method of the first and second parameters in this apparatus and the types of parameters used therein will be briefly described.
First, in this apparatus, default parameters C1 and C2 subjected to individual difference compensation are used as correction values as parameters set in the first and second registers so that optimum phase noise characteristics can be obtained under standard use conditions. Stored in the memory 21.

  As parameters for correcting the default parameters C1 and C2, there are temperature parameters p1 and p2 for correcting according to the temperature, and each has a table for each frequency subdivided according to the used frequency.

The parameters stored in the correction value memory 21 will be specifically described.
First, in the correction value memory 21, as the default value of the first parameter set in the first register 6, as the default value of the first parameter C 1 and the second parameter set in the second register 12. The second default parameter C2 is stored.
The default parameter is experimentally determined as a value that can obtain the optimum phase noise characteristics at the center frequency of the frequency band in which this device is usually most commonly used at room temperature, and is caused by variations in the characteristics of the components of the device. This value is determined so as to compensate for individual differences between the devices to be corrected, and is written in the correction value memory 21 in advance.

  That is, when this apparatus having average operating characteristics is operated under apparatus conditions (frequency and temperature) for which default parameters are determined, the first parameter set in the first register 6 is the first parameter. 1 is the default parameter C1, and the second parameter set in the second register 12 is the second default parameter C2.

The correction value memory 21 further includes a temperature table that stores coefficients for correcting the default parameters C1 and C2 in accordance with the frequency band and temperature actually used.
Here, the temperature table will be described with reference to FIG. FIG. 2 is an explanatory diagram of a temperature table stored in the correction value memory 21.
As shown in FIG. 2, the temperature table stores a temperature parameter p1 for correcting the default parameter C1 set in the first register 6 corresponding to the measured temperature (t), and stores in the second register 12. A temperature parameter p2 for correcting the set default parameter C2 is stored. The temperature parameters p1 and p2 are experimentally obtained in advance and are written in the correction value memory 21.

As a feature of this apparatus, three types of temperature tables are provided for the low frequency band (Low ch), the intermediate frequency band (Middle ch), and the high frequency band (High ch). In the example of FIG. 2, an example of a temperature table corresponding to any one frequency band is shown. When the frequency band to be used is set by the setting unit, the CPU 20 selects and reads a temperature table corresponding to the frequency band, and performs the following processing with reference to the selected temperature table. .
By providing a temperature table for each frequency band, more accurate temperature correction can be performed according to the used frequency band. Further, when the frequency band is wide, it can be dealt with by increasing the temperature table according to the frequency.

The temperature table stores temperature parameters corresponding to a temperature range of 20 degrees with respect to a temperature range of −30 ° C. to 70 ° C. For example, when the measured temperature (t) is 25 ° C., the corresponding temperature parameter p1 is stored as 1.0 and p2 is stored as 0.7, and when the measured temperature (t) is 0 ° C., p1 is 0.9. , P2 is stored as 0.8. The temperature range may be divided into finer steps or fewer depending on the characteristics of the apparatus.
When the measured temperature is outside the appropriate temperature range set separately, the CPU 20 detects (outputs) a temperature alarm.

Then, the CPU 20 reads a temperature table corresponding to the operating frequency, periodically reads the measured temperature (t) from the temperature sensor 22, and reads the temperature parameter corresponding to the measured temperature with reference to the temperature table. Thus, the first parameter and the second parameter are generated by adding the temperature parameter p1 or p2 to the default parameter C1 or C2, and are written in the first register 6 and the second register 12.
Specifically, the first parameter set in the first register is C1 + p1, and the second parameter set in the second register is C2 + p2.

Next, the CPU 20 will be described.
The CPU 20 sets the optimum first parameter for the first register 6 and the optimum second parameter for the second register 12 in accordance with the operating frequency band, the ambient temperature, and the individual differences of the devices. is there.

  Although not shown, the CPU 20 is connected to a setting unit operated by an operator from the outside, and a frequency band in which the apparatus is used is input from the setting unit. The frequency band includes a low frequency band (Low ch), an intermediate frequency band (Middle ch), and a high frequency band (High ch), and any one of them is set by the setting unit.

Then, the CPU 20 holds the set frequency band in a storage unit (not shown) inside the CPU 20, and as described above, the correction value memory 21 is set according to the set frequency band before the operation of the apparatus is started. Read the corresponding temperature table from.
Further, the CPU 20 reads default parameters C1 and C2 for compensating for individual differences from the correction value memory 21 and holds them before the operation is started.

  After the start of operation, the measured temperature from the temperature sensor 22 is periodically input, and the first and second parameters are calculated by multiplying the individual difference corrected parameter by the temperature parameter based on the temperature table. A process for updating and setting the first register 6 and the second register 12 (temperature monitoring process) is performed.

Processing in the CPU 20 will be described with reference to FIG. FIG. 3 is a flowchart showing processing in the CPU 20.
As shown in FIG. 3, before operation, first, individual adjustment is performed based on a characteristic check at the center frequency of the used frequency band at room temperature in order to absorb variations in the characteristics of the components constituting the PLL. S1), default parameters C1 and C2 for compensating for individual differences are written in the correction value memory 21 (S2).
Then, the CPU 20 reads the first and second default parameters C1 and C2 stored in the correction value memory and holds them inside.

  Then, the CPU 20 determines whether the use frequency band set by the setting unit is a low frequency band (Low ch), an intermediate frequency band (Middle ch), or a high frequency band (High ch) (S4). If the operating frequency band is the low frequency band (Low ch), the temperature table for the low frequency band is read from the correction value memory 21 and held (S5). And CPU20 performs the temperature monitoring process which calculates the 1st and 2nd parameter according to temperature (S6). The temperature monitoring process will be described later.

  If the use frequency band is an intermediate frequency band (Middle ch), the CPU 20 reads and holds the temperature table for the intermediate frequency band from the correction value memory 21 (S7). A temperature monitoring process for calculating the second parameter is performed (S8).

Similarly, if the use frequency band is a high frequency band (High ch), the CPU 20 reads and holds the temperature table for the high frequency band from the correction value memory 21 (S9), and the first is determined according to the temperature. And the temperature monitoring process which calculates a 2nd parameter is performed (S10).
In this way, processing in the CPU 20 is performed.

Next, the temperature monitoring process shown in S6, S8, and S10 in FIG. 3 will be described with reference to FIG. FIG. 4 is a flowchart of the temperature monitoring process in the CPU 20.
As shown in FIG. 4, when the temperature monitoring process is started, the CPU 20 periodically reads the temperature measured by the temperature sensor 22 (S11), and the measured temperature is within an appropriate temperature range in which the apparatus can operate properly. Whether it is (appropriate) or not (S12).

  If the measured temperature is within the appropriate temperature range, the CPU 20 reads the temperature parameters p1 and p2 corresponding to the measured temperature from the temperature table, and adds p1 to the first default parameter C1 held inside. As the first parameter, p2 is added to the second default parameter C2 to obtain the second parameter, and the first parameter is written to the first register 6 and the second parameter is written to the second register 12. (S13), the process proceeds to S11.

If the measured temperature is outside the appropriate temperature range in S12, the CPU 20 detects (outputs) a temperature alarm (S14).
In this way, the temperature monitoring process of the CPU 20 is performed.

  With the processing shown in FIGS. 3 and 4, the present apparatus refers to the temperature table in which the optimum correction parameter corresponding to the operating frequency is stored based on the default parameters C <b> 1 and C <b> 2 in which variations due to individual differences are compensated. Then, the first parameter 6 and the second register 12 are calculated by correcting the default parameter according to the temperature parameter corresponding to the temperature periodically measured by the temperature sensor 22 and calculating the first and second parameters. By setting to, it is possible to always set optimal parameters in the first register 6 and the second register 12 in accordance with the frequency band / temperature / individual difference of the device, and to change the loop gain and the damping factor. Thus, a PLL circuit that obtains stable phase noise suppression characteristics in a wide frequency band can be obtained.

Next, the effect obtained by providing the first register 6 and the first multiplier 7 will be described with reference to FIG. FIG. 5 is an explanatory diagram showing an effect obtained by providing the first register 6 and the first multiplier 7.
As shown in FIG. 5, in the graph of the detuning frequency and the phase noise suppression, the loop suppression bandwidth capable of obtaining an appropriate phase noise suppression characteristic is expressed as an inflection point of the graph. In the example of FIG. 5, the phase noise characteristic in the standard case where the first register 6 and the first multiplier 7 are not provided is indicated by a solid line, the first register 6 and the first multiplier 7 are provided, An example in which the value of a parameter set in one register 6 is changed is indicated by a broken line and a dashed line.

  In the example of FIG. 5, the curve indicated by the broken line indicates the phase noise characteristic in which the peak is shifted to the low frequency side compared to the standard case, and the curve indicated by the dashed line is the peak compared to the standard case. Shows the phase noise characteristic shifted to the high frequency side, and the loop suppression bandwidth can be changed according to the parameter value.

  As described above, the variable range of the suppression band can be further widened by giving a range to the parameter value set in the first register 6 and adjusting the correction value so that a wide range of values can be set. It is.

Next, effects obtained by providing the second register 12 and the second multiplier 13 will be described with reference to FIG. FIG. 6 is an explanatory diagram showing an effect obtained by providing the second register 12 and the second multiplier 13.
In the example of FIG. 6, the phase noise characteristic when the second register 12 and the second multiplier 13 are not provided is indicated by a solid line, the second register 12 and the second multiplier 13 are provided, An example in which the value of a parameter set in the register 12 is changed is indicated by a broken line and a one-dot broken line.

  As shown in FIG. 6, by changing the parameter value set in the second register 12, the damping factor can be changed to change the speed of response, and the peak position of the phase noise can be changed without changing the peak position. Phase noise characteristics having different heights can be obtained. Using this, it is possible to set the value of the second parameter so as to obtain a desired characteristic.

  Furthermore, the variable range of the damping factor can be further widened by giving a range to the parameter value set in the second register 12 and adjusting the correction value so that a wide range of values can be set. .

  That is, in the present PLL circuit, the loop gain and the damping factor can be made variable by adjusting the parameters set in the first register 6 and the second register 12, as shown in FIGS. The desired phase noise characteristics can be obtained.

  According to the PLL circuit (this device) according to the embodiment of the present invention, the first register 6 for storing the first parameter for adjusting the loop gain and the phase comparator 4 are arranged in the subsequent stage of the phase comparator. A first multiplier 7 that multiplies the output from the first parameter, a second register 12 that stores a second parameter for adjusting the damping factor, and a second output to the output of the first multiplier. A second multiplier 13 that multiplies the parameters, and a CPU 20 that sets optimal parameters in the first and second registers according to the operating frequency band, the ambient temperature, and the individual differences of the devices. The CPU 20 can adjust the loop gain and damping factor to the optimum values based on the frequency band used, ambient temperature, and individual differences of devices, and stable phase noise suppression characteristics can be obtained in a wide frequency band. There is that effect.

  In addition, according to the present apparatus, the correction value memory 21 that stores the parameters used when calculating the first parameter and the second parameter, and the temperature sensor 22 that measures the temperature around the apparatus are provided, and the correction value memory 21 stores, in advance, default parameters C1 and C2 experimentally obtained so as to compensate for individual differences under standard use conditions, and temperature parameters p1 and p2 for correcting the default parameters according to the temperature. However, before the operation of the apparatus is started, the default parameters C1 and C2 are read and held inside. When the operation is started, the temperature parameters p1 and p2 corresponding to the measured temperature detected by the temperature sensor 22 are set to C1. , C2 to calculate the first and second parameters and set them in the first register 6 and the second register 12, respectively. Therefore, the default parameter is set based on the individual difference of the device before the operation is started, and after the operation is started, the default parameter is further corrected with the corresponding temperature parameter according to the temperature environment, and the first and second Appropriate parameters corrected for individual differences and temperature of the device can be set in the register, and the loop gain and damping factor can be adjusted to the optimum values to achieve stable phase noise suppression characteristics over a wide frequency band. There is an effect to be obtained.

  Furthermore, according to this apparatus, since the temperature table which memorize | stored the temperature parameter which changes according to a use frequency band as a temperature parameter is memorize | stored in the correction value memory 21, CPU20 sets the frequency band to be used. Then, the temperature table corresponding to the frequency band is read from the correction value memory 21 and the temperature correction can be performed with reference to the temperature table, and the optimum parameter subjected to fine temperature correction according to the frequency is set to the first parameter. The second register and the second register can be set, and the loop gain and the damping factor are adjusted to optimum values, so that a stable phase noise suppression characteristic can be obtained in a wide frequency band.

  The present invention is suitable for a PLL circuit that prevents phase noise deterioration based on temperature changes and individual differences between apparatuses and that provides stable phase noise suppression characteristics in a wide frequency band.

1 is a configuration block diagram of a PLL circuit according to an embodiment of the present invention. It is explanatory drawing of the temperature table memorize | stored in the correction value memory. It is a flowchart figure which shows the process in CPU20. It is a flowchart figure of the temperature monitoring process in CPU20. It is explanatory drawing which shows the effect by having provided the 1st register | resistor 6 and the 1st multiplier 7. FIG. It is explanatory drawing which shows the effect by having provided the 2nd register | resistor 12 and the 2nd multiplier 13. FIG. It is a schematic block diagram of a conventional PLL circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... VCO, 2 ... 1 / N frequency divider, 3 ... A / D converter, 4 ... Phase comparator, 5 ... Reference oscillator, 6 ... 1st register, 7 ... 1st multiplier, 8 ... D / A converter, 9 ... analog filter, 10 ... digital filter, 11 ... integration circuit, 12 ... second register, 13 ... second multiplier, 20 ... CPU, 21 ... correction value memory, 22 ... temperature sensor

Claims (8)

A voltage controlled oscillator that oscillates a frequency according to a control voltage, a reference frequency oscillator that oscillates a constant frequency, and compares the output frequency of the voltage controlled oscillator and the output frequency of the reference frequency oscillator to output a phase difference A PLL circuit including a phase comparator and a loop filter that generates a control voltage based on the phase difference,
A PLL circuit comprising loop gain variable means for varying the loop gain of the circuit at the output stage of the phase comparator. A voltage controlled oscillator that oscillates a frequency according to a control voltage, a reference frequency oscillator that oscillates a constant frequency, and compares the output frequency of the voltage controlled oscillator and the output frequency of the reference frequency oscillator to output a phase difference A PLL circuit including a phase comparator and a loop filter that generates a control voltage based on the phase difference,
A PLL circuit comprising response characteristic varying means for varying the response characteristic of the circuit at an output stage of the phase comparator. A voltage controlled oscillator that oscillates a frequency according to a control voltage, a reference frequency oscillator that oscillates a constant frequency, and compares the output frequency of the voltage controlled oscillator and the output frequency of the reference frequency oscillator to output a phase difference A PLL circuit including a phase comparator and a loop filter that generates a control voltage based on the phase difference,
A PLL circuit comprising: an output stage of the phase comparator; loop gain variable means for changing a loop gain value of the circuit; and response characteristic variable means for changing the response characteristic of the circuit. . A first register for storing a first parameter;
A first multiplier that multiplies the output from the phase comparator by the first parameter output from the first register;
The PLL circuit according to claim 1, further comprising: a controller configured to set a first parameter based on a state of the device and a use condition in the first register. A response characteristic varying means, a second register for storing a second parameter;
A second multiplier that multiplies the output from the phase comparator by the second parameter output from the second register;
The PLL circuit according to claim 2, further comprising a control unit that sets a second parameter based on a state of the apparatus and a use condition in the second register. A first gain register for storing a first parameter; and a first multiplier for multiplying the output from the phase comparator by the first parameter output from the first register; Consisting of
The response characteristic variable means branches and inputs the second register for storing the second parameter and the output of the first multiplier, and outputs from the second register to the output from the first multiplier. A second multiplier for multiplying the output second parameter,
A control unit that sets a first parameter in the first register and sets a second parameter in the second register based on a state of the apparatus and a use condition is provided. The PLL circuit according to claim 3. First and second default parameters as parameters set in the first and second registers to compensate for individual differences between devices, and the first and second default parameters according to temperature A correction value memory for storing a temperature table for storing the first temperature parameter and the second temperature parameter as correction values to be corrected according to the temperature;
A temperature sensor for detecting the temperature,
The control unit refers to the temperature table according to the detected temperature from the temperature sensor, and uses the sum of the first default parameter and the first temperature parameter corresponding to the detected temperature as the first parameter. 7. The first register is set, and a sum of a second default parameter and a second temperature parameter corresponding to the detected temperature is set as a second parameter in the second register. The PLL circuit described. The correction value memory has a temperature table corresponding to a plurality of use frequency bands,
8. The PLL circuit according to claim 7, wherein when a use frequency band is set from the outside, the control unit refers to a temperature table corresponding to the set use frequency band.

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