JP2007258334A - Semiconductor device and wire bonding optimization method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wire bonding optimization method and a semiconductor device wherein, when a displacement arises in packaging position of a chip to a package, short circuit is avoided between bonding wires. <P>SOLUTION: The wire bonding optimization method comprises a first process S1 of inputting into a wire bonding apparatus instance names, coordinates, and connection information of a plurality of bonding points, and pad coordinates of a semiconductor chip such that the plurality of the bonding points are set with respect to any pad on the side of the semiconductor chip in wire bonding of connecting the pad 2 of the semiconductor chip 1 and a bonding point BP on a package substrate; a second process S2 of detecting an amount of position displacement with respect to the package substrate of the semiconductor chip; a third process S3 of detecting an optimum bonding point from among the plurality of the bonding points, on the basis of the amount of the detected position displacement; and a fourth process S4 of transmitting the instance information of the optimum bonding point to the wire bonding apparatus. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is accommodated in a semiconductor package and packaged, and a wire bonding optimization method for the semiconductor chip.

  In recent years, resin-encapsulated LSI packages such as QFP (Quad Flat Package) and BGA (Ball Grid Array) have been developed, and the number of pads on a semiconductor chip and the lead frame / substrate bonding on the package side as the LSI becomes more multifunctional and faster. Due to the increase in the number of fingers, it has become difficult to ensure a large clearance between adjacent bonding wires.

  FIG. 26 shows a partial configuration example in which a semiconductor chip is mounted on a semiconductor package substrate and wire bonding is performed as a generally designed system-in-package (SiP) semiconductor device. In FIG. 26, 1 is a semiconductor chip, 2 is a pad of the semiconductor chip 1, 3 is a package substrate wiring, 4 is a bonding finger, and 5 is a bonding wire. As shown in FIG. 26, a designer generally designs a semiconductor package in an ideal state in which a semiconductor chip is mounted without any deviation from the package substrate.

  By the way, the mechanical accuracy of the die bonding apparatus for bonding the semiconductor chip to the package substrate varies in [x, y, θ], and the mounting position shift of the semiconductor chip with respect to the package substrate occurs. Even if the semiconductor chip is bonded to the package substrate in an ideal state that is not displaced at all, an increase in the number of terminals (pins) makes the adjacent bonding wires very close to each other. For this reason, the problem of misalignment of the semiconductor chip cannot be ignored.

  As described above, there is a problem that the problem of misalignment of the semiconductor chip due to a decrease in the design margin between the bonding wires becomes noticeable, and a short-circuit defect between the bonding wires occurs. This is a problem that may occur regardless of the type of package such as a package using a lead frame.

Conventionally, as a wiring design method having a degree of freedom, a configuration in which a relay point is provided to make a detour has been proposed (see, for example, Patent Document 1). In this case, at least one relay point for bonding wires is provided in the bed or semiconductor chip in the package, and the wire is relayed at the relay point for a place where there is a concern about contact between the bonding wires. is there. With this configuration, it is possible to bypass the bonding wire for a place where contact between the bonding wires is a concern.
JP 59-138353 A (2nd page, Fig. 1-2)

  In the conventional method, no consideration is given to the mounting misalignment of the semiconductor chip, and no margin for misalignment is taken. The problem of occurrence cannot be solved.

  The present invention solves the above-described conventional problems, and enables wire bonding to an optimum location that does not cause a short-circuit failure between bonding wires even when a semiconductor chip mounting position shift occurs, and improves yield. It aims to plan.

  In order to achieve the above object, the present invention is to design a package substrate pattern / lead frame pattern in which a plurality of bonding points can be set for one or more pads of a semiconductor chip in a package substrate / lead frame design. And the bonding point instance name, coordinates, connection information, and pad coordinates of the semiconductor chip are input to the wire bonding apparatus, the amount of mounting displacement of the semiconductor chip is detected, and the optimum bonding point is detected from the amount of displacement. Become.

The wire bonding optimization method according to the present invention is a wire bonding for connecting a pad of a semiconductor chip mounted on a package substrate and a bonding point of the package substrate.
In order to set a plurality of bonding points for any of the pads on the side of the semiconductor chip, the instance names, coordinates, connection information, and pad coordinates of the semiconductor chip are set in the wire bonding apparatus. A first step of input;
A second step of detecting a displacement amount of the semiconductor chip with respect to the package substrate;
A third step of detecting an optimal bonding point from among the plurality of bonding points set based on the detected displacement amount;
And a fourth step of transmitting the instance information of the optimum bonding point to the wire bonding apparatus.

  In this configuration, when the semiconductor chip is mounted on the semiconductor package, even if the mounting position of the semiconductor chip is deviated from the planned position, the positional deviation amount is detected, and a plurality of bonding points are set. Since the optimum bonding point is selected according to the detected positional deviation amount, it is possible to perform wire bonding to an appropriate location that does not cause a short-circuit between wires, thereby improving the production yield.

Further, the wire bonding optimization method according to the present invention is a wire bonding for connecting a pad of a semiconductor chip mounted on a die pad and a bonding point of an inner lead.
The instance names, coordinates, connection information, and pad coordinates of the semiconductor chip are input to the wire bonding apparatus so that a plurality of the bonding points are set for any pad of the semiconductor chip. A first step;
A second step of detecting a displacement amount of the semiconductor chip with respect to the die pad;
A third step of detecting an optimal bonding point from among the plurality of bonding points set based on the detected displacement amount;
And a fourth step of transmitting the instance information of the optimum bonding point to the wire bonding apparatus.

  In this configuration, when the semiconductor chip is mounted on the die pad, even if the mounting position of the semiconductor chip is deviated from the planned position, the optimum bonding point is selected according to the amount of misalignment. It becomes possible to perform wire bonding to an appropriate location that does not cause a short-circuit failure, thereby improving the production yield.

  In the above, in the first step, a priority number is further input, and in the third step, a wiring simulation is performed in order of the priority numbers for the plurality of bonding points set, and the simulation is performed. From the design rule check result, if the check result is not possible (NG), a simulation is performed at the next priority bonding point until the check result becomes acceptable (OK), and the check result becomes acceptable. There is a mode in which the bonding point is determined as the optimum bonding point.

  In this way, by performing the design rule check in the order of priority number, it is not necessary to perform the design rule check for all wires, and the number of times the design rule check is performed is reduced.

  Further, in the above, the third step includes the step of shifting the semiconductor chip with respect to the coordinates of the bonding point when the semiconductor chip is displaced in both the X direction and the Y direction or only in one direction with respect to the package substrate. There is an aspect of adding an amount.

  In this way, the design rule check need not be performed, and the processing speed can be increased.

  Further, in the above, the third step includes the step of shifting the semiconductor chip with respect to the coordinates of the bonding point when the semiconductor chip is displaced in both the X direction and the Y direction or only in one direction with respect to the package substrate. There is a mode of subtracting the amount.

  In this way, the design rule check need not be performed, and the processing speed can be increased.

  Further, in the above, the first step further inputs an allowable deviation value, and the third step determines the chip deviation when the deviation amount along the chip side direction of the semiconductor chip exceeds the deviation allowable value. The bonding point located at the lower end of the direction is determined as the bonding point corresponding to the pad at the lower end of the shift direction of the pad row along the semiconductor chip side, and the starting point of the bonding point verification, The bonding point of the pad adjacent to the end pad is tentatively determined as the adjacent bonding point of the verification starting point. If the check result is acceptable, the determination is made. If the check result is not possible, the bond point is further adjacent. The next bonding point is verified one by one until the check result is acceptable. By gradually shifted to Into, there is a mode that will determine the best bonding point for all wires.

  In this way, it is possible to flexibly optimize all the bonding points with respect to the positional deviation of the semiconductor chip in the X direction and the Y direction.

  In the above, the first step further inputs an allowable deviation value and a unit shift amount for verifying the bonding point, and the third step includes a shift amount along the chip side direction of the semiconductor chip. If the allowable value is exceeded, the bonding point located at the lower end of the chip displacement direction is determined as the bonding point corresponding to the pad at the lower end of the displacement direction of the pad row along the semiconductor chip side. In this case, the bonding point of the pad adjacent to the end pad is temporarily determined as a position shifted by the unit shift amount from the verification starting point, and this determination is made if the check result is acceptable. If the check result is not possible, the process shifts to a position shifted by the unit shift amount, and the check result becomes possible. In that will shift the bonding points verification positions shifted by shift amount of the unit, there is a mode that will determine the best bonding point for all wires.

  In this way, more flexible optimization is possible.

  In the above, the first step further inputs an allowable incident angle value, and the third step calculates the wire incident angle of both end pads on the semiconductor chip side after mounting the semiconductor chip. The incident angle on the smaller side is compared with the allowable incident angle, and if the incident angle is smaller than the allowable incident angle, the bonding point verification is performed until the incident angle is equal to or greater than the allowable incident angle. It moves to the next bonding point one by one in the direction, and determines the bonding point that is equal to or greater than the incident angle allowable value as the bonding point corresponding to the pad at the end, and the starting point of the bonding point verification, The bonding point corresponding to the adjacent pad of the end pad is provisionally determined as the adjacent bonding point of the verification starting point, If the check result is acceptable, the determination is made. If the check result is not possible, the process proceeds to the next bonding point, and the bonding point verification is performed one by one until the check result is acceptable. There is a mode in which the optimum bonding point of all wires is determined by shifting to step (b).

  In this way, even if the rotational deviation of the semiconductor chip occurs and the wire incident angle changes greatly, the overall wire incident angle can be improved.

  In the above, the first step further inputs an incident angle allowable value and a unit shift amount for verifying the bonding point, and the third step includes pads on both ends of the semiconductor chip side after mounting the semiconductor chip. The wire incident angle is calculated and compared with the incident angle allowable value for the smaller incident angle. When the incident angle is smaller than the incident angle allowable value, bonding point verification is performed until the incident angle is equal to or larger than the allowable incident angle. Toward the other end of the bonding point row, the bonding point is shifted to a position shifted by the unit shift amount of the bonding point verification, and the bonding point that is equal to or greater than the allowable incident angle is bonded to the bonding point of the end pad. And the bond point of the pad adjacent to the end pad is used as a starting point for verifying the bonding point. Tentatively determined as a point shifted by the unit shift amount from the verification starting point, and if the check result is acceptable, this determination is made, and if the check result is not possible, the bonding point verification unit is further shifted. The bonding point is transferred to the location shifted by the amount, and the verification bonding point is transferred to the location shifted by the unit shift amount of the bonding point verification until the check result is acceptable, and the optimum bonding point for all wires is determined. There is a mode of going.

  In this way, it is possible to optimize the bonding points more flexibly with respect to the rotational deviation of the semiconductor chip.

  In the semiconductor device according to the present invention, a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and some of the bonding fingers have their tips branched into a plurality. It is characterized by having.

  The semiconductor device according to the present invention includes a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate bonded via bonding wires, and a tip of some of the bonding fingers has a chip side. It is characterized by widening along the direction.

  In the semiconductor device according to the present invention, a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and some of the bonding fingers are perpendicular to the chip side direction. A plurality of bonding fingers are separated in the direction.

  The semiconductor device according to the present invention includes a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate bonded via bonding wires, and a tip of some of the bonding fingers has a chip side. It is characterized by being widened along a direction perpendicular to the direction.

  The semiconductor device according to the present invention includes a plurality of pads in a semiconductor chip and a plurality of bonding fingers in a package substrate bonded through bonding wires, and a series of rows as viewed from above the package substrate. A plurality of the bonding fingers are arranged in a cross arrangement.

  In the semiconductor device according to the present invention, a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and the number of pads on the package substrate is reduced. It is characterized in that the bonding wires are stretched through bonding relay lands provided at least one or more.

  The semiconductor device according to the present invention includes a plurality of pads in a semiconductor chip and a plurality of bonding fingers in a package substrate bonded through bonding wires, and a long bonding provided on the package substrate. The bonding wire is passed through a relay land, and after being passed, it is divided into a state in which bonding points are separated.

  In the semiconductor device according to the present invention, a plurality of pads in a semiconductor chip and a plurality of inner leads in a lead frame package are bonded via bonding wires, and the inner leads located at least at the end are It is characterized by being branched or deformed.

  The semiconductor device according to the present invention includes a plurality of pads in a semiconductor chip and a plurality of bonding fingers or inner leads in the package substrate bonded via bonding wires, and is positioned at an end portion in the chip side direction. The bonding finger or the inner lead is branched or deformed into a plurality.

  In the semiconductor device according to the present invention, a plurality of pads on a semiconductor chip and a plurality of bonding fingers or inner leads on a package substrate are bonded via bonding wires, and are adjacent to each other in plan view. The bonding finger or the inner lead corresponding to the bonding wire in a state where a cross point exists is branched or deformed into a plurality.

  In the semiconductor device according to the present invention, a plurality of pads on a semiconductor chip and a plurality of bonding fingers or inner leads on a package substrate are bonded via bonding wires, and are adjacent to each other and have different wire lengths. The bonding finger or the inner lead corresponding to the bonding wire is branched or deformed into a plurality.

  A semiconductor device according to the present invention is characterized in that it has a system-in-package structure in which a plurality of the semiconductor chips are stacked and mounted.

  According to the present invention, after the semiconductor chip is mounted on the semiconductor package, even if the mounting position of the semiconductor chip is deviated from the planned position, the wire bonding is performed to an appropriate position that does not cause a short-circuit between wires. It is possible to improve the production yield.

  DESCRIPTION OF EMBODIMENTS Embodiments of a wire bonding optimization method in a semiconductor device according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a flowchart showing a processing procedure of a wire bonding optimization method according to Embodiment 1 of the present invention.

  In FIG. 1, S1 is a step of inputting instance names, coordinates, connection information, and pad coordinates of a semiconductor chip to a wire bonding apparatus for any pad on the side of the semiconductor chip, and S2 is a substrate. A step of detecting a deviation of the semiconductor chip with respect to the package substrate in the package, S3 is a step of detecting an optimum bonding point from a plurality of bonding points set based on the detected positional deviation amount, and S4 is an instance information of the optimum bonding point. This is a process of transmitting to the wire bonding apparatus.

  First, in step S1, the wire bonding apparatus uses the instance names, coordinates, connection information and semiconductor chip pad coordinates of a plurality of bonding points so that a plurality of bonding points are set for any pad on the semiconductor pad side. To enter. That is, basic wire bonding information that enables selection of an optimum bonding point with respect to the chip position deviation is input.

  Next, in step S2, the semiconductor chip mounting position deviation amount is detected.

  Next, in step S3, an optimum bonding point is detected from a plurality of bonding points set based on the detected positional deviation amount. That is, a bonding point to a location where no short circuit between wires occurs is detected.

  Next, in step S4, the instance information of the optimum bonding point is transmitted to the wire bonding apparatus.

  As described above, it is possible to perform wire bonding without causing a short circuit defect.

(Embodiment 2)
FIG. 2 is a flowchart showing a processing procedure of the wire bonding optimization method according to the second embodiment of the present invention. This is a wire bonding optimization method for a mounting position shift of a semiconductor chip mounted on a lead frame package. In FIG. 2, steps having the same reference numerals as those in FIG. 1 of the first embodiment indicate processes having the same contents. The process unique to this embodiment is step S2a, in which the amount of deviation of the semiconductor chip with respect to the die pad in the lead frame package is detected. Since other processes are the same as those in the first embodiment, the description thereof is omitted. This embodiment also has the same effect as that of the first embodiment.

(Embodiment 3)
FIG. 3 is a flowchart showing a processing procedure of the wire bonding optimization method according to the third embodiment of the present invention.

  In step S1a, priority numbers of a plurality of bonding points are input to the wire bonding apparatus. The instance name, coordinates, connection information, and pad coordinates of the semiconductor chip are also input.

  In step S3a for detecting the optimum bonding point, a design rule check (DRC: Design Rule Check) around the bonding points is performed in order of priority number, and the result of the check by the design rule check at the first priority bonding point. If it becomes impossible, a design rule check is performed at the next priority point, the bonding point, and if the check result is acceptable, optimization based on the detected positional deviation is made with that bonding point as the optimal bonding point. , And so on until the check result is acceptable. Since other processes are the same as those in the first embodiment, the description thereof is omitted.

  According to the present embodiment, optimization that can reliably prevent short-circuit defects can be performed, and the design rule check need not be performed on all wires by performing in order of priority number. The number of implementations can be reduced.

  A check result by a design rule check in consideration of the wire flow may be used.

(Embodiment 4)
FIG. 4 is a flowchart showing the procedure of the wire bonding optimization method according to the fourth embodiment of the present invention. In FIG. 4, steps with the same reference numerals as those in FIG. 1 of the first embodiment indicate processes having the same contents.

  In the step S3b of detecting the optimum bonding point, all or some of the bonding points to be set are detected when the semiconductor chip is displaced in both the X direction and the Y direction with respect to the package substrate or only in one direction. The bonding point is optimized by adding a deviation amount to the coordinates of the bonding point. Since other processes are the same as those in the first embodiment, the description thereof is omitted.

  According to the present embodiment, it is not necessary to perform the design rule check, and the processing speed can be increased.

(Embodiment 5)
FIG. 5 is a flowchart showing the procedure of the wire bonding optimization method according to the fifth embodiment of the present invention. In FIG. 5, steps with the same reference numerals as those in FIG. 1 of the first embodiment indicate processes having the same contents.

  In the step S3c of detecting the optimum bonding point, all or some of the bonding points to be set are detected when the semiconductor chip is displaced in both the X direction and the Y direction with respect to the package substrate or only in one direction. The bonding point is optimized by subtracting the amount of deviation from the coordinates of the bonding point. Other processes are the same as those in the fourth embodiment, and thus the description thereof is omitted.

  According to the present embodiment, it is possible to perform optimization in the opposite direction to that of the fourth embodiment, and there is an effect of speeding up the processing because it can be performed without performing the design rule check.

(Embodiment 6)
FIG. 6 is a flowchart showing a processing procedure of the wire bonding optimization method according to the sixth embodiment of the present invention. FIG. 7 is a plan view schematically showing processing of the wire bonding optimization method in the sixth embodiment.

  In FIG. 7, 1 is a semiconductor chip, 2 is a pad of the semiconductor chip 1, 5 is a bonding wire, BP is a bonding point, X is a bonding point verification direction, and X 'is a displacement direction of the semiconductor chip 1 with respect to the package substrate.

  In step S1b, the allowable deviation value Xth is input to the wire bonding apparatus together with the instance names, coordinates, connection information, and pad coordinates of the semiconductor chip of the plurality of bonding points BP.

  In the step S3d of detecting the optimum bonding point, when the semiconductor chip 1 is displaced beyond the deviation allowable value Xth along the chip side direction, the lower side of the chip deviation direction X ′ among the plurality of available bonding point BP groups. The bonding point BP located at the end of the semiconductor chip 1 is determined as the bonding point BP corresponding to the pad 2 at the lower end of the shift direction X ′ in the two rows of pads along the chip side of the semiconductor chip 1, and the bonding point is verified. The starting point of Then, the bonding point BP of the adjacent pad 2 of the end pad 2 is provisionally determined to be the adjacent bonding point BP of the verification starting point, and if the check result by the design rule check around the wire is acceptable, this determination is made. If the check result is not possible, the process proceeds to the next bonding point BP, and the bonding point verification is performed one by one along the bonding point verification direction X until the check result by the design rule check becomes acceptable. To move on. In this way, the bonding point BP is optimized for each of the semiconductor pads 2.

  It should be noted that the optimization process is not performed when the deviation amount of the semiconductor chip 1 does not exceed the deviation tolerance value Xth. Since other processes are the same as those in the first embodiment, the description thereof is omitted.

  A check result by a design rule check in consideration of the wire flow may be used.

  According to the present embodiment, it is possible to flexibly optimize all the bonding points BP with respect to the displacement of the semiconductor chip 1. Furthermore, by making the starting point of the bonding point verification at the lower end of the chip displacement direction X ′, the wire incident angle of the other end side pad 2 can be set to the maximum selectable angle. It is possible to avoid short circuit.

(Embodiment 7)
FIG. 8 is a flowchart showing a processing procedure of the wire bonding optimization method according to the seventh embodiment of the present invention. FIG. 9 is a plan view schematically showing processing of the wire bonding optimization method in the seventh embodiment. In FIG. 9, ΔX is a unit shift amount of the bonding point verification. The other parts are the same as those in FIG. 7, and the same parts are denoted by the same reference numerals.

  In step S1c, the allowable deviation value Xth and the unit shift amount ΔX for verifying the bonding point are input to the wire bonding apparatus together with the instance names, coordinates, connection information, and the coordinates of the pads 2 of the semiconductor chip.

  In the step S3e of detecting the optimum bonding point, if the semiconductor chip 1 is displaced beyond the allowable deviation Xth with respect to the chip side, it is shifted from the end of the bonding finger by the unit shift amount ΔX toward the inside of the bonding finger. When the detection point is transferred from the starting point to the next, the bonding point BP of the adjacent pad 2 is transferred based on the check result of the design rule check each time the unit shifts by ΔX from the verification starting point. Detection is performed.

  It should be noted that the optimization process is not performed when the deviation amount of the semiconductor chip 1 does not exceed the deviation tolerance value Xth. The other processes are the same as those in the sixth embodiment, and a description thereof will be omitted.

  A check result by a design rule check in consideration of the wire flow may be used.

  The difference from FIG. 7 is that, in order to optimize the bonding point BP after the determination of the bonding point verification start point, the verification unit is shifted when the detection point is transferred from the verification start point to the adjacent bonding point BP. This is to shift in the bonding point verification direction X by the amount ΔX.

  According to the present embodiment, more flexible optimization is possible.

(Embodiment 8)
FIG. 10 is a flowchart showing the procedure of the wire bonding optimization method according to the eighth embodiment of the present invention. FIG. 11 is a plan view schematically showing processing of the wire bonding optimization method in the eighth embodiment. θ is an incident angle of the bonding wire 5. The other parts are the same as those in FIG. 7, and the same parts are denoted by the same reference numerals.

  In step S1d, the incident angle allowable value θth is input to the wire bonding apparatus instead of the deviation allowable value Xth. The instance names, coordinates, connection information, and coordinates of the pads 2 of the semiconductor chip are also input.

  In the step S3f of detecting the optimum bonding point, when the wire incident angle θ to the semiconductor chip 1 in either of the two end pads 2 of the two rows of pads on the chip side of the semiconductor chip 1 is smaller than the incident angle allowable value θth, It is detected whether the wire incident angle θ is small, and the wires having the small incident angle θ are moved one by one to the adjacent bonding point BP one by one in the direction of the other end of the bonding point BP row until the incident angle allowable value θth is exceeded. A portion where the incident angle is equal to or larger than the allowable angle θth is determined as a bonding point BP corresponding to the pad 2 at the end and is set as a starting point. Similarly, the bonding point BP of the adjacent pad 2 is optimized along the bonding point verification direction X from the starting point, and the bonding point BP is similarly optimized one by one using the check result by the design rule check around the wire.

  Note that the optimization process is not performed when the wire incident angle θ of the pads 2 at both ends of the pads 2 on the chip side of the semiconductor chip 1 is larger than the allowable incident angle θth. Other processes are the same as those in the sixth embodiment (FIG. 6), and thus the description thereof is omitted.

  A check result by a design rule check in consideration of the wire flow may be used.

  According to the present embodiment, it is possible to flexibly optimize all the bonding points BP with respect to the rotational deviation of the semiconductor chip 1.

  The difference from FIG. 7 is that, based on the check result by the design rule check along the bonding point verification direction X after detecting the starting point such that the incident angle θ of the end wire as the starting point to the semiconductor chip 1 is not too small. By optimizing the bonding points BP one by one, even if the rotational deviation of the semiconductor chip 1 occurs and the wire incident angle θ changes greatly, the overall wire incident angle θ can be improved. .

(Embodiment 9)
FIG. 12 is a flowchart showing the procedure of the wire bonding optimization method according to the ninth embodiment of the present invention. FIG. 13 is a plan view schematically showing processing of the wire bonding optimization method in the ninth embodiment.

  In step S1, the allowable incident angle θth and the unit shift amount ΔX for verifying the bonding point are input to the wire bonding apparatus. The instance names, coordinates, connection information, and coordinates of the pads 2 of the semiconductor chip are also input.

  In the step S3 of detecting the optimum bonding point, when the wire incident angle θ to the semiconductor chip 1 of either the pad 2 or both-end pads 2 on the chip side of the semiconductor chip 1 is smaller than the incident angle allowable value θth, the semiconductor chip Detecting which end pad 2 on one chip side has a smaller wire incident angle θ and bonding a wire having a smaller incident angle θ toward the other end of the bonding point BP row until the incident angle is equal to or greater than the allowable incident angle θth. The starting point is determined while shifting the bonding point BP by the unit verification amount ΔX for point verification. Then, while the bonding point BP is shifted by the unit shift amount ΔX from the starting point of the bonding point verification, the adjacent pad 2 is similarly optimized based on the check result by the design rule check.

  Note that the optimization process is not performed when the wire incident angle θ of the pads 2 at both ends of the pads 2 on the chip side of the semiconductor chip 1 is larger than the allowable incident angle θth. Other processes are the same as those in the eighth embodiment (FIG. 10), and thus the description thereof is omitted.

  A check result by a design rule check in consideration of the wire flow may be used.

  According to the present embodiment, more flexible optimization of all the bonding points BP can be automatically performed with respect to the rotational deviation of the semiconductor chip 1.

  The difference from FIG. 11 is that when detecting toward the other end of the bonding point BP row in order to determine the starting point, optimization using the check result by the design rule check while shifting the unit shift amount ΔX of the bonding point verification By automatically performing the above, even if the rotation deviation of the semiconductor chip 1 occurs and the wire incident angle θ changes greatly, the overall wire incident angle θ can be automatically improved.

(Embodiment 10)
FIG. 14 is a plan view schematically showing a package substrate pattern in the tenth embodiment of the present invention.

  In FIG. 14, 1 is a semiconductor chip, 2 is a pad of the semiconductor chip 1, 3 is a package substrate wiring, and 4 is a bonding finger that forms a bonding point BP at the tip of the package substrate wiring 3.

  A plurality of pads 2 for wire bonding are formed side by side on the chip side of the semiconductor chip 1. A plurality of package substrate wirings 3 from the package substrate are juxtaposed along the chip side direction outside the semiconductor chip 1. In the package substrate wiring 3e located at the end in the chip side direction in the package substrate wiring 3 group, the bonding finger is branched into two bonding fingers 4A and 4B. When passing the bonding wire 5 between the pad 2e positioned at the end in the chip side direction and one of the two bonding fingers 4A and 4B of the package substrate wiring 3e positioned at the end, The most suitable bonding finger is selected in order to avoid short circuit failure, and the bonding wire 5 is passed between the selected bonding finger.

  The configuration in which the bonding fingers are branched into a plurality may be applied not only to the end portion in the chip side direction but also to the package substrate wiring 3 at an arbitrary location.

  According to the present embodiment, the bonding point BP is selected from the plurality of bonding fingers branched at the tip of the package substrate wiring 3 with respect to the positional deviation of the semiconductor chip 1 with respect to the package substrate. Short circuit failure can be avoided.

(Embodiment 11)
FIG. 15 is a plan view schematically showing a package substrate pattern according to the eleventh embodiment of the present invention.

  In FIG. 15, the same reference numerals as in FIG. 14 denote the same components.

  In the package substrate wiring 3e located at the end in the chip side direction among the group of package substrate wirings 3 arranged in parallel along the chip side direction, the bonding finger 4C is widened in the chip side direction. When the bonding wire 5 is passed between the pad 2e located at the end in the chip side direction and the wide bonding finger 4C of the package substrate wiring 3e located at the end, the area range of the wide bonding finger 4C is reduced. Among them, a position that is optimal for avoiding a short-circuit failure between the bonding wires is selected, and the bonding wire 5 is passed between the selected positions.

  The configuration in which the bonding fingers are wide may be applied not only to the end portion in the chip side direction but also to the package substrate wiring 3 at an arbitrary location.

  According to the present embodiment, the bonding point BP is selected within the area of the wide bonding finger 4C widened at the tip of the package substrate wiring 3 with respect to the positional deviation of the semiconductor chip 1 with respect to the package substrate. Short-circuit defects between wires can be avoided.

(Embodiment 12)
FIG. 16 is a plan view schematically showing a package substrate pattern in the twelfth embodiment of the present invention.

  In FIG. 16, the same reference numerals as those in FIG. 14 denote the same components. Y is a direction perpendicular to the chip side direction.

  In some package substrate wirings 3e located at both ends in the chip side direction among the group of package substrate wirings 3 arranged in parallel along the chip side direction, the bonding fingers are separated by 2 in the direction Y perpendicular to the chip side direction. Two bonding fingers 4 and 4D are provided. That is, there are two rows of bonding fingers.

  The number of bonding fingers is not limited to two, but may be three or more. Further, the bonding fingers need not be limited to both ends in the chip side direction, and may be arranged at any position.

  According to the present embodiment, a bonding point BP is selected from a plurality of bonding fingers separated in the vertical direction Y with respect to the positional deviation of the semiconductor chip 1 in the vertical direction Y with respect to the chip side direction with respect to the package substrate. Therefore, a short circuit failure between bonding wires can be avoided.

(Embodiment 13)
FIG. 17 is a plan view schematically showing a package substrate pattern in the thirteenth embodiment of the present invention.

  In FIG. 17, the same reference numerals as in FIG. 16 indicate the same components.

  Among several package substrate wirings 3e located at both ends in the chip side direction among the group of package substrate wirings 3 arranged in parallel along the chip side direction, the bonding fingers 4E are elongated in the direction Y perpendicular to the chip side direction. Is formed. When passing the bonding wire 5 between the pad 2e on the end side in the chip side direction and the elongated bonding finger 4E of the package substrate wiring 3e on the end side, the bonding wire is out of the length range of the elongated bonding finger 4E. A position that is optimal for avoiding a short-circuit failure is selected, and the bonding wire 5 is passed between the selected position.

  Note that the configuration in which the bonding fingers are formed elongated is not necessarily limited to both ends in the chip side direction, and may be at any position.

  According to the present embodiment, the bonding point BP within the length range of the elongated bonding finger 4E at the tip of the package substrate wiring 3 with respect to the positional deviation of the semiconductor chip 1 in the direction Y perpendicular to the chip side direction with respect to the package substrate. Therefore, it is possible to avoid a short-circuit failure between bonding wires, and there is no need to increase the number of bonding fingers.

(Embodiment 14)
FIG. 18 is a plan view schematically showing a package substrate pattern in the fourteenth embodiment of the present invention.

  In FIG. 18, the same reference numerals as in FIG. 16 denote the same components.

  In the group of package substrate wirings 3 arranged in parallel along the chip side direction, two bonding fingers 4F and 4G are formed in the length direction of almost all package substrate wirings 3 except for some central package substrate wirings 3. Separated. The distance between the two bonding fingers 4F and 4G increases as it goes outward in the chip side direction. As a result, the two bonding fingers 4F and 4G are arranged so as to form an “X” -shaped cross arrangement when viewed from above the package substrate. One row of bonding fingers 4F is inclined downward to the right with respect to the chip side direction, and the other row of bonding fingers 4G is inclined downward with respect to the chip side direction.

  In the state shown in the drawing, the semiconductor chip 1 has a rotational deviation in the clockwise direction and is inclined downwardly to the right. Correspondingly, of the two bonding fingers 4F and 4G, the bonding finger 4F inclined to the right is selected, and the pad 2 and the bonding finger 4F of the semiconductor chip 1 are bonded by the bonding wire 5. It is connected.

  If the semiconductor chip 1 is rotated counterclockwise and tilted to the left, the bonding finger 4G that is tilted to the left is selected.

  The number of bonding fingers at the center in the chip side direction may be two.

  According to the present embodiment, since the rotation angle of the semiconductor chip 1 with respect to the package substrate is selected from the two bonding fingers 4F and 4G that are cross-arranged with different inclination angles, a short circuit failure between the bonding wires Can be avoided.

(Embodiment 15)
FIG. 19 is a plan view schematically showing a package substrate pattern in the fifteenth embodiment of the present invention.

  A plurality of pads 2 for wire bonding are formed side by side on the chip side of the semiconductor chip 1. 2A represents a pad row. A plurality of package substrate wirings 3 from the package substrate are juxtaposed along the chip side direction outside the semiconductor chip 1, and each tip portion is a bonding finger 4, and the package substrate wiring 3 group, the semiconductor chip 1, A plurality of bonding relay lands 4H are arranged along the chip side direction. One or more bonding relay lands 4H are arranged more than the number of pads 2 in the pad row 2A of the semiconductor chip 1 corresponding to wiring.

  When the pad 2 of the semiconductor chip 1 and the package substrate wiring 3 are electrically connected, the bonding wire 5a is passed between the pad 2 and the bonding relay land 4H, and the bonding relay land 4H and the package substrate wiring 3 are further connected. A bonding wire 5 b is passed between the bonding fingers 4. When the bonding wire 5a is transferred between the pad 2 and the bonding relay land 4H, the bonding wire 5a is transferred after selecting the bonding relay land 4H which is optimal for avoiding a short-circuit failure between the bonding wires.

  According to the present embodiment, since the bonding relay land 4H located in the middle is used for the positional deviation of the semiconductor chip 1 in the chip side direction, the selection of the bonding point in all the pads 2 becomes flexible. Short circuit defects between bonding wires can be avoided.

(Embodiment 16)
FIG. 20 is a plan view schematically showing a package substrate pattern in the sixteenth embodiment of the present invention.

  20, the same reference numerals as those in FIG. 19 denote the same components.

  Between the package substrate wiring 3 group and the semiconductor chip 1, a single bonding relay land 4 </ b> I that is long in the lateral direction is arranged along the chip side direction. The long bonding relay land 4I is divided after the bonding point BP for relay is determined.

  When the pad 2 of the semiconductor chip 1 and the package substrate wiring 3 are electrically connected, a bonding wire 5a is passed between the pad 2 and the long bonding relay land 4I, and a longer bonding relay land is formed. A bonding wire 5 b is passed between 4 I and the bonding finger 4 of the package substrate wiring 3. When the bonding wire 5a is passed between the pad 2 and the long bonding relay land 4I, the optimum position for avoiding a short circuit between the bonding wires is selected on the bonding relay land 4I. Pass the bonding wire 5a. After passing the bonding wire 5b, the long bonding relay land 4I is divided so that a plurality of bonding points BP in the long bonding relay land 4I are separated from each other. This division includes laser cutting and etching. The direction of division may be right angle, diagonal or curved.

  A plurality of long bonding relay lands 4I may be arranged. Moreover, the shape does not necessarily need to be a rectangle.

  According to the present embodiment, since a long bonding relay land 4I is used for position displacement of the semiconductor chip 1 in the chip side direction and divided after wire bonding, selection of bonding points in all the pads 2 is possible. Becomes flexible, and a short circuit failure between bonding wires can be avoided. In particular, since the bonding point BP can be determined at any point within the continuous range of the long bonding relay land 4I, the bonding point BP can be handled with a narrow pitch.

(Embodiment 17)
FIG. 21 is a plan view schematically showing a lead frame pattern in the seventeenth embodiment of the present invention.

  A plurality of inner leads 6 from the lead frame are juxtaposed along the chip side direction outside the semiconductor chip 1. The form of the inner lead 6 e located at the end in the chip side direction in the inner lead 6 group is different from the other inner leads 6.

  In the case of FIG. 21A, the inner lead 6e at the end has a bifurcated tip. Then, when passing the bonding wire 5 between the pad 2e located at the end in the chip side direction and one of the two branch portions of the inner lead 6e at the end, a short circuit between the bonding wires is avoided. Then, the most suitable branching portion is selected, and the bonding wire 5 is passed between the selected branching portion.

  In the case of FIG. 21B, the width of the inner lead 6e at the end is increased. In the case of FIG. 21 (c), the inner lead 6e at the end has an L shape in which only the tip is widened outward. In the case of FIG. 21D, the inner lead 6e at the end has an L shape in which only the tip is conversely widened inward. In any case, when passing the bonding wire 5 between the pad 2e located at the end in the chip side direction and the inner lead 6e at the end, the inner is optimal for avoiding a short-circuit defect between the bonding wires. A position on the lead 6 is selected, and the bonding wire 5 is passed to the selected position.

  The inner lead 6 to be deformed may be applied not only to the end portion in the chip side direction but also to the inner lead 6 at an arbitrary location.

  According to the present embodiment, since the bonding point BP is selected in the deformed inner lead 6 with respect to the positional deviation of the semiconductor chip 1 with respect to the lead frame, it is possible to avoid a short-circuit failure between bonding wires.

(Embodiment 18)
22A is a plan view schematically showing a pattern in the case of a substrate package in Embodiment 18 of the present invention, and FIG. 22B is a plan view schematically showing a pattern in the case of a lead frame package. . In the present embodiment, when there is a possibility of causing a short-circuit failure between bonding wires as a result of the positional deviation of the semiconductor chip 1, the bonding finger 4 is formed at the end portion in the chip side direction in order to optimize the bonding point. The inner lead 6 is deformed.

  That is, the bonding fingers 4e at the end portions in the chip side direction are formed wide. Further, the inner lead 6e at the end portion in the chip side direction is formed wide. A bonding wire 5A indicated by a broken line represents a wire position before optimization, and a bonding wire 5B indicated by a solid line represents a wire position after optimization.

  Note that this applies not only to deformation but also to the case of branching at the tip. Further, the position of the bonding wire 5B may be changed from the bonding wire 5A to the ring power supply wiring 7 as well.

  According to the present embodiment, it is possible to avoid a short-circuit failure between bonding wires at the end portion in the chip side direction.

(Embodiment 19)
FIG. 23A is a plan view schematically showing a pattern in the case of a substrate package according to Embodiment 19 of the present invention, and FIG. 23B is a plan view schematically showing a pattern in the case of a lead frame package. . In the present embodiment, in order to optimize the bonding point when there is a possibility of causing a short-circuit failure between bonding wires as a result of crossing two adjacent bonding wires 5 and 5A in plan view, the bonding finger 4 is optimized. The inner lead 6 is deformed or branched.

  The bonding wire 5 and the bonding wire 5A before optimization cross in plan view. The bonding wires 5 and 5A are lifted from the position of the pad 2 and further lowered after reaching the apex to reach the bonding points BP1 and BP2. In the figure, the bonding wires 5 and 5A appear to be in cross contact with each other in a plan view, but in reality, both the bonding wires 5 and 5A are curved and are three-dimensionally crossing and are not in contact with each other.

  Since the bonding point BP1 where the bonding wire 5 lands and the bonding point BP2 where the bonding wire 5A lands are too close to each other, there is a possibility of causing a short circuit between the bonding wires. Therefore, the bonding finger 4 is widened. The tip of the inner lead 6 is branched. The bonding wire 5A is switched to the bonding wire 5B. The starting point of the bonding wire 5B is the same pad 2 as that of the bonding wire 5A, but the landing bonding point BP3 is farther from the bonding point BP1 than the bonding point BP2. As a result, short-circuit defects between bonding wires can be avoided.

(Embodiment 20)
FIG. 24 is a plan view schematically showing a pattern in the case of the substrate package in the twentieth embodiment of the present invention. In the present embodiment, the pads 2 in the semiconductor chip 1 are arranged in two rows in a staggered pattern, and accordingly, when the package substrate wiring 3 is arranged in two rows of different potentials, When the bonding wires 5 and 5A have different wire lengths and may cause a short-circuit failure between bonding wires, the bonding fingers 4 and the inner leads 6 are branched or deformed in order to optimize bonding points. It is.

  The bonding wire 5 is passed between the outer (upper) one of the two rows of pads 2 and the inner one of the two rows of bonding fingers 4. The bonding wire 5 is relatively short. The bonding wire 5A before optimization is passed between the inner (lower) one of the two rows of pads 2 and the outer one of the two rows of bonding fingers 4. The bonding wire 5A is relatively long. The bonding wires 5 and 5A are lifted from the position of the pad 2 and further lowered after reaching the apex to reach the bonding fingers 4a and 4b. In the figure, the bonding wires 5 and 5A appear to be in cross contact with each other in a plan view, but in reality, both the bonding wires 5 and 5A are curved and are three-dimensionally crossing and are not in contact with each other.

  Since the bonding finger 4a on which the bonding wire 5 lands and the bonding finger 4b on which the bonding wire 5A lands are too close to each other, there is a possibility of causing a short circuit between the bonding wires. Therefore, the bonding finger 4c is branched from the bonding finger 4b. The bonding wire 5A is switched to the bonding wire 5B. The starting point of the bonding wire 5B is the same pad 2 as the starting point of the bonding wire 5A, but the landing bonding finger 4c is farther from the bonding finger 4a than the bonding finger 4b. As a result, short-circuit defects between bonding wires can be avoided.

  This applies not only to branching but also to deformation.

(Embodiment 21)
FIG. 25A is a plan view schematically showing a package substrate pattern according to the twenty-first embodiment of the present invention. FIG. 25B is a cross-sectional view of the substrate package according to the twenty-first embodiment. In the figure, 8 is a sealing resin, 9 is a package terminal, and 10 is a package substrate. The above-described tenth to twentieth embodiments can be implemented even with a system in package (SiP) structure in which a plurality of semiconductor chips 1 are stacked. The same applies to the lead frame package.

  As described above, by using the bonding point optimizing method of the present invention and designing a semiconductor device such as a bonding finger pattern and an inner lead pattern capable of realizing them, a semiconductor chip mounting position with respect to the package Even when a shift occurs, it is possible to avoid a short circuit between wires. For this reason, it has a great effect on yield improvement and reliability improvement by preventing defects.

The flowchart which shows the procedure of the process of the wire bonding optimization method in Embodiment 1 of this invention The flowchart which shows the procedure of the process of the wire bonding optimization method in Embodiment 2 of this invention The flowchart which shows the process sequence of the wire bonding optimization method in Embodiment 3 of this invention. The flowchart which shows the procedure of the process of the wire bonding optimization method in Embodiment 4 of this invention The flowchart which shows the process sequence of the wire bonding optimization method in Embodiment 5 of this invention. The flowchart which shows the process sequence of the wire bonding optimization method in Embodiment 6 of this invention. The top view which shows typically the process of the wire bonding optimization method in Embodiment 6 of this invention The flowchart which shows the procedure of the process of the wire bonding optimization method in Embodiment 7 of this invention The top view which shows typically the process of the wire bonding optimization method in Embodiment 7 of this invention The flowchart which shows the procedure of the process of the wire bonding optimization method in Embodiment 8 of this invention. The top view which shows typically the process of the wire bonding optimization method in Embodiment 8 of this invention The flowchart which shows the process sequence of the wire bonding optimization method in Embodiment 9 of this invention. The top view which shows typically the process of the wire bonding optimization method in Embodiment 9 of this invention The top view which shows typically the package substrate pattern in Embodiment 10 of this invention The top view which shows typically the package substrate pattern in Embodiment 11 of this invention A plan view schematically showing a package substrate pattern in an embodiment 12 of the invention A plan view schematically showing a package substrate pattern in a thirteenth embodiment of the present invention. The top view which shows typically the package substrate pattern in Embodiment 14 of this invention The top view which shows typically the package substrate pattern in Embodiment 15 of this invention The top view which shows typically the package substrate pattern in Embodiment 16 of this invention The top view which shows typically the package substrate pattern in Embodiment 17 of this invention The top view which shows typically the pattern of the board | substrate package and lead frame package in Embodiment 18 of this invention The top view which shows typically the pattern of the board | substrate package and lead frame package in Embodiment 19 of this invention Plan view schematically showing a substrate package pattern according to the twentieth embodiment of the present invention. FIG. 7 is a plan view schematically showing a package substrate pattern and a sectional view of the substrate package in the twenty-first embodiment of the present invention. The figure which shows the example of ideal semiconductor package design which does not consider the conventional semiconductor chip position shift

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Semiconductor chip pad 2A Semiconductor chip pad row 3 Package substrate wiring 4 Bonding finger 4A-4G Bonding finger 4H-4I Bonding land 5 Bonding wire 5A Bonding wire before optimization 5B Bonding wire after optimization 6 Inner lead 7 Ring power supply wiring 8 Package sealing resin 9 Package terminal 10 Package substrate X Bonding point verification direction X ′ Semiconductor chip displacement direction ΔX Bond point unit displacement amount θ Wire incident angle BP Bonding point S1 Various information on wiring device S2 Step of detecting semiconductor chip position shift amount relative to package S3 Step of detecting optimum bonding point S4 Optimal bond The step of transmitting the instance information for grayed point wire bonding apparatus

Claims (21)

In wire bonding for connecting a pad of a semiconductor chip mounted on a package substrate and a bonding point of the package substrate,
In order to set a plurality of bonding points for any of the pads on the side of the semiconductor chip, the instance names, coordinates, connection information, and pad coordinates of the semiconductor chip are set in the wire bonding apparatus. A first step of input;
A second step of detecting a displacement amount of the semiconductor chip with respect to the package substrate;
A third step of detecting an optimal bonding point from among the plurality of bonding points set based on the detected displacement amount;
And a fourth step of transmitting the instance information of the optimum bonding point to the wire bonding apparatus. In wire bonding that connects the pad of the semiconductor chip mounted on the die pad and the bonding point of the inner lead,
The instance names, coordinates, connection information, and pad coordinates of the semiconductor chip are input to the wire bonding apparatus so that a plurality of the bonding points are set for any pad of the semiconductor chip. A first step;
A second step of detecting a displacement amount of the semiconductor chip with respect to the die pad;
A third step of detecting an optimal bonding point from among the plurality of bonding points set based on the detected displacement amount;
And a fourth step of transmitting the instance information of the optimum bonding point to the wire bonding apparatus. The first step further inputs a priority number,
In the third step, a wiring simulation is performed in the order of priority numbers for the plurality of bonding points set, and if the check result is impossible from the design rule check result by the simulation, the check result is The wire bonding optimization method according to claim 1, wherein a simulation is performed at a bonding point of the next priority until it becomes possible, and a bonding point where the check result is acceptable is determined as an optimum bonding point.   The third step adds the shift amount to the coordinates of the bonding point when the semiconductor chip is shifted in the X direction and / or the Y direction with respect to the package substrate. The wire bonding optimization method according to claim 1 or 2.   In the third step, when the semiconductor chip is displaced in both the X direction and the Y direction or only in one direction with respect to the package substrate, the deviation amount is subtracted from the coordinates of the bonding point. The wire bonding optimization method according to claim 1 or claim 2. The first step further inputs a deviation tolerance value,
In the third step, when the amount of deviation along the chip side direction of the semiconductor chip exceeds the deviation tolerance value, a bonding point located at the lower end of the chip deviation direction is along the semiconductor chip side. The bonding point corresponding to the pad at the lower end of the shift direction of the pad row is determined as a starting point for bonding point verification, and the bonding point of the pad adjacent to the end pad is used as the adjacent bonding at the starting point of verification. If the check result is acceptable, this determination is made. If the check result is not possible, the process proceeds to the next bonding point, and the bonding point verification is performed until the check result is acceptable. By moving to the next bonding point one by one, the optimal bonding point for all wires Wire bonding optimization method according to claim 1 to continue to constant. In the first step, an input of an allowable shift value and a unit shift amount for bonding point verification is further performed.
In the third step, when the amount of deviation along the chip side direction of the semiconductor chip exceeds the deviation tolerance value, a bonding point located at the lower end of the chip deviation direction is along the semiconductor chip side. The bonding point is determined as a bonding point corresponding to the pad at the lower end of the pad row in the shift direction, and the bonding point of the pad adjacent to the end pad is determined from the verification starting point as the unit. If the check result is acceptable, the determination is made as a final decision, and if the check result is not possible, the process proceeds to a location shifted by the unit shift amount, and the check result is acceptable. By shifting the bonding point verification to the position shifted by the unit shift amount until the Wire bonding optimization method according to claim 1, continue to determine the grayed point. In the first step, an incident angle allowable value is further input.
The third step calculates a wire incident angle of both end pads on the semiconductor chip side after mounting the semiconductor chip, compares the incident angle on the smaller side with the allowable incident angle, and the incident angle is When the incident angle is smaller than the allowable incident angle, the bonding point verification is shifted to the adjacent bonding point one by one toward the other end of the bonding point row until the incident angle is equal to or larger than the allowable incident angle. The bonding point thus determined is determined as the bonding point corresponding to the pad at the end, and is used as a starting point for verifying the bonding point. The bonding point corresponding to the adjacent pad at the end pad is used as the adjacent bonding at the starting point of the verification. Temporarily decide on a point and make the final decision if the check result is acceptable. Further, the process proceeds to the next bonding point, and the optimum bonding point for all wires is determined by shifting the bonding point verification to the adjacent bonding point one by one until the check result becomes acceptable. Item 2. The wire bonding optimization method according to Item 1. In the first step, an incident angle allowable value and a unit shift amount for bonding point verification are further input,
The third step calculates a wire incident angle of both end pads of the semiconductor chip side after mounting the semiconductor chip, compares the incident angle on the smaller side with the allowable incident angle, and the incident angle is If the incident angle is smaller than the allowable incident angle, the bonding point is shifted to the position shifted by the unit shift amount of the bonding point verification toward the other end of the bonding point row until the incident angle is equal to or greater than the allowable incident angle. The bonding point that is equal to or greater than the allowable incident angle is determined as the bonding point of the end pad, and is used as the starting point of the bonding point verification. The bonding point of the adjacent pad of the end pad is used as the starting point of the verification. If the check result is acceptable If the check result is not possible, the bonding point is further shifted to the position shifted by the unit shift amount of the bonding point verification, and the unit shift amount of the bonding point verification is shifted until the check result is acceptable. The wire bonding optimization method according to claim 1, wherein the verification bonding point is transferred to a location to determine the optimum bonding point for all wires.   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and a part of the bonding fingers has its tip branched into a plurality.   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and the tip of some of the bonding fingers is widened along the chip side direction. Semiconductor device.   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and some bonding fingers are separated in a direction perpendicular to the chip side direction. Semiconductor device installed.   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and the tip of some of the bonding fingers is widened in a direction perpendicular to the chip side direction. Semiconductor device.   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and a series of the plurality of bonding fingers in a row as viewed from above the package substrate is cross-arrayed A semiconductor device arranged to be   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, wherein at least one or more of the pads are provided on the package substrate. A semiconductor device in which the bonding wire is stretched through a bonding relay land.   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers on a package substrate are bonded via bonding wires, and the bonding is performed via a long bonding relay land provided on the package substrate. A semiconductor device in which a wire is stretched and divided into a state in which bonding points are separated after the wire is stretched.   A semiconductor device in which a plurality of pads in a semiconductor chip and a plurality of inner leads in a lead frame package are bonded via bonding wires, and at least the inner lead located at the endmost portion is branched or deformed .   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers or inner leads on a package substrate are bonded via bonding wires, wherein the bonding fingers or the inner leads are located at end portions in the chip side direction. Is a semiconductor device branched or deformed into a plurality.   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers or inner leads on a package substrate are bonded via bonding wires, wherein the wires are close to each other and have cross points between the wires in plan view A semiconductor device in which the bonding finger or the inner lead corresponding to a bonding wire is branched or deformed into a plurality.   A semiconductor device in which a plurality of pads on a semiconductor chip and a plurality of bonding fingers or inner leads on a package substrate are bonded via bonding wires, which correspond to the bonding wires in proximity to each other and having different wire lengths A semiconductor device in which a bonding finger or the inner lead is branched or deformed into a plurality.   21. The semiconductor device according to claim 10, wherein the semiconductor device has a system-in-package structure in which a plurality of the semiconductor chips are stacked and mounted.

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