JP2007257327A - Design support device, design support method and design support program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design support device capable of reducing the man-hour of design verification and preventing mismatching in pin assignment between a logic circuit diagram and a designated component even when the pin assignment is changed as a result of circuit design and substrate layout design based on a precedently prepared logic circuit diagram. <P>SOLUTION: Pin assignment information of an FPGA(field programmable gate array)/PLD(programmable logic device) component and a substrate is extracted from data of a logic circuit diagram of the substrate with the FPGA/PLD component mounted, and the pin assignment information is used to prepare a pin correspondence table for regulating the pin assignment of the FPGA/PLD component on the substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a design support apparatus, a design support method, and a design support program for a semiconductor integrated circuit.

  For example, Patent Document 1 automatically generates a logic circuit diagram of a board (hereinafter referred to as an FPGA / PLD board) on which FPGAs (Field Programmable Gate Arrays) / PLDs (Programmable Logic Devices) are mounted from a pin correspondence table. Discloses a technique for reflecting a change in pin assignment in a logic circuit diagram of an FPGA / PLD mounting board (see Patent Document 1 and FIG. 5).

JP 2002-279010 A

  In the logic circuit design of the conventional FPGA / PLD mounting board, it is necessary to set the pin assignments of the logic circuit diagrams of the FPGA / PLD and the FPGA / PLD mounting board independently. There was a problem of requiring enormous man-hours.

The above problem will be specifically described.
In the conventional logic circuit design, after the FPGA / PLD pin assignment is determined, the FPGA / PLD logic circuit diagram symbol is created, and the logic circuit diagram symbol is arranged to arrange the logic circuit diagram of the FPGA / PLD mounting board. Create This procedure is also assumed in Patent Document 1, and the logic circuit diagram generation device disclosed in Patent Document 1 automatically creates an FPGA / PLD-mounted board logic circuit diagram from the pin correspondence table.

  In the above-described procedure, when creating a new logic circuit diagram based on the logic circuit diagram of the FPGA / PLD mounting board created prior to the creation of the FPGA / PLD logic circuit diagram symbol, the board layout When it is necessary to change the pin assignment according to the design result, it is necessary to manually reflect the change in the pin correspondence table from the logic circuit diagram of the FPGA / PLD mounting board. Such a complicated manual input operation becomes a factor of prolonging the construction period of the FPGA / PLD mounting substrate.

  In general, it takes time to create a logic circuit diagram symbol for FPGA / PLD. In this regard, the logic circuit diagram generation device disclosed in Patent Document 1 automatically creates a symbol for FPGA / PLD logic circuit diagram. However, in Patent Document 1, a power supply and a ground pin other than the bidirectional pins must be added. For this reason, when the FPGA pin name is described on the FPGA / PLD-mounted board logic circuit diagram, a complicated additional work by manual input is required.

Here, a design procedure of a conventional FPGA / PLD mounting board will be described.
First, with respect to a conventional logic circuit creation device as disclosed in Patent Document 1, the pin number of FPGA / PLD, the net name on the circuit diagram of the signal connected to the pin of FPGA / PLD, the net on the circuit diagram Information on the input / output direction of the inter-page connection is input as configuration information of the pin correspondence table. The logic circuit creation device creates a pin correspondence table in which input information is described.

  Subsequently, FPGA / PLD placement and routing is performed using the pin correspondence table. For example, according to the contents of the pin correspondence table, a net (wiring) is connected to a pin specified by a pin number having an FPGA / PLD logic circuit diagram symbol arranged on the circuit diagram. Then, a net name corresponding to the pin number in the pin correspondence table is added as a net name on the circuit diagram. Any change in pin assignment as a result of this placement and routing is reflected in the pin correspondence table.

  Thereafter, a logic circuit diagram symbol for FPGA / PLD is created based on the above-described pin correspondence table after processing, and is arranged on the logic circuit diagram of the FPGA / PLD mounting board. In Patent Document 1, the FPGA / PLD logic circuit diagram symbol has a logic pin name corresponding to the pin specified by the pin number, and the logic pin indicates whether the signal is a bidirectional signal. A symbol (asterisk) is attached. As described above, in Patent Document 1, bidirectional pins are automatically created.

  Next, a logic circuit diagram of the FPGA / PLD mounting board is created by drawing a net or the like. In Patent Document 1, a logic circuit diagram creation device automatically creates a logic circuit diagram of an FPGA / PLD mounting board. Thereafter, the pin name of the FPGA is entered in the symbol for the FPGA / PLD logic circuit diagram on the logic circuit diagram.

  A board layout diagram is created by the board layout diagram creation device based on the logic circuit diagram described above. If there is a change in pin assignment as a result of this board layout design, this change is reflected in the logic circuit diagram of the FPGA / PLD mounting board.

  When all the drawings have been created, the net names in the logic circuit diagram of the FPGA / PLD mounting board and the FPGA pin names in the pin correspondence table are read together to assign the pin assignment between the FPGA / PLD mounting board and the FPGA / PLD. Check if there is a mismatch.

  Thus, in the conventional logic circuit design, it is necessary to read the logic circuit diagram of the FPGA / PLD mounting board and the FPGA / PLD pin correspondence table as a final check of the pin assignment. For both the FPGA / PLD board and the FPGA / PLD, the pin assignment is changed as a result of the board layout design. Therefore, it is not necessary to match the pin assignment between the pin correspondence table and the logic circuit diagram at the stage of creating the circuit diagram. It is enough. For this reason, in the past, in order to prevent pin assignment mistakes, the final check as described above has been indispensable.

  The present invention has been made to solve the above-described problems, and even when the pin assignment is changed as a result of circuit design or board layout design based on a logic circuit diagram created in advance. It is an object of the present invention to obtain a design support apparatus, a design support method, and a design support program that can reduce the number of man-hours for design verification and can prevent inconsistencies in pin assignments between a logic circuit diagram and a specified component.

  The design support apparatus according to the present invention includes circuit diagram processing means for extracting pin assignment information of a specified component and a board from data of a logical circuit diagram of the board on which the specified component is mounted, and designation on the board using the pin assignment information. And a pin correspondence table creating means for creating a pin correspondence table that defines pin assignments of parts.

  According to the present invention, the pin correspondence for specifying the pin assignment of the designated component on the board using the designated part extracted from the logic circuit diagram data of the board on which the designated part such as FPGA / PLD is mounted and the board pin assignment information is used. Since the table is created, there is an effect that the circuit design and the board layout design can be efficiently performed based on the logic circuit diagram created in advance.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a design support apparatus according to Embodiment 1 of the present invention. The design support apparatus according to the first embodiment includes an input / output device 1, an arithmetic processing device 2, a data storage device 3, a board circuit diagram creation device (circuit diagram processing means) 4, and a pin correspondence table editing device (pin correspondence table creation means). 5 is comprised. The input / output device 1 is embodied by an input device such as a keyboard and a mouse for inputting and setting input data, and a display device such as a CRT or LCD for displaying a circuit diagram under design.

  The data storage device 3 stores various programs including the design support program according to the present invention and basic settings, and is used as a work area for various processes such as image processing. The data storage device 3 is capable of data communication via, for example, a hard disk device standardly installed in the computer constituting the design support device according to the first embodiment, a large-capacity storage medium and its playback device, and an electric communication line. A data server or the like can be considered.

  The arithmetic processing device 2 controls data input via the input / output device 1, output of circuit diagrams and the like, exchange of data from the data storage device 3, operation of the board circuit diagram creation device 4 and the pin correspondence table editing device 8. . The board circuit diagram creation device 4 includes a connection information read processing unit 5, a pin number check processing unit 6, and an FPGA pin name update processing unit (update processing unit) 7. The pin correspondence table editing device 8 includes a pin assignment check processing unit 9.

  FIG. 2 is a diagram showing a logic circuit diagram symbol of FPGA / PLD, and FIG. 3 is a diagram showing a logic circuit diagram of an FPGA / PLD mounting board on which the FPGA / PLD logic circuit symbol in FIG. 2 is arranged. . FIG. 4 is a diagram showing a pin correspondence table created based on information obtained from the FPGA / PLD-mounted board logic circuit diagram in FIG. 3 and the pin assignment check result. The operation of each component in the design support apparatus according to the first embodiment will be described with reference to these drawings.

  Note that the FPGA / PLD logic circuit diagram symbol (hereinafter, abbreviated as FPGA / PLD symbol as appropriate) 100 shown in FIG. 2 is not a function of the FPGA / PLD but a general-purpose logic circuit diagram symbol corresponding to the model name. The FPGA pin name setting column 101 and the pin identified by the pin number 102 are included. The FPGA pin name is a net name (FPGA signal name) of a signal on a corresponding pin in the FPGA / PLD symbol.

  Here, the logic circuit diagram symbol of Patent Document 1 is a symbol dedicated to the logic circuit in which logic pins are set for the logic circuit diagram to be designed from the pin correspondence table. On the other hand, the present invention uses general-purpose logic circuit diagram symbols corresponding to the FPGA / PLD model names for which no logic pins are set.

  In the example of FIG. 2, an asterisk (*) is added to the FPGA pin name setting column 101 for bidirectional pins that can be set for signal input / output with respect to components specified by the FPGA / PLD symbols. Both the asterisk indicating the pin and the pin number 102 can be rewritten.

  Furthermore, in the FPGA / PLD symbol handled in the present invention, in addition to bidirectional pins, for example, unidirectional pins that can be set to only input or output of signals to components, such as ground (GND) and power supply (VCC), in advance. Is set. For this one-way pin, the FPGA pin name and pin number cannot be rewritten.

  When a part number is input using the input / output device 1, the arithmetic processing unit 2 controls the substrate circuit diagram creation device 4 to arrange a FPGA / PLD mounting board logical circuit diagram in which FPGA / PLD symbols are arranged as components. From the above, a search is made for those in which the FPGA / PLD symbol specified by the corresponding part number is arranged. For example, when “U1”, which is the part number 115 in FIG. 3, is input via the input / output device 1, the FPGA specified by the part number “U1” corresponding to the FPGA / PLD model name is arranged. The logic circuit diagram 116 of the FPGA / PLD mounting board is retrieved.

  The connection information reading processing unit 5 obtains the pin number 112, the net name 113, and the direction 114 shown in FIG. 3 from the part specified by the part number 115 in the searched logic circuit diagram 116 under the control of the arithmetic processing unit 2. The included pin assignment information is extracted and output to the pin correspondence table editing device 8. The net name 113 is a net name of a signal on a net (wiring) connected to the pin of the FPGA / PLD symbol 110, and the direction 114 is a signal (a signal specified by the net name 113) input to the component ( IN) or output from the component (OUT).

  In designing a board on which an FPGA / PLD is mounted, the logic circuit design of a printed circuit board is advanced while changing the pin assignment of the FPGA / PLD taking advantage of the characteristics of the FPGA / PLD. Therefore, when the FPGA / PLD pin assignment in the logic circuit diagram 116 of the FPGA / PLD mounting board is changed, in the present invention, the pin number check processing unit 6 controls the original logic circuit diagram under the control of the arithmetic processing unit 2. Check whether the data and the pin number are different from those other than the layout change.

  The pin correspondence table editing device 8 holds a pin correspondence table of the logic circuit diagram 116 of the FPGA / PLD mounting board created by the board circuit diagram creation device 4. For example, the pin correspondence table having the FPGA pin name, net name, pin number, and direction as components in the logic circuit diagram 116 shown in FIG. 3 can be edited or changed by the pin correspondence table editing device 8. It is stored in a storage device or the like.

  As a result of the check by the pin number check processing unit 6, as the pin number having a difference other than the change in arrangement, the data of the original logic circuit diagram extracted by the connection information reading processing unit 5 matches the logic circuit diagram data after the change. When there is a pin number, the pin correspondence table editing device 8 updates the row content corresponding to the pin number 112 in the pin correspondence table under the control of the arithmetic processing device 2. On the other hand, if there is no matching pin number, the pin number 112, the net name 113, and the direction 114 in the changed logic circuit diagram are described as the contents of a newly provided row on the pin correspondence table.

  Simultaneously with the processing by the pin correspondence table editing device 8 described above, the FPGA pin name update processing unit 7 changes the FPGA pin name as a check result by the pin number check processing unit 6 under the control of the arithmetic processing device 2. If there is a pin number that matches the pin number, the FPGA pin name 111 corresponding to the pin number is read from the logic circuit diagram after the change, and the row of the corresponding pin number in the pin correspondence table of the logic circuit diagram 116 before the change The FPGA pin name 121 is updated with the changed FPGA pin name.

  In this way, the contents of the original pin correspondence table are updated or new contents are added using the changed pin assignment information in the logic circuit diagram 116 of the FPGA / PLD mounting board, for example, as shown in FIG. Such a pin correspondence table 120 is created.

  Here, by executing a pin assignment check command via the input / output device 1, the pin assignment check processing unit 9 of the pin correspondence table editing device 8 executes pin assignment check processing under the control of the arithmetic processing device 2. To do. In the pin assignment check, it is determined whether or not the FPGA pin name 121 and the net name 122 match in the pin correspondence table (see FIG. 4) generated as described above.

  The FPGA pin name 121 corresponds to the signal name at the corresponding FPGA pin, and the net name on the board of the signal from this pin is the net name 122. Therefore, if the FPGA pin name and the net name match, that fact Is displayed on the display device of the input / output device 1 as shown in the pin assignment check result 125 in FIG.

  Here, a case where the FPGA pin name and the net name cannot be matched will be described. As an example where the FPGA pin name and the net name cannot be matched, a case where the same FPGA / PLD symbols U1 and U2 are arranged on the board logic circuit diagram 116 as shown in FIG.

  In this case, if the net names connected to the FPGA / PLD symbols U1 and U2 are not unique in the drawing, it is not possible to distinguish which of the FPGA / PLD symbols U1 and U2 is connected to the net. Therefore, in the example of FIG. 5, the net names 113 of the FPGA / PLD symbol U1 are sigAE3 to sigAE0, respectively, and the net names 113 of the FPGA / PLD symbol U2 are sigBE3 to sigBE0, respectively.

  Therefore, as shown in FIG. 6, the FPGA pin name 121 and the net name 122 do not match. In this case, like the pin assignment check result 126, only the range of serial numbers 0 to 3 (terminal numbers) assigned to each pin for the FPGA signal name that is the FPGA pin name 121 is described, and sigE [3: 0] Only the range of serial numbers 0 to 3 (terminal numbers) assigned to each pin for the net name 122 is described and displayed as sigAE [3: 0]. In this way, visual check can be easily performed by automatically displaying the FPGA signal name and the end number of the net name together.

  The arithmetic processing device 2, the board circuit diagram creation device 4, the connection information reading processing unit 5, the pin number check processing unit 6, the FPGA pin name update processing unit 7, the pin correspondence table editing device 8, and the pin assignment check processing unit 9 The design support program according to the present invention is executed by the CPU of the computer that constitutes the design support apparatus according to the first embodiment, and the operation is controlled so that the hardware and software cooperate with each other. Can be realized on a computer.

  In the following description, the configuration of the computer itself that embodies the design support apparatus of the present invention and the basic functions thereof can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. The detailed description is omitted because it is not directly related to the essence of the invention.

  FIG. 7 is a block diagram showing a configuration in which the design support apparatus according to the first embodiment shown in FIG. 1 and the board layout drawing creation apparatus are combined. In FIG. 7, the same components as those in FIG. The reflection processing unit 10 (hereinafter referred to as the reflection processing unit 10) of the layout diagram in the circuit diagram is a pin in the board layout diagram created by the board layout diagram creation device 11 based on the logic circuit diagram of the FPGA / PLD mounting board. A process of reflecting the change of assignment in the original FPGA / PLD-mounted board logic circuit diagram is executed. The board layout diagram creation device 11 creates a board layout diagram based on the FPGA / PLD-mounted board logic circuit diagram created by the board circuit diagram creation device 4.

  Also for the reflection processing unit 10, the hardware and software cooperate by causing the CPU of the computer constituting the design support apparatus according to the first embodiment to execute the design support program according to the present invention and controlling the operation thereof. It can be realized on the computer as a specific means.

Next, the operation will be described.
FIG. 8 is a flowchart showing the operation of the apparatus configuration shown in FIG. 7, and details of processing for simultaneously performing the logic circuit diagram design and the board layout design of the FPGA / PLD mounting board will be described with reference to this figure.
First, the board circuit diagram creation device 4 reads the data of the FPGA / PLD symbol (for example, corresponding to FIG. 2) from the data storage device 3, and arranges the FPGA / PLD symbol on the logic circuit diagram (step ST1).

  Subsequently, the board circuit diagram creation device 4 creates a logic circuit diagram of the FPGA / PLD mounting board by connecting nets (wirings) to the pins of the arranged FPGA / PLD symbols (step ST2). Here, the FPGA pin name corresponding to the FPGA pin name setting field 101 shown in FIG. 2 is set. The logic circuit diagram data of the FPGA / PLD mounted board created in this way is output to the board layout drawing creating apparatus 11 via the reflection processing unit 10.

  The board layout diagram creation device 11 creates a board layout diagram that takes into account the actual dimensions of the components based on the logic circuit diagram of the FPGA / PLD mounting board created by the board circuit diagram creation device 4 (step ST3). . The creation of the board layout diagram may use an existing layout diagram creation technique.

  Simultaneously with step ST3, the connection information reading processing unit 5 of the board circuit diagram creation device 4 extracts the pin assignment information including the pin number, the net name, and the direction from the logic circuit diagram of the FPGA / PLD mounting board created in step ST2. Then, the data is output to the pin correspondence table editing device 8.

  As a result, the pin correspondence table editing device 8 uses the pin assignment information extracted by the connection information reading processing unit 5 under the control of the arithmetic processing device 2, and the logic circuit of the FPGA / PLD mounting board created in step ST2. A pin correspondence table having the pin number of the FPGA / PLD symbol and the corresponding FPGA pin name, net name and direction in the figure as components is automatically generated (step ST6).

  When the pin correspondence table is generated in step ST6, the board circuit diagram creation device 4 performs placement / wiring of FPGA / PLD symbols according to the pin correspondence table. As described above, in designing the board on which the FPGA / PLD is mounted, the logic circuit design of the printed board is advanced while changing the FPGA / PLD pin assignment. For this reason, the pin assignment may be changed in the placement and routing.

  Therefore, when there is a change in the pin assignment in the FPGA / PLD symbol arrangement and wiring, the connection information reading processing unit 5 controls the pin number from the circuit diagram in which the FPGA / PLD symbol is arranged and wired under the control of the arithmetic processing unit 2. Pin assignment information including the net name and direction is extracted and output to the pin correspondence table editing device 8. Thereafter, the pin number check processing unit 6 compares the pin assignment information extracted by the connection information reading processing unit 5 with the pin assignment information in the original pin correspondence table before the change, and other than the pin number arrangement change Check whether they are different.

  As a result of this check, if there is a pin number that matches the pin number to which a change other than the layout change has been made, the pin correspondence table editing device 8 uses the pin number extracted by the connection information read processing unit 5 for the pin number, The net name and direction are input, and the row content corresponding to the pin number in the original pin correspondence table is updated. If there is no matching pin number, the pin number, net name, and direction are described as the contents of a newly provided line on the pin correspondence table. Simultaneously with this processing, the FPGA pin name update processing unit 7 updates the original pin correspondence table with the FPGA pin name corresponding to the changed pin number. As a result, the pin correspondence table is updated according to the result of the FPGA / PLD symbol placement and routing (step ST7).

  Subsequently, the FPGA pin name update processing unit 7 automatically applies the FPGA pin name updated in step ST7 to the logic circuit diagram of the FPGA / PLD mounted board created in step ST2 under the control of the arithmetic processing unit 2. (Step ST8).

  On the other hand, in step ST4, when there is a change in the pin assignment as a result of the board layout design in step ST3, the reflection processing unit 10 uses this change information as the logic circuit diagram of the FPGA / PLD mounted board created in step ST2. A process of reflecting the above FPGA / PLD symbol is executed. For example, when the pin number is changed as a result of the board layout design, the change contents are reflected in the logic circuit diagram of the FPGA / PLD mounting board.

  When the processes of step ST4 and step ST8 are completed, the pin assignment check processing unit 9 controls the arithmetic processing unit 2 to reflect the logic circuit diagram in which the change in the board layout is reflected in step ST4 and the logic circuit after the process of step ST8. For the figure, the pin assignment check process is automatically executed (step ST5).

  Here, it is determined whether or not the FPGA pin name matches the net name. At this time, if the FPGA pin name and the net name match, the pin assignment check processing unit 9 determines that the pin assignments match on the FPGA / PLD side and the board side in the logic circuit diagram, and calculates that. The processing device 2 is notified.

  The arithmetic processing unit 2 controls the display device of the input / output device 1 to display the pin correspondence table and the pin assignment check result 125 on the display screen. On the other hand, when the FPGA pin name and the net name cannot be matched, the FPGA signal name and the end number of the net name are automatically set together with the pin correspondence table as shown in the pin assignment check result 126 shown in FIG. Display differences collectively.

  As described above, according to the first embodiment, the pin correspondence table of the circuit diagram is created from the pin assignment information extracted from the logic circuit diagram of the FPGA / PLD mounting board, and the pin assignment is changed every time the pin assignment is changed. Since the change is reflected in the correspondence table, the circuit design and the board layout design can be efficiently performed based on the logic circuit diagram created in advance. There is no need to previously create a PLD symbol, and this creation process can be reduced.

  Further, according to the first embodiment, since the board layout design and the logic circuit design of the FPGA / PLD mounting board can be performed at the same time, the work period can be shortened by the simultaneous progress of both operations.

  Further, according to the first embodiment, since the match / mismatch between the FPGA pin name and the net name in the pin correspondence table is automatically checked, the pin assignment mismatch can be prevented.

  In the first embodiment, an example in which the pin correspondence table of the logic circuit diagram of the FPGA / PLD mounting board is automatically generated in step ST6 of FIG. 8 in parallel with the board layout drawing creation process in step ST3 is shown. However, the pin correspondence table may be created by inputting while simultaneously performing the operations as described below. Thus, the construction period can be shortened by simultaneously carrying out a plurality of operations.

  For example, a pin correspondence table relating to the logic circuit diagram of the FPGA / PLD mounting board is created in parallel with the processing from step ST1 to step ST4 in FIG. In this case, a pin correspondence table of the logic circuit diagram is generated using the pin assignment information set in step ST2 corresponding to the arrangement in step ST1. After the creation of the pin correspondence table, the processing in step ST7 and step ST8 in FIG. 8 is performed, and in step ST5, the match / mismatch between the FPGA pin name and the net name in the pin correspondence table is automatically checked.

  Further, the FPGA / PLD symbol pin correspondence table may be created in parallel with the processing from step ST2 to step ST4 in FIG. In this case, a pin correspondence table is created using the pin assignment information of the logic circuit diagram of the FPGA / PLD mounting board created in step ST2. After the creation of the pin correspondence table, the processing in step ST7 and step ST8 in FIG. 8 is performed, and in step ST5, the match / mismatch between the FPGA pin name and the net name in the pin correspondence table is automatically checked.

  As described above, the creation of the pin correspondence table may be processed according to the flow shown in FIG. 9, for example, without performing parallel processing. FIG. 9 is a flowchart showing another example of the operation of the design support apparatus shown in FIG. In FIG. 9, the process from step ST1 to step ST4 is the same as that of FIG. After the process of step ST4, the pin correspondence table of the logic circuit diagram of the FPGA / PLD mounting board is automatically generated in the same manner as in step ST6 of FIG. 8 (step ST5c).

Thereafter, similarly to step ST7 of FIG. 8, FPGA / PLD symbol placement and routing is performed based on the pin correspondence table generated in step ST5c. Here, when a change occurs in the pin assignment, the change is reflected in the pin correspondence table (step ST6c).
Subsequently, as in step ST8 of FIG. 8, the FPGA pin name in the logic circuit diagram of the FPGA / PLD mounting board created in step ST2 is updated with the FPGA pin name of the pin correspondence table generated in step ST5c ( Step ST7c).

  Finally, the pin assignment check process is automatically executed in the same manner as in step ST5 of FIG. 8 (step ST8c). Even in such a flow, the automatic generation of the FPGA / PLD symbol pin correspondence table eliminates the need to create a dedicated FPGA / PLD symbol in advance in the logic circuit diagram to be designed in the circuit design. Can be reduced. In addition, since a match / mismatch between the FPGA pin name and the net name in the pin correspondence table is automatically checked, a pin assignment mismatch can be prevented.

It is a block diagram which shows the structure of the design assistance apparatus by Embodiment 1 of this invention. It is a figure which shows the circuit symbol of FPGA / PLD. FIG. 3 is a diagram showing an FPGA / PLD-mounted substrate logic circuit diagram using the FPGA / PLD circuit symbol in FIG. 2. It is a figure which shows the pin correspondence table based on the FPGA / PLD mounting board | substrate logic circuit diagram in FIG. 3, and a pin assignment check result. It is a figure which shows the FPGA / PLD mounting board | substrate logic circuit diagram which has arrange | positioned the same FPGA / PLD circuit symbol on a board | substrate. FIG. 6 is a diagram showing a pin correspondence table and a pin assignment check result based on the FPGA / PLD-mounted board logical circuit diagram in FIG. 5. It is a block diagram which shows the structure which combined the design support apparatus and board | substrate layout drawing production apparatus by Embodiment 1 shown in FIG. It is a flowchart which shows the operation | movement by the apparatus structure shown in FIG. It is a flowchart which shows the other operation example by the apparatus structure shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Input / output device, 2 Arithmetic processing device, 3 Data storage device, 4 Substrate circuit diagram creation device (circuit diagram processing means) 5 Connection information reading processing unit, 6 Pin number check processing unit, 7 FPGA pin name update processing unit ( Update processing unit), 8-pin correspondence table editing device (pin correspondence table creation means), 9-pin assignment check processing unit, 10 reflection processing unit, 11 board layout drawing creation device, 100/110 FPGA / PLD logic circuit symbol 101 FPGA pin name setting field, 111, 121 FPGA pin name, 102, 112, 123 pin number, 113, 122 Net name, 114, 124 direction, 115 part number, 116 Logic circuit diagram of FPGA / PLD mounting board, 125, 126 Pin assignment check results.

Claims (16)

Circuit diagram processing means for extracting pin assignment information of the designated component and the board from data of a logic circuit diagram of the board on which the designated part is mounted;
A design support apparatus, comprising: a pin correspondence table creating means for creating a pin correspondence table that defines the pin assignment of the specified component on the substrate using the pin assignment information.   The pin assignment information includes a pin number for identifying the pin of the designated component, a net name for identifying a signal on the net connected to the pin, and a direction for identifying an input or output of the signal on the net for the designated component. The design support apparatus according to claim 1, comprising information.   The specified component is a logic circuit diagram symbol corresponding to the FPGA / PLD component model name, and the pin name and pin number for identifying the signal on the pin can be rewritten, and either the signal input or output 3. The design support apparatus according to claim 1, further comprising: a bidirectional pin capable of setting one of the pins, and a pin whose pin name and pin number are not rewritable and whose signal input / output direction cannot be set. . Circuit diagram processing means
Connection information read processing unit that extracts the pin assignment information of the specified component and the board from the logic circuit diagram data of the board on which the specified component is mounted, and whether there is a pin number related to the change in the logic circuit diagram before and after the pin assignment change And a board circuit diagram creating device having a pin number check processing unit for determining the pin correspondence table and an update processing unit for updating the pin correspondence table before the change with the pin name of the designated part in the logic circuit diagram after the pin assignment change,
The pin correspondence table creation means is
Of the pin assignment information extracted from the data of the logic circuit diagram after the pin assignment change by the connection information reading processing unit, the pin assignment information for the pin number determined to be related to the change by the pin number check processing unit is used. 4. The design support apparatus according to claim 2, further comprising: a pin correspondence table editing device that updates a pin correspondence table before change.   5. A pin assignment check processing unit for determining whether or not the pin assignment information of a specified component in the pin correspondence table matches the pin assignment information of the board. The design support apparatus according to claim 1. The pin assignment check processing unit matches the pin name that specifies the signal on the pin as the pin assignment information of the specified component and the net name that specifies the signal on the net connected to the pin as the pin assignment information of the board. Whether or not
The pin name and the net name are presented by describing only a range of serial numbers given to the pin name and the net name for each pin when the pin name and the net name do not match. 5. The design support apparatus according to 5.   The design support apparatus extracts pin assignment information of the designated component and the board from the logic circuit diagram data of the board on which the designated part is mounted, and uses the pin assignment information to assign the pin assignment of the designated part on the board. A design support method for creating a pin correspondence table.   The pin assignment information includes a pin number that identifies a pin of a designated component, a net name that identifies a signal on the net connected to the pin, and a direction that identifies the input or output of the signal on the net for the designated component. The design support method according to claim 7, comprising information.   The specified component is a logic circuit diagram symbol corresponding to the FPGA / PLD component model name, and the pin name and pin number for identifying the signal on the pin can be rewritten, and either the signal input or output 9. A design support method according to claim 7, comprising: a bidirectional pin capable of setting one of the pins, and a pin whose pin name and pin number are not rewritable and whose signal input / output direction cannot be set. .   The design support device determines whether there is a pin number related to the change in the logic circuit diagram before and after the pin assignment change, and updates the pin correspondence table before the change with the pin name of the specified component in the logic circuit diagram after the pin assignment change. At the same time, of the pin assignment information extracted from the data of the logic circuit diagram after the pin assignment change, the pin correspondence table before the change is updated using the pin assignment information for the pin number determined to be related to the change. 10. The design support method according to claim 8 or 9, wherein   The design support apparatus determines whether or not the pin assignment information of the specified component in the pin correspondence table matches the pin assignment information of the board. The design support method described.   Circuit processing means for extracting pin assignment information of the designated component and the board from the logic circuit diagram data of the board on which the designated part is mounted, and pin assignment of the designated part on the board is defined using the pin assignment information A design support program that causes a computer to function as a pin correspondence table creation means for creating a pin correspondence table.   The pin assignment information includes a pin number that identifies a pin of a designated component, a net name that identifies a signal on the net connected to the pin, and a direction that identifies the input or output of the signal on the net for the designated component. 13. The design support program according to claim 12, comprising information.   The specified component is a logic circuit diagram symbol corresponding to the FPGA / PLD component model name, and the pin name and pin number for identifying the signal on the pin can be rewritten, and either the signal input or output 14. The design support program according to claim 12, further comprising: a bidirectional pin capable of setting one of the pins, and a pin whose pin name and pin number cannot be rewritten and whose signal input / output direction cannot be set. . Circuit diagram processing means
Connection information read processing unit that extracts the pin assignment information of the specified component and the board from the logic circuit diagram data of the board on which the specified component is mounted, and whether there is a pin number related to the change in the logic circuit diagram before and after the pin assignment change And a board circuit diagram creating device having a pin number check processing unit for determining the pin correspondence table and an update processing unit for updating the pin correspondence table before the change with the pin name of the designated part in the logic circuit diagram after the pin assignment change,
The pin correspondence table creation means is
Of the pin assignment information extracted from the data of the logic circuit diagram after the pin assignment change by the connection information reading processing unit, the pin assignment information for the pin number determined to be related to the change by the pin number check processing unit is used. 15. The design support program according to claim 13, comprising a pin correspondence table editing device for updating a pin correspondence table before change.   The pin assignment check processing unit for determining whether or not the pin assignment information of the specified component in the pin correspondence table matches the pin assignment information of the board is provided. The design support program according to claim 1.

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