JP2007257109A - Nonvolatile storage device, method for writing data therein, nonvolatile storage system, and memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a nonvolatile storage device using a multivalued flash memory wherein data other than data being written could be destroyed should power be interrupted while the data are being written. <P>SOLUTION: Binary data are written in a physical block PB 5 by writing in a binary mode. The binary data in the PB 5 are aggregated in multivalued data in a completely written block PB 4 where an aggregation process has already been performed, and multivalued data are written in another new physical block PB 6. The data written in the PB 5 with the same logic page number as the data in the PB 4 are replaced by the data in the PB 4 while other data are written in the PB 6 as the data in the PB 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device using a nonvolatile semiconductor memory element capable of recording multi-value data, a data writing method thereof, a nonvolatile memory system, and a memory controller.

  There are various types of recording media for recording digital data such as music content and video data, such as magnetic disks, optical disks, and magneto-optical disks. A semiconductor memory card which is one of these recording media uses a non-volatile semiconductor memory such as a flash memory as its storage element, and is easy to miniaturize. Thus, a small size such as a digital still camera or a cellular phone terminal is used. It is spreading rapidly, especially in mobile devices. In recent years, high recording image quality has been demanded in digital cameras and the like, and high data recording speed is required in addition to high recording density in nonvolatile semiconductor memories.

  In order to further improve the recording capacity of the flash memory, a flash memory capable of storing a plurality of bits of data in one memory cell has been developed. Since this is a flash memory capable of recording multi-value data, it is called a multi-value flash memory. According to this, since the recording density per unit area of the flash memory can be increased and the recording capacity can be increased, the number of memory cells in the same recording capacity can be reduced, and the price of the flash memory for the same capacity can be reduced. Is possible.

  Hereinafter, a recording method of the multilevel flash memory will be described. Generally, a nonvolatile semiconductor memory such as a flash memory stores data by utilizing a phenomenon that a threshold voltage of a memory cell changes when electrons are injected into a floating gate or a trap gate of the memory cell. Incidentally, the threshold voltage of the memory cell is high when electrons are present in the floating gate, and is low when electrons are not present in the floating gate.

  FIG. 13 is a diagram showing a threshold voltage distribution of a memory cell in a quaternary flash memory storing 2-bit data in one memory cell. The threshold voltage of the memory cell is distributed in any of the regions L0, L1, L2, and L3 according to the corresponding 2-bit data. The areas L0, L1, L2, and L3 correspond to 2-bit data “11”, “10”, “00”, and “01”, respectively.

  Data writing is realized by repeating a program for changing the threshold voltage of each memory cell until the verification voltage VV (VV1, VV2, VV3) is exceeded. The threshold voltage of the memory cell to which no data is written is the region L0, and when data “11” is written, the program for changing the threshold voltage is not executed. On the other hand, when data “10” is written in the memory cell, the program operation is repeated until the threshold voltage of the memory cell exceeds the verification voltage VV1, and the threshold voltage is changed to fall within the region L1.

  Data reading is realized by comparing the threshold voltage of the memory cell with the reference voltage VR (VR1, VR2, VR3). When the threshold voltage of the memory cell is lower than the reference voltage VR1, it is determined that the data held in the memory cell is “11”, and when the threshold voltage of the memory cell is between the reference voltages VR1 and VR2, It is determined that the data held in the cell is “10”. Similarly, when the threshold voltage of the memory cell is between the reference voltages VR2 and VR3, it is determined to be “00”, and when the threshold voltage of the memory cell is higher than the reference voltage VR3, it is determined to be “01”.

  Erasing data in the memory cell is completed by supplying a low voltage to the control gate of the memory cell to be erased, supplying a high voltage to the well region of the memory cell, and releasing electrons accumulated in the floating gate. . At this time, the control gates of the memory cells that are not erased are placed in a floating state separated from the power supply, for example.

  When multi-value data is recorded in one memory cell, data writing to the nonvolatile memory cell is performed in a plurality of stages. For example, as shown in FIG. 13, when the regions L0, L1, L2, and L3 correspond to 2-bit data “11”, “10”, “00”, and “01”, respectively, the lower 1 2-bit data is written in two stages, that is, writing bit data and writing upper 1-bit data. Hereinafter, the second and subsequent writings to the memory cell are referred to as “additional writing”.

  For example, when data “1” is written in the lower 1 bit of one memory cell, the threshold voltage of the memory cell is set so as to be in the region L0 when data “0” is written in the lower 1 bit data. Set. Thereafter, when data is additionally written to the upper 1 bit, when the upper 1 bit data is “1”, it is not necessary to change the threshold voltage. When the upper 1-bit data is “0”, the program operation for changing the threshold voltage is further repeated to change the threshold voltage from the region L0 to the region L3 or from the region L1 to the region L2.

In the semiconductor memory device of Patent Document 1 using such a multi-value flash memory, the memory array is divided into a multi-value region for storing multi-value data and a binary region for storing binary data according to the physical block address. Therefore, data requiring high write reliability is written in the binary area, and data requiring a large capacity is written in the multi-value area.
JP 2000-173281 A

  However, the technique as in Patent Document 1 has the following problems. In multi-value data writing, for example, if the power supply is cut off in the process in which the threshold voltage of the memory cell is changed from the region L0 to the region L3 shown in FIG. 13, the threshold voltage of the memory cell does not reach the region L3. There is a case where it remains outside L1, the region L2, or the region. As described above, when the power supply is interrupted during the additional writing of the upper 1-bit data, not only the upper 1-bit data being written but also the already-written lower 1-bit data is changed to erroneous data. For the reasons described above, a memory storing multi-values of 2 bits or more is liable to generate a data error, and the data writing reliability is lower than that of a memory storing binary values with 1 bit.

  Therefore, Patent Document 1 shows a method of selectively using binary writing and multi-value writing. In this usage, since a multi-value memory cell is used like a binary memory cell, the amount of data that can be stored However, the memory cost per unit data amount increases. When a quaternary memory cell that stores 2-bit multi-value data is used like a binary memory cell that stores 1-bit binary data, the amount of data that can be stored in the memory is halved. Costs double.

  The present invention has been made to solve the above-described problems. Even if the power is interrupted during data writing, the written data is not destroyed, and moreover, per unit data amount of the multi-level flash memory. It is an object of the present invention to effectively use a multi-value flash memory without impairing the economics of the system.

  In order to solve this problem, a method of writing data in a nonvolatile memory device according to the present invention includes a plurality of memory cells having M (M> 3, M is an integer) threshold voltage regions. Non-volatile memory comprising a plurality of physical pages that are configured data write units and having a plurality of physical blocks that are data erase units, and data using two threshold voltage regions of the M threshold voltage regions A memory controller that writes data to the non-volatile memory and reads data from the non-volatile memory by binary mode writing that writes data and multi-value mode writing that writes data using M threshold voltage regions; A method for writing data in a nonvolatile memory device, wherein a physical block of the nonvolatile memory is external to the nonvolatile memory device. A write completion block in which data is written to all of the plurality of physical pages corresponding to a logical address designated by the access device, a write block to which data corresponding to the address designated by the access device is written, and data The memory controller always writes data to the write block by the binary mode write, and the data is written to all physical pages of the write block. In this case, an aggregation process is performed in which the data of the write completion block and the write block having the same logical address are copied to the empty block by binary mode writing or multilevel mode writing.

  In order to solve this problem, the nonvolatile memory device of the present invention includes a plurality of memory cells having threshold voltage regions of M (M> 3, M is an integer), and data including the plurality of memory cells. A non-volatile memory comprising a plurality of physical pages, which are write units, and a plurality of physical blocks, which are data erase units, and a binary value for writing data using two threshold voltage regions of the M threshold voltage regions A nonvolatile controller comprising: a memory controller that writes data to the nonvolatile memory and reads data from the nonvolatile memory by either mode writing or multi-value mode writing that writes data using M threshold voltage regions The physical block of the non-volatile memory is a logical address designated by an access device outside the non-volatile storage device. Correspondingly, a write completion block in which data is written to all of the plurality of physical pages, a write block in which data corresponding to an address designated by the access device is written, and an empty block in which data has been erased The memory controller always writes data to the write block by the binary mode write, and when the data is written to all physical pages of the write block, the logical address is common. Aggregation processing for copying the data of the write completion block and the write block to the empty block by binary mode write or multi-value mode write is performed.

  In order to solve this problem, the nonvolatile memory system of the present invention includes a plurality of memory cells having threshold voltage regions of M (M> 3, M is an integer), and data configured by the plurality of memory cells. A non-volatile memory comprising a plurality of physical pages, which are write units, and a plurality of physical blocks, which are data erasure units, and a binary value for writing data using two threshold voltage regions of the M threshold voltage regions A memory controller that writes data to and reads data from the nonvolatile memory by either mode writing or multi-value mode writing that writes data using M threshold voltage regions; A nonvolatile storage system comprising: an access device that instructs writing and reading of data to and from the nonvolatile memory The physical block of the nonvolatile memory includes a write completion block in which data is written in all of the plurality of physical pages corresponding to a logical address specified by an access device outside the nonvolatile storage device, Including a write block in which data corresponding to an address designated by the access device is written and an empty block in which data is erased, and the memory controller always writes the binary mode to the write block. When the data is written in all the physical pages of the writing block, data in the writing completion block and the writing block having a common logical address can be written in binary mode writing or multi-value mode writing. Performs aggregation processing to copy to the empty block That.

In order to solve this problem, the memory controller of the present invention has a plurality of memory cells having M (M> 3, M is an integer) threshold voltage region, and data writing composed of the plurality of memory cells is performed. A physical block, which is composed of a plurality of physical pages as a unit and is a data erasing unit, has data written to all of the plurality of physical pages in correspondence with a logical address designated by an access device outside the nonvolatile storage device. M non-volatile memories including a write complete block, a write block into which data corresponding to an address designated by the access device is written, and an empty block in which data is erased Binary mode writing in which data is written using two threshold voltage regions of the threshold voltage regions, and M threshold voltage regions are used. A memory controller that writes data to and reads data from the non-volatile memory by any of multi-value mode writing, and always writes data to the writing block by the binary mode writing. And when the data is written to all the physical pages of the write block, the write complete block and the write block data having a common logical address are written in binary mode or multi-value mode. Aggregation processing for copying to a block is performed.

  Here, the memory controller, when copying the data of the write completion block and the write block to the empty block by binary mode write or multi-value mode write, writes the write completion block and the logical address in common. If there is no block, an empty block in which no data is written may be used as the write completion block.

  Here, the memory controller includes a first table relating a logical address obtained from an address designated by the access device and a physical address indicating the write completion block, and a physical address indicating the logical address and the write block. And a logical-physical conversion table having a second table related to.

  Here, the memory controller copies the latest data for each logical address unit corresponding to the physical page in the aggregation process, and writes the binary mode based on the logical address designated by the access device. It may be determined whether to copy by the multi-value mode writing.

  Here, the nonvolatile memory includes a normal area where data can be read and written by arbitrarily accessing from the access device, and an authentication area where data can be read and written only when access from the access device is authenticated. And the aggregation processing in the authentication area may be performed by the multi-value mode writing.

  Here, as the two threshold voltage regions used in the binary mode writing, two adjacent threshold voltage values may be selected from all the threshold voltage regions.

  Here, the nonvolatile memory may have a plurality of super blocks each composed of a plurality of physical blocks, and the write completion block, the write block, and the empty block may be composed of units of the super block.

  Since the data writing of the present invention is always writing only to the first cell page with respect to the memory cell in which the written data is not stored, the written data is not destroyed by the power shutdown. The data aggregation process for the physical block to which data has been written is a process of copying the written data to another physical block, so even if the power is cut off during the aggregation process, the written data before copying is destroyed. There is nothing. Furthermore, since the aggregation process is performed as soon as data is written to all the first cell pages of the physical block, the written data can be densified, and an increase in cost per unit data amount can be prevented. .

  FIG. 1 is a diagram illustrating a nonvolatile memory system according to the present embodiment, and includes a nonvolatile memory device and an access device that accesses the nonvolatile memory device. The nonvolatile storage device 100 is a semiconductor memory card, and the access device 200 is a host device that writes data to and reads data from the nonvolatile storage device 100. The nonvolatile storage device 100 includes a memory controller 110 that controls writing and reading of data to and from the nonvolatile memory 120 in accordance with instructions from the access device, and the nonvolatile memory 120.

  The memory controller 110 includes a host interface 111 that exchanges commands and data with the access device 200, and a logical-physical conversion that is a table that converts a logical address designated by the access device 200 into a physical address in the nonvolatile memory 120. Table 112. The memory controller 110 further includes an empty block management table 113 that manages the usage status in the nonvolatile memory 120 and a read / write control unit 114 that controls writing and reading of data with respect to the nonvolatile memory 120.

  The nonvolatile memory 120 is composed of a NAND flash memory having a plurality of physical blocks as data erasing units, and includes a management data storage area 121 and a data storage area 122. The management data storage area 121 stores information that the user cannot directly access, that is, information that cannot be accessed from the access device 200. Information that cannot be directly accessed by the user includes a part of address management information and system information. The data storage area 122 stores data that can be accessed by the user, that is, data that can be rewritten or read by designating a logical address from the access device 200. File system information also exists in this area. In this embodiment, it is assumed that the data storage area 122 is managed by the FAT file system.

  FIG. 2 is a block diagram showing the internal state of the nonvolatile memory 120. The nonvolatile memory 120 is composed of 1024 physical blocks PB0 to PB1023. The physical block is a data erasing unit of the nonvolatile memory 120 and has a capacity of 256 kB (bytes). The data storage capacity of the entire nonvolatile memory 120 is 256 MB.

  FIG. 3 is a block diagram showing the inside of one physical block. The physical block is composed of 128 physical pages PP0 to PP127. A physical page is a minimum unit of data writing in the nonvolatile memory 120, and each physical page has a data capacity of 2 kB for storing data and 64 B for storing management information.

  FIG. 4 shows the contents of the logical / physical conversion table 112. In the logical-physical conversion, the logical block LB obtained from the logical address designated by the access device 200 is associated with the physical block of the nonvolatile memory 120, and each logical block LB has a plurality of logical pages LP. . Such a logical-physical conversion table 112 includes a table 112A for managing a write completion block in which data is written to all physical pages in the physical block among the physical blocks of the nonvolatile memory 120, and a data write. And a table 112B for managing a block in the middle of writing that has a physical page that has not been written. In FIG. 4, the logical block LB1 corresponds to the physical blocks PB358 and PB38. That is, the physical block PB358 is a write completion block in which data is written to all physical pages, but the physical block PB38 is registered as a writing intermediate block in which a physical page to which data is written remains. Show. This indicates that data of the same logical block as that of the physical block PB358 is written in the physical block PB38. As described above, one logical block can correspond to a maximum of two physical blocks, that is, one write completion block and one write intermediate block.

  The block registered as a writing intermediate block is used as a writing block for writing new data, and a maximum of three physical blocks are registered. When three sets of logical blocks and physical blocks are registered as blocks in the middle of writing and it is necessary to newly register logical blocks and physical blocks, the data of the physical blocks already registered will be described later. An aggregation process is performed, and after the aggregation process is completed, registration of the logical block corresponding to the physical block is canceled and a new logical block and physical block are registered.

  Next, FIG. 5 is a diagram showing the configuration of the free block management table 113. The free block management table 113 is a table indicating whether each physical block is used as a write completion block or is not used. In the figure, “in use” indicates that the physical block is a write complete block or a block in the middle of writing, and “empty” indicates that there is a physical page for writing data in the physical block. . In this way, the physical block corresponds to the write completion block in which data is written in all the physical pages corresponding to the logical address specified by the access device outside the nonvolatile storage device, and the address specified by the access device. There are write blocks in which the written data is written and empty blocks in which valid data is not written.

[How to use multi-value memory cells]
The nonvolatile memory 120 of this embodiment has multi-value memory cells. The multi-value memory cell has M (M> 3, M is an integer) threshold voltage region, and data is written by changing the threshold voltage to that region. The memory cell of this embodiment can write 2-bit data of “00” to “11” using four threshold voltage regions. The multilevel memory cell is composed of two cell pages, and 1-bit data is written in each cell page. Of the 2-bit data written in the memory cell, the lower 1 bit is the data of the first cell page, and the upper 1 bit is the data of the second cell page. That is, the first cell page and the second cell page are one set sharing a memory cell, and the multi-level memory cell stores 2-bit data by a combination of the first and second cell pages. . A plurality of such first cell pages are collected to form a physical page as a write unit, and similarly, a plurality of second cell pages are also collected to form a physical page as a write unit. In this embodiment, both physical pages have the same capacity.

  A procedure for writing 2-bit data in the memory cell as described above will be described with reference to FIG. The writing of 2-bit data goes through the steps of writing lower 1-bit data to the first cell page of the memory cell and then writing upper 1-bit data to the second cell page. The writing of will be described.

  The initial state of the memory cell is in a region L0 where the threshold voltage is equal to or lower than the reference voltage VR1. The area L0 is an area indicating the 2-bit data “11”, and is an area indicating that both the first and second cell pages store the data “1”. However, in the initial state, the memory cell is not handled as storing data “11”, and is treated as a memory cell in which no data is written.

  Here, when data “1” is written in the first cell page of the memory cell, the threshold voltage of the memory cell is changed to an area where the lower 1 bit indicates “1”. The regions L0 and L3 indicate that the lower 1 bit is “1”. However, since the region L0 has a threshold voltage in the initial state of the memory cell, the data writing is finished without changing the region. Subsequently, when data “0” is written to the second cell page, data “1” is written to the second cell page if the threshold voltage remains in the region L0. It is necessary to change the threshold voltage to the region L3 where the data of “0” indicates “0”. Therefore, the threshold voltage of the memory cell is changed to the region L3 indicating that the data of the first cell page is “1” and the data of the second cell page is “0”.

  In addition, when data “0” is written in the first cell page, the region L0 in the initial state indicates that “1” is written in the first cell page. Therefore, the region L1 in which the lower 1 bit indicates “0”. Until the threshold voltage of the memory cell is changed, data writing to the first cell page is completed. Subsequently, when “0” is written in the second cell page, the data “1” is written in the second cell page if the threshold voltage remains in the region L1. The threshold voltage of the memory cell is changed to the region L2 indicating the data “0” and the second cell page also indicating the data “0”, and the writing of the data “0” to the second cell page is completed.

  When 2-bit data is written according to the above procedure, if the power supply is interrupted while data is being written to the second cell page, there is a possibility that both the first cell page and the second cell page will be destroyed. is there. For example, if the power supply is cut off during the change of the threshold voltage from the region L0 to the region L3 and remains in the region L1, the data of the first cell page indicated by the lower 1 bit becomes “0”. The data of the first cell page changes. Furthermore, the data in the second cell page is not “0” but “1”, and is not correct data.

  In the above description, writing data using only the first cell page corresponds to writing to a conventional binary memory in which 1-bit data is written to one memory cell. This is called writing. In addition, since the writing of data using the second cell page in addition to the first cell page is writing to a multi-level memory in which 2-bit data is written to one memory cell, in the following description, the multi-level mode is used. This is called writing.

[Relationship between data write mode and physical page]
As described above, each memory cell of the multilevel flash memory can store the data of the first cell page and the second cell page. However, when data is written in this embodiment, the above-described binary mode is used. Write and multi-value mode write are selectively used.

  In binary mode writing, since 1-bit data is written to one memory cell, only one writing is required for one memory cell. For example, only the areas L0 and L1 shown in FIG. 6 are used, and each area is associated with a 1-bit value of “0” or “1” to indicate the data of the first cell page. It can be used like a conventional binary flash memory. As described above, since a combination of regions having a high writing speed is normally used, binary mode writing is performed using a combination of regions L0 and L1 in this embodiment.

  Next, since data of either the first cell page or the second cell page is written in each physical page, a method for determining the sharing will be described with reference to FIGS. 3 and 7. FIG. Data is written to the flash memory in units of physical pages. When it is determined that one physical page is a physical page to which data of the first or second cell page is written, all the memory cells corresponding to the physical page have data of either the first or second cell page. Written. As described above, FIG. 3 shows physical pages PP0 to PP127 existing in one physical block. The physical page PP0 is connected to the physical page PP4 by a broken line. For example, there is one physical page PP0 in which data of the first cell page is written and one physical page PP4 in which data of the second cell page is written. As a group, the same memory area, that is, the memory cell is used.

  FIG. 7 shows such a physical page grouping. The column in charge of the first cell page shows the number of the physical page to which the data of the first cell page is written, and the column in charge of the second cell page shows the number of the physical page in which the data of the second cell page is written. It is shown. Note that n in the figure is an integer satisfying the inequality 0 ≦ n ≦ 29. In FIG. 7, adjacent physical pages form one set and use the same memory area. Here, the physical pages PP0 and PP4, PP1 and PP5, PP122 and PP126 are grouped.

  FIG. 8A shows the state of the physical block after performing binary mode writing. The physical block of FIG. 8A has 128 physical pages from PP0 to PP127, but all the physical pages that store the data of the first cell page are hatched and data is written. Show.

  On the other hand, FIG. 8B shows the state of the physical block after the multi-value mode write is performed. All of the physical pages that store the data of the second cell page are also shaded to indicate that the data has been written. In the present embodiment, data indicating a logical page of data written in each physical page is also stored in the physical page. In data writing in binary mode writing and multi-value mode writing, physical pages are used in the order of physical page numbers.

[Data writing procedure]
In the following, a procedure of processing when data is written to the flash memory 120 will be described, and binary mode aggregation and multi-value mode aggregation performed in the procedure will be described. First, FIG. 9 is a flow showing an operation of the nonvolatile memory device 100 when the access device 200 transmits an initialization command to the nonvolatile memory device 100.

  The initialization command is transmitted when the access device 200 is turned on or when the nonvolatile storage device 100 is installed. When the nonvolatile memory device 100 receives the initialization command, the memory controller 110 erases internal memories such as the logical-physical conversion table 112 and the empty block management table 113, and initializes hardware such as connection confirmation of the nonvolatile memory 120. Processing is performed (step 101). Thereafter, the read / write control unit 114 acquires address management information and the like stored in the management data storage area 121 of the nonvolatile memory 120 (step 102), and based on the acquired information, the logical-physical conversion table 112 and the empty block are acquired. The management table 113 is created and the initialization process of the nonvolatile storage device 100 is completed (step 103).

  Next, the operation of the nonvolatile storage device 100 when the access device 200 transmits a write command and write data to the nonvolatile storage device 100 will be described with reference to FIG. The host interface 111 of the memory controller 110 acquires a logical address for starting writing specified by the access device 200 (step 201), and notifies the read / write control unit 114 of the logical address.

  The read / write control unit 114 calculates a logical block (block unit, that is, 256 kB unit) that starts writing from a logical address (sector unit, that is, 512B unit) that starts writing, and performs logical-physical conversion as described below. Using the table 112, a physical block corresponding to a logical block to start writing is determined.

  When the physical block corresponding to the logical block to start writing is registered in the writing intermediate block of the logical-physical conversion table 112, the read / write control unit 114 sets this physical block as a writing physical block. If a physical block is not registered as a writing-in-progress block, an empty block is acquired using the empty block management table 113, and if the empty block has not been deleted, the data of the empty block is deleted (step 202). . Subsequently, the acquired physical block is registered as a writing intermediate block and determined as a writing physical block.

  Next, the read / write control unit 114 writes the data from the access device 200 into the write physical block by binary mode writing (step 203). Further, the read / write control unit 114 confirms whether there is unwritten data, and determines whether writing of all data is completed (step 204). If all data is written and there is no unwritten data, the data writing is terminated.

  If unwritten data remains, it is checked whether data has been written to all physical pages of the write physical block (step 205). If an unwritten physical page remains in the writing physical block, the process returns to step 203 to write unwritten data.

  When data is written to all physical pages of the physical block for writing, the area where the written data is stored is determined based on the logical block number based on the number of the logical block corresponding to the physical block, and aggregation processing is performed. Is determined (step 206). The area in which data is stored is either an area in which file system information is recorded or an area in which user data is recorded.

  In this embodiment, if it is data of the logical block LB0, it is determined that the FAT file system information, which is important data, is recorded, and binary mode aggregation is performed (step 207). If it is any other logical block, it is determined that the user data is recorded, and multi-value mode aggregation is performed (step 208).

  After each such aggregation process, the write completion block and write block that are the aggregation source are updated from “in use” to “empty” in the free block management table 113, and the physical block of the aggregation destination is changed from “free”. Updated to “In Use”. In the logical-physical conversion table 112, the physical block of the aggregation destination is assigned to the logical block of the table 112A instead of the write completion block of the aggregation source. In the table 112B in which the aggregation-source writing physical block is registered, the registration of the corresponding logical block is also canceled together with the physical block.

  The aggregation processing according to the present embodiment is processing for collecting data written in two physical blocks having the same logical address into another physical block. In the binary mode aggregation in step 207, data of two physical blocks in which data is written by binary mode writing is aggregated by binary mode writing. In the multilevel mode aggregation of step 208, data of the physical block in which data is written by the multilevel mode write and the physical block in which data is written by the binary mode write are aggregated by the multilevel mode write.

  When the above aggregation process is completed, the process proceeds to step 209 in FIG. Here, it is stored in the logical-physical conversion table 112, the free block management table 113, and the management data storage area 121 in order to record that the allocation of the physical block to the logical block has been changed by the aggregation processing in step 207 or 208. The address management information being updated is updated, and the data of the write completion block and write block of the aggregation source are erased (step 209). Thereafter, the process returns to step 202 and is repeated until all data is written.

  Next, a binary mode aggregation method will be described with reference to FIG. The physical block PB1 is a write completion block, and data is written in binary mode writing to all physical pages storing data of the first cell page. Each physical page in which data is written corresponds to 64 logical pages LP0 to LP63.

  Data of the same logical block as that of the physical block PB1 is written in binary mode writing in all the physical pages in which the data of the first cell page of the writing physical block PB2 is written. Here, a part of the logical page appearing in the physical block PB1 is updated to new data in the physical block PB2.

  If data of the same logical page as the physical block PB1 is written in the physical block PB2, the data of the physical block PB1 is old data, and new data corresponding to the logical page is written in the physical block PB2. The data updated in this way and the data originally written in the physical block PB1 but not updated in the physical block PB2 are collected in another physical block PB3. That is, the latest data of each physical page is collected in the physical block PB3.

In the binary mode aggregation, the following two rules are used to determine the latest data from the data of the same logical page of the physical pages PB1 and PB2.
The data of the physical block for writing is newer than the rule 1, the writing completion block.
In rule 2, the physical block for writing has newer data with a larger physical page number.

  According to these rules, since the data of the logical pages LP0 to LP3 can be found to be the latest data written in the physical pages PP0 to PP3 of the physical block PB1, the data is transferred from the physical page PP0 of the aggregation-destination physical block PB3. Copy to PP3.

  Next, the data of LP4 and LP5 must be copied to the physical block PB3, but the data of the logical pages LP4 and LP5 is the data written to the physical pages PP122 and 123 of the physical block PB2 according to the rules shown above. Is found to be up-to-date. Therefore, the data of PP122 and 123 of physical block PB2 are copied to PP6 and 7 of PB3. As described above, the remaining latest data is also collected in the physical block PB3.

  When there is no write completion block in the binary mode aggregation, a binary mode aggregation similar to the above is performed by using a physical block in which no data is written instead of the write completion block. In this case, the data of 64 logical pages of the physical block for writing is aggregated into 64 physical pages of the physical block of the aggregation destination. In the binary mode aggregation, since 64 physical pages can be used for the physical block of the aggregation destination, the physical block of the aggregation destination becomes a write completion block in this binary mode aggregation.

  Next, the multi-value mode aggregation method will be described with reference to FIG. The physical block PB4 is a write completion block, and data is written to all physical pages by multi-value mode writing. Each physical page in which data is written corresponds to logical pages LP0 to LP127.

  Data of the same logical address as that of the physical block PB4 is written in binary mode writing in all physical pages in the data physical block PB5 to which data of the first cell page can be written. Here, a part of the logical page held in the physical block PB4 is updated to new data in the physical block PB5.

  Multi-level mode aggregation also means that the latest data out of the data of the write completion block PB4 and the write block PB5 is collected in the physical block PB6, so that the latest data is determined according to the two rules shown in the binary mode aggregation. . According to this, since the data of the logical pages LP0 to LP3 is known to be the latest data of the physical pages PP0 to PP3 of the physical block PB4, the data is copied to the physical pages PP0 to PP3 of the physical block PB6 of the aggregation destination. .

  Next, the data of the logical page LP4 is copied to the physical block PB6. Since rules 1 and 2 indicate that the data of logical page LP4 is the latest data written in PP0 of physical block PB5, the data is copied to physical page PP4 of physical block PB6. As described above, the remaining latest data is also collected in the physical block PB6.

  Since the physical block PB5 of this embodiment handles 64 logical pages at the maximum, 64 physical pages of the 128 physical pages of PB4 are rewritten with new data.

  If there is no write completion block in the multi-value mode aggregation, the same multi-value mode aggregation is performed by using a physical block in which no data is written instead of the write completion block. In this case, the data of 64 logical pages of the physical block for writing is aggregated into 64 physical pages of the physical block of the aggregation destination. The initial value is written in the remaining 64 physical pages instead of data, and the aggregation process is completed. If the multi-value mode aggregation is further performed between the aggregation destination physical block and the write physical block having the data of another logical page, the aggregation destination physical block becomes a write completion block.

  In this embodiment, when writing data from the access device to the nonvolatile memory 120, binary mode writing is first performed. At this time, since 1-bit data is always written to a memory cell having no written data, the written data is not destroyed by power interruption during writing. In addition, the subsequent writing in the aggregation process is a process of copying the data already written in the physical block to another physical block, and is not erased in the middle of copying. Previously written data is not destroyed.

  In addition, even if the power shutoff occurs during the aggregation process of step 207 and step 208, the logical-physical conversion table 112, the free block management table 113, the address management information, etc. are updated when the power shutoff occurs. Absent. Therefore, the address management information, the logical / physical conversion table 112, and the free block management table 113 that are read from the management data storage area 121 in the process of step 102 in the initialization after the power recovery are those before the aggregation process. This is because the physical block of the aggregation destination remains “free”, and the data of the aggregation source written before the aggregation processing is not destroyed. Therefore, the logical-physical conversion table 112 and the empty block management table 113 before the aggregation processing are not destroyed. This shows that the same processing as before the power shutdown can be performed again using the address management information and the like.

  Although the embodiment of the present invention has been described above, the present invention is not limited to this embodiment. Modifications can be made without departing from the spirit of the present invention. For example, the following cases are also included in the present invention.

  (1) As the nonvolatile memory 120 of this embodiment, a NAND flash memory using a memory cell capable of recording quaternary data is used. However, not only quaternary data but also multi-value data recording is possible. Even a nonvolatile memory using various memory cells can realize the same configuration as the present invention and can obtain the same effect.

  (2) In this embodiment, whether “binary mode aggregation” or “multilevel mode aggregation” is performed depends on whether the file system management information is stored or the user data is stored. Although an example of determination is shown, the determination is not limited to this, and an arbitrary determination criterion may be used. For example, the data storage area 122 may include a normal area where a user can freely read and write, and a protected area where data can be read and written only after an authentication process. At this time, the normal area is “multi-value mode aggregation”, the authentication area is “binary mode aggregation”, or the opposite normal area is “binary mode aggregation”, and the authentication area is “multi-value mode aggregation”. Both aggregations may be properly used according to the determination criterion, and “multi-value mode aggregation” may be always performed regardless of the region.

  (3) In the present embodiment, an example in which data from the access device 200 is always written in two stages of binary mode writing and aggregation processing has been described. However, an area to be written in two stages is a partial area of the nonvolatile memory. You may limit to.

  (4) In this embodiment, in the binary mode writing, 1-bit data is written only in the first cell page, but it may be written only in the second cell page. In order to improve the writing speed, it is desirable to write only to the page having the fastest average writing speed among the pages sharing the memory cell.

  (5) In this embodiment, the logical-physical conversion table 112 and the empty block management table 113 are generated with the block which is the minimum unit of data erasure as a unit, and the write completion block and the write intermediate block are composed of one block. However, the table, the write completion block, the write block, and the like may be configured in units of super blocks including a plurality of blocks. At this time, since the number of super blocks to be managed is smaller than the number of blocks, the size of the logical-physical conversion table 112 and the empty block management table 113 can be reduced, and cost reduction per unit data amount can be expected.

  (6) When there is no write completion block in the binary and multi-value mode aggregation, a physical block in which only the initial value is written and no data is written is used instead of the write completion block. However, even if an actual physical block is not used, the same aggregation can be performed if the initial value is written in the aggregation-destination physical block as necessary.

  The present invention can be applied to an information recording medium that is required for a large capacity and high reliability used in electronic devices such as digital AV devices, mobile phone terminals, and personal computers. In particular, the present invention can be applied to a multi-value flash memory having a high recording density, and is more effective in a semiconductor memory card using a flash memory that is becoming increasingly multi-valued. Therefore, it is suitable for a nonvolatile memory device that requires low cost. It is.

It is a block diagram which shows the structure of the non-volatile storage system in embodiment of this invention. It is a figure which shows the structure of the non-volatile memory in embodiment of this invention. It is a figure which shows the structure of the physical block in embodiment of this invention. It is a figure which shows the structure of the logical-physical conversion table in embodiment of this invention. It is a figure which shows the structure of the empty block management table in embodiment of this invention. It is a figure which shows distribution of the threshold voltage of the memory cell in embodiment of this invention. It is a table | surface which shows the combination of the physical page which takes charge of the 1st cell page and 2nd cell page in embodiment of this invention. It is a figure which shows the state of the physical block for writing after binary mode writing in embodiment of this invention. It is a figure which shows the state of the physical block for writing after multi-value mode writing in embodiment of this invention. It is a flowchart which shows the operation | movement after the initialization command reception of the non-volatile memory device in embodiment of this invention. It is a flowchart which shows the operation | movement after reception of the write command of the non-volatile memory device in embodiment of this invention. It is a figure which shows the state of the physical block before and behind binary mode aggregation in embodiment of this invention. It is a figure which shows the state of the physical block before and behind multi-value mode aggregation in embodiment of this invention. It is a figure which shows distribution of the threshold voltage of the memory cell in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Nonvolatile memory device 110 Memory controller 111 Host interface 112 Logical-physical conversion table 113 Empty block management table 114 Read / write control part 120 Nonvolatile memory 121 Management data storage area 122 Data storage area 200 Access device

Claims (28)

A plurality of memory cells having a threshold voltage region of M (M> 3, M is an integer), comprising a plurality of physical pages that are data write units composed of the plurality of memory cells, and is a data erase unit A non-volatile memory including a plurality of physical blocks,
The non-volatile memory according to any one of binary mode writing in which data is written using two threshold voltage regions out of the M threshold voltage regions and multi-value mode writing in which data is written using M threshold voltage regions And a data controller for writing data to and a memory controller for reading data from the nonvolatile memory,
The physical block of the nonvolatile memory is
A write completion block in which data is written to all of the plurality of physical pages corresponding to a logical address designated by an access device external to the nonvolatile storage device;
A write block in which data corresponding to an address designated by the access device is written;
Including an empty block in which data is erased,
The memory controller is
Data is always written to the writing block by the binary mode writing,
When data is written to all physical pages of the write block, the data of the write complete block and the write block having the same logical address are copied to the empty block by binary mode write or multi-value mode write. A method for writing data in a nonvolatile storage device that performs aggregation processing.   When the memory controller copies the data of the write completion block and the write block to the empty block by binary mode write or multi-value mode write, the write completion block having the same logical address as the write block If not, the data writing method of the nonvolatile memory device according to claim 1, wherein an empty block in which no data is written is used as the writing completion block. The memory controller is
A first table relating a logical address obtained from an address designated by the access device and a physical address indicating the write completion block; and a second table relating the logical address and a physical address indicating the write block. The data writing method of the non-volatile memory device according to claim 1, further comprising a logical-physical conversion table having: The memory controller is for copying the latest data for each logical address unit corresponding to the physical page in the aggregation process,
4. The nonvolatile memory according to claim 1, wherein whether to copy by the binary mode writing or to copy by the multi-value mode writing is determined based on a logical address designated by the access device. 5. Device data writing method. The nonvolatile memory has a normal area where data can be read and written arbitrarily by accessing from the access device, and an authentication area where data can be read and written only when access from the access device is authenticated. And
The data writing method of the nonvolatile memory device according to claim 1, wherein the aggregation process in the authentication area is performed by the multi-value mode writing.   6. The nonvolatile memory device according to claim 1, wherein two threshold voltage regions used in the binary mode writing are selected from two adjacent threshold voltage values among all threshold voltage regions. Data writing method. The nonvolatile memory has a plurality of super blocks composed of a plurality of physical blocks,
7. The method of writing data in a nonvolatile memory device according to claim 1, wherein the write completion block, the write block, and the empty block are in units of the super block. A plurality of memory cells having a threshold voltage region of M (M> 3, M is an integer), comprising a plurality of physical pages that are data write units composed of the plurality of memory cells, and is a data erase unit A non-volatile memory including a plurality of physical blocks,
The non-volatile memory according to any one of binary mode writing in which data is written using two threshold voltage regions out of the M threshold voltage regions and multi-value mode writing in which data is written using M threshold voltage regions A non-volatile storage device comprising: a memory controller that writes data to and reads data from the non-volatile memory;
The physical block of the nonvolatile memory is
A write completion block in which data is written to all of the plurality of physical pages corresponding to a logical address designated by an access device external to the nonvolatile storage device;
A write block in which data corresponding to an address designated by the access device is written;
Including an empty block in which data is erased,
The memory controller is
Data is always written to the writing block by the binary mode writing,
When data is written to all physical pages of the write block, the data of the write complete block and the write block having the same logical address are copied to the empty block by binary mode write or multi-value mode write. A non-volatile storage device that performs aggregation processing.   When the memory controller copies the data of the write completion block and the write block to the empty block by binary mode write or multi-value mode write, the write completion block having the same logical address as the write block If not, the non-volatile memory device according to claim 8, wherein an empty block in which no data is written is used as the write completion block. The memory controller is
A first table relating a logical address obtained from an address designated by the access device and a physical address indicating the write completion block; and a second table relating the logical address and a physical address indicating the write block. The nonvolatile memory device according to claim 8, further comprising a logical-physical conversion table including: The memory controller is for copying the latest data for each logical address unit corresponding to the physical page in the aggregation process,
11. The non-volatile memory according to claim 8, wherein whether to copy by the binary mode writing or to copy by the multi-value mode writing is determined based on a logical address designated by the access device. apparatus. The nonvolatile memory has a normal area where data can be read and written arbitrarily by accessing from the access device, and an authentication area where data can be read and written only when access from the access device is authenticated. And
The nonvolatile storage device according to claim 8, wherein the aggregation processing in the authentication area is performed by the multi-value mode writing.   13. The nonvolatile memory device according to claim 8, wherein two threshold voltage regions used in the binary mode writing are selected from two adjacent threshold voltage values among all threshold voltage regions. . The nonvolatile memory has a plurality of super blocks composed of a plurality of physical blocks,
The non-volatile memory device according to claim 8, wherein the write completion block, the write block, and the empty block are units of the super block. A plurality of memory cells having a threshold voltage region of M (M> 3, M is an integer), comprising a plurality of physical pages that are data write units composed of the plurality of memory cells, and is a data erase unit A non-volatile memory comprising a plurality of physical blocks,
The non-volatile memory according to any one of binary mode writing in which data is written using two threshold voltage regions out of the M threshold voltage regions and multi-value mode writing in which data is written using M threshold voltage regions A memory controller that writes data to and reads data from a nonvolatile memory;
An access device that instructs the controller to write and read data to and from the nonvolatile memory;
The physical block of the nonvolatile memory is
A write completion block in which data is written to all of the plurality of physical pages corresponding to a logical address designated by an access device external to the nonvolatile storage device;
A write block in which data corresponding to an address designated by the access device is written;
Including an empty block in which data is erased,
The memory controller is
Data is always written to the writing block by the binary mode writing,
When data is written to all physical pages of the write block, the data of the write complete block and the write block having the same logical address are copied to the empty block by binary mode write or multi-value mode write. A non-volatile storage system that performs aggregation processing.   When the memory controller copies the data of the write completion block and the write block to the empty block by binary mode write or multi-value mode write, the write completion block having the same logical address as the write block If not, the non-volatile storage system according to claim 15, wherein an empty block in which no data is written is used as the write completion block. The memory controller is
A first table relating a logical address obtained from an address designated by the access device and a physical address indicating the write completion block; and a second table relating the logical address and a physical address indicating the write block. The nonvolatile storage system according to claim 15, further comprising a logical-physical conversion table having: The memory controller is for copying the latest data for each logical address unit corresponding to the physical page in the aggregation process,
18. The nonvolatile memory according to claim 15, wherein whether to copy by the binary mode writing or the multi-value mode writing is determined based on a logical address designated by the access device. 18. system. The nonvolatile memory has a normal area where data can be read and written arbitrarily by accessing from the access device, and an authentication area where data can be read and written only when access from the access device is authenticated. And
The non-volatile storage system according to claim 15, wherein the aggregation process in the authentication area is performed by the multi-value mode writing.   20. The nonvolatile memory system according to claim 15, wherein two threshold voltage regions used in the binary mode writing are selected from two adjacent threshold voltage values among all threshold voltage regions. . The nonvolatile memory has a plurality of super blocks composed of a plurality of physical blocks,
The nonvolatile storage system according to any one of claims 15 to 20, wherein the write completion block, the write block, and the empty block are composed of units of the super block. A plurality of memory cells having a threshold voltage region of M (M> 3, M is an integer), comprising a plurality of physical pages that are data write units composed of the plurality of memory cells, and is a data erase unit Is a physical block
A write completion block in which data is written to all of the plurality of physical pages corresponding to a logical address designated by an access device external to the nonvolatile storage device;
A write block in which data corresponding to an address designated by the access device is written;
Binary mode writing in which data is written using two threshold voltage regions out of the M threshold voltage regions, and M pieces of non-volatile memory including an empty block in which data is erased A memory controller that writes data to the nonvolatile memory by any one of multi-value mode writing that writes data using the threshold voltage region, and reads data from the nonvolatile memory,
Data is always written to the writing block by the binary mode writing,
When data is written to all physical pages of the write block, the data of the write complete block and the write block having the same logical address are copied to the empty block by binary mode write or multi-value mode write. A memory controller that performs aggregation processing.   When copying the data in the write completion block and the write block to the empty block by binary mode write or multi-value mode write, if there is no write complete block having the same logical address as the write block, The memory controller according to claim 22, wherein an empty block that has not been written is used as the write completion block.   A first table relating a logical address obtained from an address designated by the access device and a physical address indicating the write completion block; and a second table relating the logical address and a physical address indicating the write block. 24. The memory controller according to claim 22, further comprising a logical-physical conversion table having: In the aggregation process, the latest data is copied for each logical address unit corresponding to the physical page,
The memory controller according to any one of claims 22 to 24, wherein whether to copy by the binary mode writing or the multi-value mode writing is determined based on a logical address designated by the access device. The nonvolatile memory has a normal area where data can be read and written arbitrarily by accessing from the access device, and an authentication area where data can be read and written only when access from the access device is authenticated. And
26. The memory controller according to claim 22, wherein the aggregation process in the authentication area is performed by the multi-value mode writing.   27. The memory controller according to claim 22, wherein two threshold voltage regions used in the binary mode writing are selected from two adjacent threshold voltage values among all threshold voltage regions. The nonvolatile memory has a plurality of super blocks composed of a plurality of physical blocks,
The memory controller according to any one of claims 22 to 27, wherein the write completion block, the write block, and the empty block are composed of units of the super block.

Images