JP2001006374A - Semiconductor memory and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve convenience of a device by realizing a flash memory and the like capable of being selectively operated in a binary mode or a quaternary mode, performing high speed access and reducing chip size is reduced thereby increasing the operation speed of a flash file system and the like including the memory. SOLUTION: In the flash memory FM and the like including in the flash file system FF and the like, a two layer gate structure type memory cell is operated selectively in a binary mode or a multivalue mode based on a command, its storage area is made selectively for a binary area or a multi-level area, for example, in a sector unit, that is, a word line unit, while a binary/ multi-value control table VT showing whether a storage area is allotted to the binary area or the multivalue area is provided in the flash file system FF and the like. Further, the binary area is used as a buffer area at the time of writing or reading the data for the multivalue area, and a data compression/ defrosting function is provided to a flash memory FM and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a system, for example, a flash memory and a flash file system using the flash memory as a basic component, and a technique particularly effective when used for speeding up and improving system flexibility. About.

[0002]

2. Description of the Related Art There is a so-called two-layer gate type memory cell having a control gate and a floating gate. In addition, there is a flash memory having a memory array in which two-layer gate structure type memory cells are arranged in a lattice as a basic component, and there is a flash file system including a predetermined number of such flash memories. In a general flash memory, a two-layer gate structure type memory cell constituting a memory array operates in a so-called binary mode,
Data of logic "0" or "1" is selectively held depending on whether the threshold voltage is lower or higher than a predetermined value.

On the other hand, there is a multi-valued memory cell comprising a memory cell of a two-layer gate structure, for example, capable of holding two bits of stored data by switching its threshold voltage in four stages. 2. Description of the Related Art There is a multilevel flash memory having a memory array in which value memory cells are arranged in a lattice as a basic component. The multi-valued memory cell set to the quaternary mode has, for example, logic "01", "00", "10" or "11" at each stage of the threshold voltage.
Data is selectively retained.

[0004]

In a flash memory of a binary mode in which the threshold voltage of a memory cell is switched in two stages, the word line selection level at the time of data reading is unified, and at the time of data writing. Switching of the word line potential is small. For this reason, the time required for data reading and writing operations of a normal flash memory is sufficiently shorter than that of a multilevel flash memory, and high-speed access is possible. Since the data is one bit, there is a problem that the data density of the memory array portion is reduced, the layout required area is increased, and as a result, the chip size of the flash memory is increased.

On the other hand, in a multilevel flash memory in a quaternary mode in which the threshold voltage of a memory cell is switched in, for example, four stages, the word line selection level at the time of data reading is three.
At this stage, the number of switching of the word line potential at the time of writing data also increases. For this reason, the time required for data read and write operations of the multi-level flash memory is longer than that of a normal flash memory, and there is a problem that the access time is slow.
Since the bit data is retained, the data density of the memory array section is increased, and the required layout area is reduced.

An object of the present invention is to provide a flash memory or the like which can be selectively operated in a binary or multi-level mode as needed. Another object of the present invention is to provide a flash memory or the like which can be accessed at high speed and has a reduced chip size. A further object of the present invention is to increase the speed of a flash file system or the like including a flash memory, and to enhance its convenience.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a flash memory or the like included in a system such as a flash file system,
The two-layer gate structure type memory cells constituting the memory array are selectively operated in a binary mode or a multilevel mode such as a quaternary mode according to a command. In addition, the storage area is, for example, a binary area that selectively operates in a binary mode or a multi-level area that operates in a multi-level mode in units of word lines. A binary / multi-value management table is provided which indicates whether the region is assigned to a region or a multi-value region.

Further, a storage area allocated as a binary area, such as a flash memory, is used as a buffer area for writing or reading data to or from a multi-value area, and two memories of a binary area are used in a flash memory or the like. A data compression function for reading data written in a cell and writing it to one memory cell in a multi-value area, and a data compression function for reading data written in one memory cell in a multi-value area It has a data decompression function for writing to cells.

According to the above means, it is possible to realize, on the same chip, a binary region having a relatively low data density but capable of high-speed operation and a multi-value region having a relatively low operation speed but a high data density. At the same time, these storage areas can be selectively used according to the system configuration, and the configuration ratio can be set freely. Also, by using a binary area as a buffer area and providing a flash memory or the like with a data compression function and a data decompression function between a binary area and a multi-value area, an apparent access from an access device such as a flash memory is provided. The chip size can be reduced while shortening the time. As a result, the speed of a flash file system or the like including a flash memory or the like can be increased, and its convenience can be improved.

[0011]

FIG. 1 is a block diagram showing one embodiment of a flash file system FF (system) to which the present invention is applied, and FIG. 2 explains a storage area, that is, an address area. FIG. 1 shows an address configuration diagram of an embodiment for the present invention. The outline of the configuration and operation of the flash file system FF of this embodiment and the address configuration will be described with reference to these drawings. FIG.
Although the circuit elements constituting each block are not particularly limited, a known MOSFET (Metal Oxide Semiconductor Field Effect Transistor; in this specification, a MOSFET is a generic name of an insulated gate field effect transistor) integrated circuit Is formed on one or a plurality of semiconductor substrate surfaces made of single crystal silicon or the like, respectively.

In FIG. 1, a flash file system FF of this embodiment includes a microcomputer MC,
Four flash memories FM (semiconductor storage devices) coupled to the microcomputer MC via the address bus AB and the data bus DB are basic components thereof.
Among them, the microcomputer MC includes a so-called stored program type central processing unit, and controls and controls the operation of each unit of the flash file system FF. Also, the flash memory FM has a
A memory array in which a two-layer gate structure type memory cell is arranged in a lattice is used as its basic component, and data is read or written to a specified address in response to an instruction from a microcomputer MC or the like serving as an access device.

The flash file system FF further includes an ECC (error correction code) circuit ECC coupled to the microcomputer MC via the address bus AB and the data bus DB, a standard bus interface unit BI and a write buffer WB, and various types of management. It has management tables such as a table, that is, a sector management table ST, a write count management table WT, and a binary / multi-value management table VT. Of these, the standard bus interface section BI and the write buffer WB
The standard bus BUS is connected to a standard bus interface unit of a host computer (not shown).

ECC circuit ECC is one dedicated LSI
(Large-scale integrated circuit device)
A predetermined error correction code is added when writing M data, and an error in read data is detected and corrected when reading the flash memory FM. Similarly, the standard bus interface section BI also has one dedicated LS
I, and performs interface matching between the internal bus, that is, the address bus AB and the data bus DB, and the standard bus BUS. The write buffer WB temporarily saves write data input at a high speed via the standard bus BUS.

On the other hand, the sector management table ST manages the storage area of the flash memory FM in association with the sector in word line units, and the write count management table WT manages the write count for each sector of the flash memory FM. Is monitored so as not to exceed a predetermined value. Also, 2
The value / multi-value management table VT is used to set and store whether a sector of the flash memory FM, that is, a storage area in units of word lines is assigned to a binary area or a multi-value area.

In this embodiment, the flash memory F
As shown in FIG. 2, M includes four flash memories FM0 to FM3, and the storage areas thereof are associated with sectors in units of word lines W0 to Wm of these flash memories. Also, the flash memories FM0 to FM0
The storage area of the FM3 is a binary area that operates in a binary mode or a multilevel area that operates in, for example, a quaternary mode in units of word lines or sectors, and the binary / multilevel management table VT includes It is used to indicate to which area a sector is assigned. Flash memory F
A microcomputer MC serving as an access device of M
Prior to the access, the binary / multi-value management table VT is referred to determine whether the area to be accessed is assigned to the binary area or the multi-value area. Selectively edit memory commands for FM.

As a result, in the flash file system FF of this embodiment, the storage area of the flash memory FM can be selectively used as a binary area or a multi-level area in units of sectors, that is, word lines. The convenience of the file system FF can be improved, and the system flexibility of the flash file system FF and, consequently, a computer system or the like including the flash file system FF can be improved.

The flash memory FM, that is, FM0
FM3, the specific read and write operations in the binary mode and the quaternary mode, and the specific configuration of the memory command will be described later in detail.

FIG. 3 is a block diagram of one embodiment of the flash memory FM0 included in the flash file system FF of FIG. 1, and FIG. 4 is a partial view of one embodiment of the memory array and peripheral portions. A simple circuit diagram is shown.
FIG. 5 shows the memory arrays ARYUL and A of FIG.
FIG. 6 shows a distribution characteristic diagram of an embodiment of the threshold voltage of the memory cell of the two-layer gate structure constituting RYDL.
FIG. 4 shows a bit configuration diagram of an embodiment of a memory command for the flash memory of FIG. With reference to these figures, the configuration and operation of the flash memories FM0 to FM3 constituting the flash file system FF of this embodiment will be described more specifically.

The circuit elements constituting each block in FIG. 3 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique as described above. Also, the MOSFET shown in FIG.
Are all N-channel MOSFETs. further,
In FIG. 3, the flash memories FM1 to FM3 will be described with the description of the flash memory FM0. In FIG. 4, the memory arrays ARYUL and ARYDL and the data latch D will be described.
The memory arrays ARYUR and ARYDR, the data latches DLUR and DLDR, and the sense latch SLR will be described with the description of LUL and DLDL and the sense latch SLL.

In FIG. 3, a flash memory FM0
Is not particularly limited, but the two memory mats MATU
And MATD, a read-only memory ROM serving as an indirect peripheral circuit, a write / erase determination circuit WE, and a direct peripheral control circuit P
C, power supply switching circuit POWS, address counter ADD
C, redundancy repair circuit RC and clock generation circuit CPG
And the like. Among them, the memory mat MATU on the upper side, that is, the upper side, has a pair of memory arrays ARYUL and ARYUR sharing a word line WL as its basic constituent elements, and further has a main decoder MDU, a pair of sub decoders SDUL and SDUR, and a data latch. DLUL and DLUR.

Similarly, the lower memory mat MATD on the down side, that is, the down side, has a pair of memory arrays ARYDL and ARYDR sharing a word line WL as its basic constituent elements, and further has a main decoder MDD and a pair of sub decoders SDDL and SDDR and data latch DLD
L and DLDR. Memory mats MATU and M
In the middle of the ATD, sense latches SLL and SLR are provided.

Here, the memory arrays ARYUL and ARYUR of the memory mat MATU and the memory mat M
The ATD memory arrays ARYDL and ARYDR are substantially (m + 1) / 2 word lines (see FIG. 4) arranged in parallel in the horizontal direction in FIG. 4 as representatively represented by the memory arrays ARYUL and ARYUR, respectively. 4 has two word lines WLU constituting the memory array ARYUL.
1 and WLU2 and one word line WLD3 constituting the memory array ARYDL) and n + 1 bit lines arranged in parallel in the vertical direction in the drawing (FIG. 4 shows the memory array ARYUL Is BL
U includes a bit line constituting the memory array ARYDL as a BLD). At the intersections of these word lines and bit lines, a two-layer gate structure type memory cell having a control gate and a floating gate (in FIG. 4, memory cells MC1 and MC2 constituting a memory array ARYUL and a memory array AR
And a memory cell MC3 constituting the YDL) are arranged in a grid pattern.

In this embodiment, the memory array ARY
The memory cells MC1 and MC2 forming the UL are
The memory cells MC3 constituting the memory array ARYDL included in the multivalued mode, ie, the memory cells of the quaternary mode, ie, the quaternary mode memory cells included in the memory array ARYDL. The specific operation and the like at the time of writing and reading operations will be described later in detail.

The drains of (m + 1) / 2 memory cells arranged in the same column of the memory arrays ARYUL and ARYDL are commonly coupled to the corresponding bit line BLU or BLD. Also, the memory arrays ARYUL and ARY
The control gates of the (n + 1) memory cells arranged on the same row of the DL correspond to the corresponding word lines WLU1 and WLU.
The sources of all the memory cells constituting each memory array are commonly coupled to U2 or WLD3 or the like, and are commonly coupled to the ground potential VSS.

On the other hand, memory arrays ARYUL and ARY
The word lines WLU1, WLU2, WLD3, etc. constituting the DL are connected to corresponding sub-decoders SDUL or SDUL.
DL, or alternatively, a predetermined selection level.
The bit lines BLU and BLD constituting the memory arrays ARYUL and ARYDL are respectively coupled to the corresponding unit circuit of the data latch DLUL or DLDL on the outside, and the sense latch SL on the inside.
L is connected to the corresponding unit circuit.

The data latch DLUL is connected to the memory array A
N + provided corresponding to the bit line BLU of RYUL, etc.
As shown in FIG. 4, each of the unit circuits includes one unit data latch UDLU, an input / output node of the unit data latch UDLU, and a corresponding bit of the memory array ARYUL. And a power supply voltage V
DD and corresponding bit line BL of memory array ARYUL
Two MOSFETs provided in series with U etc.
N12 and N13, and M provided between an input / output node of the unit data latch UDLU and the common IO line CIOD.
OSFET N14. The control signal DTU is commonly supplied to the gate of the MOSFET N11,
The control signal PCDU is commonly supplied to the gate of TN12. The gate of MOSFET N13 is coupled to the input / output node of unit data latch UDLU,
The corresponding control signal YGU is supplied to the gate of the FET N14.

As a result, the MOSFET N11 of each unit circuit of the data latch DLU is selectively turned on in response to the high level of the control signal DTU, and the input / output node of the unit data latch UDLU and the corresponding bit line of the memory array ARYUL. A connection state is selectively established with the BLU or the like. The MOSFETs N12 and N13 function as a precharge circuit for precharging the corresponding bit lines BLU and the like of the memory array ARYUL to a predetermined level, and the bit lines BLU corresponding to the data held in the unit data latch UDLU. And the like, and also functions as an arithmetic circuit for performing a predetermined arithmetic process based on the logical value of the remaining data. Furthermore, MOSFET N14
Are selectively turned on in response to the high level of the corresponding control signal YGU, and function as column switches for selectively connecting the input / output node of the unit data latch UDLU and the common IO line CIOD.

Similarly, the data latch DLDL includes n + 1 unit circuits provided corresponding to the bit lines BLD and the like of the memory array ARYDL. Each of these unit circuits is, as illustrated in FIG. One unit data latch UDLD, an input / output node of unit data latch UDLD, and corresponding bit line B of memory array ARYDL
And two MOSFETs N32 and N33 provided in series between the power supply voltage VDD and the corresponding bit line BLD, etc.
MOSFET N34 provided between an input / output node of unit data latch UDLD and common IO line CIOD
And The control signal DTD is commonly supplied to the gate of the MOSFET N31,
The control signal PCDD is commonly supplied to the 32 gates. The gate of the MOSFET N33 is coupled to the input / output node of the unit data latch UDLD,
The corresponding control signal YGD is supplied to the gate of TN34.

As a result, the MOSFET N31 of each unit circuit of the data latch DLD is selectively turned on in response to the high level of the control signal DTD, and the input / output node of the unit data latch UDLD and the corresponding bit line of the memory array ARYDL. A connection state is selectively established with the BLD or the like. The MOSFETs N32 and N33 function as a precharge circuit for precharging the corresponding bit line BLD or the like of the memory array ARYDL to a predetermined level, and the bit line BLD corresponding to the data held in the unit data latch UDLD. And the like, and also functions as an arithmetic circuit for performing a predetermined arithmetic process based on the logical value of the remaining data. Further, MOSFET N34
Are selectively turned on in response to the high level of the corresponding control signal YGD, and function as column switches for selectively connecting between the input / output node of the unit data latch UDLD and the common IO line CIOD.

On the other hand, the sense latch SLL is connected to the bit lines BLU and BL of the memory arrays ARYUL and ARYDL.
And n + 1 unit circuits provided corresponding to D and the like.
Each of these unit circuits includes one unit sense latch USL as illustrated in FIG. Further, a MOSFET N21 provided between the input / output node on the left side of the unit sense latch USL and the corresponding bit line BLU of the memory array ARYUL, and the power supply voltage VDD and the corresponding bit line BLU of the memory array ARYUL are provided. Two MOSFETs N22 and N provided in series
23 and a MOSFE provided between the input / output node on the left side of the unit sense latch USL and the common IO line CIOS.
And a MOSFET N provided between the input / output node on the right side of the unit sense latch USL and the corresponding bit line BLD of the memory array ARYDL.
25, two MOSFETs N26 and N27 provided in series between the power supply voltage VDD and the corresponding bit line BLD of the memory array ARYDL, an input / output node on the right side of the unit sense latch USL, and a common IO line CIO.
D.

The MOSFETs N21 and N2 of each unit circuit
The control signal TRU or TRD is commonly supplied to the gate of No. 5, and the control signal PCU or PCD is commonly supplied to the gates of the MOSFETs N22 and N26. The gates of the MOSFETs N23 and N27 are respectively coupled to the left and right input / output nodes of the unit sense latch USL.
The gate 28 has a corresponding control signal YGSU or YGSU.
SD are supplied respectively.

As a result, the MOSFETs N21 and N25 constituting each unit circuit of the sense latch SLL are selectively turned on in response to the high level of the control signal TRU or TRD, and are turned on at the left or right of the unit sense latch USL. The output node is selectively connected to the corresponding bit line BLU or BLD of the memory array ARYUL or ARYDL. Also, the MO of each unit circuit
SFETs N22 and N23 and N26 and N27
Operates as a precharge circuit for precharging the corresponding bit line BLL or BLD of the memory array ARYUL or ARYDL to a predetermined level, and also operates the bit line BLU or the data corresponding to the data held in the unit sense latch USL. It also functions as an arithmetic circuit for performing predetermined arithmetic processing based on the logical value of data remaining in the BLD or the like. Furthermore, MOSFET N2 of each unit circuit
4 and N28 are the corresponding control signals YGSU or YGS
D is selectively turned on in response to the high level of D, and acts as a column switch for selectively connecting the input / output node on the left or right side of the unit sense latch USL and the common IO line CIOS or CIOD. .

In the flash memory of this embodiment, the memory cells of the two-layer gate structure constituting each memory array of the memory mats MATU and MATD are selectively operated in the binary mode or the multilevel mode in units of sectors, that is, word lines. Mode, that is, a four-value mode.
In the embodiment, for example, the memory cell MC1 coupled to the word lines WLU1 and WLU2 of the memory array ARYUL
And MC2 are in the binary mode, and the memory array ARYD
The memory cells MC3 coupled to the L word line WLD3 operate in the quaternary mode.

When the memory cell operates in the binary mode,
The threshold voltage is, as exemplified in FIG.
A two-stage distribution is obtained with the potential VRW1 as the boundary potential. When each memory cell is in an erased state and its threshold voltage is in a region of distribution 1 lower than the boundary potential VRW1, for example, it is assumed that the memory cell holds data of logic "0". State and its threshold voltage is in the region of distribution 2 higher than the boundary potential VRW1,
It holds data of logic "1". Therefore, in the read operation of the flash memory in the binary mode, the word line corresponding to the specified sector is set to the boundary potential V
The write operation in the binary mode is performed by setting the write voltage to a selection level such as RW1. The write voltage sufficiently higher than the boundary potential VRW1 until the threshold voltage of the specified memory cell after writing reaches the area of distribution 2 is obtained. Is applied.

On the other hand, when a memory cell operates in a multilevel mode, for example, in a four-level mode, its threshold voltage is
As illustrated in FIG. 5B, the potentials VRW1 and VRW
A distribution of four steps is taken with 2 and VRW3 as boundary potentials. Each memory cell is not particularly limited, but is in an erased state, and its threshold voltage has a boundary potential VRW.
When it is in the area of distribution 1 lower than 1, for example, logic “0”
1 is held, and when the data is in the written state and its threshold voltage is in the distribution 2, distribution 3 or distribution 4 region higher than the boundary potential VRW1, the logic "00" and "10" respectively. "Or" 11 "data.

Therefore, in the read operation of the flash memory in the four-value mode, the word line corresponding to the designated sector is connected to the boundary potentials VRW1, VRW2 and VRW.
The write operation in the quaternary mode is performed by sequentially switching to the selection level 3 as shown in FIG. Is performed by applying a write voltage sufficiently higher than the boundary potential VRW1 until the voltage reaches the threshold voltage VRW1.

The boundary potential VRW in the binary mode
Although not particularly limited, 1 is set to the same potential as the boundary potential VRW1 in the quaternary mode. Further, needless to say, the distribution state illustrated in FIG. 5 is only an example, and the logical value of the data held in the memory cells in each distribution region can also be set arbitrarily.

Next, returning to FIG. 3, the flash memory FM
The outline of the indirect peripheral circuit of 0 will be described.

The control signal buffer CB is provided with a chip enable signal CEB (here, a so-called inverted signal or the like which is selectively turned to a low level when it is enabled) supplied as a start control signal from an access device such as a microcomputer MC. Of the flash memory FM0 in response to a write enable signal WEB, an output enable signal OEB, a reset control signal RESB, and a command data enable signal CDEB. An internal control signal for establishing a state is selectively formed and supplied. Further, the input / output control circuit IOC generates various internal control signals necessary for input / output control based on the internal control signal supplied from the control signal buffer CB and the serial clock signal SC supplied from the access device. Form and supply to required parts. Further, the clock generation circuit CPG generates a predetermined internal clock signal and supplies it to the ROM control system circuit ROMC, the address counter ACC, the step-down circuit VC, and the like.

On the other hand, data input / output buffers IOB0 to IOB
OB7 is a data input / output terminal IO0 from the access device.
The 8-bit write data supplied via IO7 is fetched and transmitted to the input data operation circuit IDA, and the 8-bit read data output from the corresponding main amplifiers MA0 to MA7 is fetched, and the data input / output terminals IO0 to IO0 are input. Output to the access device via IO7.

In this embodiment, the data input / output terminal I
O0 to IO7 are also used as input terminals of a memory command for the flash memory FM0. For this reason,
The data input / output buffers IOB0 to IOB7 have a function of taking in a memory command supplied from the access device via the data input / output terminals IO0 to IO7 in 8-bit units and transmitting the command to the command decoder CMD. The command decoder CMD operates according to a predetermined internal control signal supplied from the control signal buffer, and converts a memory command supplied via the data input / output buffers IOB0 to IOB7 into fixed data previously written in the read-only memory ROM. Decode to the original. Then, the operation mode of the flash memory FM0 is determined according to the decoding result, and a corresponding control signal is selectively formed and supplied to each unit.

As described above, the memory cells constituting each memory array of the flash memory FM0 operate selectively in the binary mode or the quaternary mode. ~ IO7
Is determined for each memory cycle by decoding a predetermined memory command supplied through the command decoder CMD. At this time, although the memory command is not particularly limited, as illustrated in FIG. 6, for example, the fourth bit command data CMB3 includes a binary / multi-value designation bit, and the memory cell of each memory array is
Command data CMB3 is low level, that is, logic "0".
The operation in the two-level mode is performed when the signal is turned on, and the operation in the four-value mode is performed when the signal is set to the high level, that is, the logic “1”.

As described above, the flash memory FM0 of this embodiment includes the flash memories FM1 to FM3,
Access to a specified sector, that is, a word line, is selectively executed in a binary mode or a quaternary mode. Therefore, each sector is 2 in the flash file system FF.
By providing a binary / multi-value management table VT indicating which of the value mode and the quaternary mode is assigned,
The storage area can be selectively and arbitrarily assigned in a binary mode or a quaternary mode on a word line basis, thereby increasing the system flexibility of the flash file system FF and, consequently, a computer system including the flash file system FF. Things.

The flash memory FM0 further includes, as indirect peripheral circuits, a redundancy control circuit RC and a fuse circuit FC for relieving defects, a substrate power supply circuit VRG for generating various internal voltages, a step-down circuit VC, and a power supply. Although it includes a switching circuit POWS and a power supply control circuit POWC, a ready / busy signal buffer RBB, and the like, the description of the functional blocks is omitted because the relationship with the present invention is relatively thin.

FIG. 7 shows the flash memory FM0 of FIG.
FIG. 8 shows a processing flow diagram of an embodiment at the time of a read operation in the binary mode, and FIG. 8 shows a processing flow diagram of an embodiment at the time of a write operation in the binary mode.
FIG. 9 is a processing flowchart of an embodiment of the read operation in the multi-level mode, that is, the quaternary mode, of the flash memory FM0 of FIG. 3, and FIG. FIG. 2 is an explanatory diagram of one embodiment for explaining the relationship between the word line selection level and the bit line level. Further, FIG. 11 shows a processing flow chart of an embodiment at the time of the write operation in the quaternary mode of the flash memory FM0 of FIG. Based on these figures, the binary mode and 4
A specific procedure of the operation in the value mode and its characteristics will be described.

In FIGS. 7 and 8, the memory mat M
The memory cell MC1 coupled to the word line WLU1 of the memory array ARYUL of the ATU is exemplified as a representative of the memory cell operating in the binary mode. In FIGS. 9 to 11, the word line WLD3 of the memory array ARYDL of the memory mat MATD is shown. Memory cell MC3 coupled to
It is exemplified as a representative of the memory cell operating in the value mode.

First, in FIG. 7, the flash memory F
The read operation in the binary mode of M0 is performed in step ST
71, the word line WLU of the memory array ARYUL
It is started by setting 1 to a selection level such as the boundary potential VRW1. The bit lines BLU of the designated memory array ARYUL are precharged to a high level such as 1.0 V (volts) in advance, and a pair of memory arrays A
The bit line BLD of RYDL is precharged to an intermediate level, for example, 0.5V.

Memory cell MC of memory array ARYUL
When 1 is in the erased state and holds data of logic "0", its threshold voltage is in the region of distribution 1 as shown in FIG. For this reason, the memory cell MC1
When the corresponding word line WLU1 is set to a selection level such as the boundary potential VRW1, the word line WLU1 is turned on, and the bit line B
The precharge level of about 1.0 V of the LU is discharged via the selected memory cell MC1, and is set to a low level such as 0 V, for example.

However, when the memory cell MC1 of the memory array ARYUL is in a write state and holds data of logic "1", its threshold voltage is in the area of distribution 2 in FIG. Therefore, even if the corresponding word line WLU1 is set to a selection level such as the boundary potential VRW1, the memory cell MC1 is not turned on and the bit line BL
The precharge level of U of about 1.0 V is slightly lowered by charge sharing, and is kept at a high level such as about 0.9 V.

Bit line BLU of memory array ARYUL
The low-level or high-level read signal at
In step ST72, the corresponding unit sense latch USL of the sense latch SLL is set to the operating state,
The intermediate level of the paired bit lines BLD is amplified as a reference potential, and its logical value is determined. The logical value of the bit line BLU, that is, the high level / low level (H / L) of the bit line BLU is stored as it is in the corresponding unit sense latch USL of the sense latch SLL. Then, in step ST73, the data is selectively transmitted serially to the main amplifiers MA0 to MA7 via the corresponding common IO line CIOS, amplified, and then input / output buffer IO.
The data is output from B0 to IOB7 to a microcomputer MC or the like as an access device via data input / output terminals IO0 to IO7.

On the other hand, in the write operation of the flash memory FM0 in the binary mode, as shown in FIG.
The operation is started by sequentially taking in write data serially supplied in 8-bit units from the IOB 7 via the input data operation circuit IDA and the common IO line CIOS into the unit sense latch USL of the sense latch SLL.

Unit sense latch U of sense latch SLL
The write data captured in the SL is stored in step ST8.
2, the word line WLU1 of the memory array ARYUL
Are written in parallel to the (n + 1) memory cells coupled to the word line unit. At this time, when the corresponding bit of the write data is logic “0”, for example, since the corresponding bit BLU is set to the high level, the memory cell M
Although the threshold voltage of C1 does not change, if the corresponding bit of the write data is logic "1", the corresponding bit line BLU is set to low level, so that the memory cell MC
The threshold voltage of 1 is gradually increased, and shifts to the region of distribution 2 in FIG.

Next, in the read operation in the multi-value mode, that is, in the quaternary mode, as shown in FIG. 9, first, in step ST91, the designated word line WLD3 of the memory array ARYDL is selected by the boundary potential VRW1. Start by leveling. Memory array ARY
The DL bit lines BLD and the like are pre-charged to a high level such as 1.0 V in advance, and form a pair of memory arrays AR.
The YUL bit lines BLU and the like are precharged to an intermediate level such as 0.5V.

When the selected memory cell MC3 of the memory array ARYDL is in the erased state and holds data of logic "01", its threshold voltage is in the region of distribution 1 as shown in FIG. . Therefore, the memory cell MC3
Is turned on when the word line WLD3 is set to a selection level like the boundary potential VRW1, and the bit line BLD
1.0V precharge level is selected by the selected memory cell M
Discharged via C3, and brought to a low level L as shown in FIG. This means that the word line W
The same applies to the case where LD3 is at a selection level such as the boundary potential VRW2 or VRW3, and the bit line BLD is also at the low level L.

On the other hand, when the memory cell MC3 of the memory array ARYDL is in the first to third write states and holds data of logic "00", "10" or "11", its threshold voltage is It is in the distribution 2, distribution 3 or distribution 4 region of FIG. Therefore, in the memory cell MC3, the corresponding word line WLD3 has the boundary potential VR.
Even if a selection level such as W1 is set, the bit line BLD is not turned on, and the precharge level of about 1.0 V of the bit line BLD is slightly reduced due to charge sharing.
It is kept at a high level H such as 9V.

Bit line BLD of memory array ARYDL
The low-level or high-level read signal at
In step ST92, the corresponding unit sense latch USL of the sense latch SLL is set to the operating state,
The intermediate level of the paired bit lines BLU is amplified as a reference potential, and its logical value is determined. The logic value of the bit line BLD, that is, the high level / low level (H / L) of the bit line BLD is stored and held as it is in the corresponding unit sense latch USL of the sense latch SLL.
In step ST93, the data is transferred to and held by the corresponding unit data latch UDLD on the memory array ARYDL side.

Next, in step ST94, a similar read operation is performed on the memory cell MC3 by setting the word line WLD3 to a selection level such as the boundary potential VRW2. It is amplified by the latch USL. In step ST96, the logical value of the bit line BLD is changed from the unit sense latch USL of the sense latch SLL to the unit data latch UDLU on the memory array ARYUL side.
Is transferred to and retained. Then, in step ST97, the third read operation is performed on the memory cell MC3 by setting the word line WLD3 to a selection level such as the boundary potential VRW3, and the result is obtained by the unit sense latch USL of the sense latch SLL in step ST98. After being amplified, it is held in the corresponding unit sense latch USL as it is.

At step ST99, sense latch SL
The exclusive OR of the third read result (USL) held in the L unit sense latch USL and the first read result (UDLD) held in the unit data latch UDLD is obtained, and the inverted value thereof is calculated. Same unit data latch U
Stored in DLD. The data held in the unit data latch UDLD together with the data held in the unit data latch UDLU are determined in step ST910 by the common IO line CIO.
S and CIOD are output to the main amplifiers MA0-MA
7 is output to the microcomputer MC or the like via the data input / output buffers IOB0 to IOB7 and the data input / output terminals IO0 to IO7.

When memory cell MC3 holds data of logic "00", the level of bit line BLD is such that word line WLD3 is at boundary potential VRW as shown in FIG.
At the time of the first read operation at a selection level such as 1, the level is high, but the boundary potentials VRW2 and VRW are high.
At the time of the second and third read operations at a selection level such as W3, both become low level L. Further, when the memory cell MC3 holds data of logic "10", it becomes high level H in the first and second read operations, but becomes low level L in the third read operation. Further, when the memory cell MC3 holds data of logic "11", it becomes high level H in all of the first to third read operations.

As is apparent from FIG. 10, the output logical value of the second read operation held in the unit data latch UDLU directly corresponds to the logical value of the upper bit of the data held in the memory cell MC3. Further, an exclusive OR of an output logical value (UDLD) of the first read operation held in the unit data latch UDLD and an output logical value (USL) of the third read operation held in the unit sense latch USL is performed. Correspond to the logical value of the lower bit of the data held in the memory cell MC3 by further logical inversion. Therefore, unit data latches UDLU and UDLU after the process of step ST99 in FIG.
The data held in D corresponds to the upper and lower bits of the data held in the memory cell MC3, respectively.

On the other hand, in the write operation in the multilevel mode, that is, the quaternary mode, as shown in FIG. 11, first, in step ST111, the write operation supplied from the input data operation circuit IDA via the common IO lines CIOS and CIOD is performed. The process is started by taking data into the unit data latches UDLU and UDLD of the data latches DLU and DLD. Unit data latches UDLU and UDL
The upper and lower bits of the write data captured and held in D are ORed with the non-inverted value and the inverted value in step ST112, and the result is stored in the corresponding unit sense latch USL of the sense latch SLL. Is stored.

As apparent from FIG. 10, the logical OR of the non-inverted value of the data held in unit data latch UDLU and the inverted value of the data held in unit data latch UDLD is obtained by inverting the upper bit of the data to be written to memory cell MC3. It corresponds to the inverted value of the logical product of the value and the non-inverted value of the lower bit.
In other words, the result of the logical sum at step ST112 being logic "1" means that the memory cell MC
3 indicates that the logical value of the data to be written is other than "01".
The distribution of the threshold voltage of the memory cell MC3 by the
Is selectively performed to raise the area. Needless to say, if the result of the logical sum in step ST112 is logical "0", the first write in step ST113 is not performed, and the memory cell MC3 remains in the erased state.

Thereafter, in step ST114, the logical sum of the non-inverted value of the data held in unit data latch UDLU and the non-inverted value of the data held in unit data latch UDLD is calculated. Writing for raising the threshold voltage of the cell MC3 to the region of distribution 3 is selectively performed. Also, in step ST116, the logical sum of the inverted value of the data held in unit data latch UDLU and the non-inverted value of the data held in unit data latch UDLD is calculated, and according to the result, the memory cell MC3 in step ST117 is removed. Writing for raising the threshold voltage to the region of distribution 4 is selectively performed.

As is clear from FIG. 10, step ST
The result of the OR operation between the non-inverted value of the data held in the unit data latch UDLU and the non-inverted value of the data held in the unit data latch UDLD by 114 indicates the inverted value of the upper bit and the lower bit of the data to be written to the memory cell MC3. It corresponds to the inverted value of the logical product of the memory cell MC and the inverted value.
No. 3 indicates that the logical value of the data to be written is other than "00", that is, "10" or "11". The result of the logical sum of the inverted value of the data held in the unit data latch UDLU and the non-inverted value of the data held in the unit data latch UDLD in step ST116 is as follows:
The fact that the result of the logical sum is logical "1" corresponding to the inverted value of the logical product of the non-inverted value of the upper bit and the inverted value of the lower bit of the data to be written to the memory cell MC3 means that
The logical value of the data to be written to the memory cell MC3 is “1”.
It is nothing but "0", that is, "11".

From these, the memory array ARYD
The threshold voltage of the memory cell MC3 designated as L gradually increases after receiving the writing in steps ST113, ST115 and ST117, and changes from the erased state of the distribution 1 area to the distribution 2, distribution 3 or distribution 4 area. The state is changed to the write state.

As described above, in the flash memories FM0 to FM3 of this embodiment, the access to the designated sector, that is, the word line is selectively performed in the binary mode or the quaternary mode according to the predetermined bit of the memory command.
The flash file system FF is provided with a binary / multivalue management table VT indicating whether each sector is assigned to the binary mode or the quaternary mode. As a result, a binary region having a relatively low data density but capable of high-speed operation and a multi-value region having a relatively low operation speed but a high data density can be realized on the same chip.
The storage area of the flash file system FF can be selectively allocated in units of sectors, that is, word lines, and in any combination in the binary mode or the quaternary mode,
As a result, the system flexibility of the flash file system FF and the computer system including the flash file system FF can be enhanced.

FIG. 12 is a conceptual diagram of one embodiment for explaining the data compression / decompression operation of the flash memory of FIG. FIG. 13 shows a processing flow chart of an embodiment at the time of data compression of the flash memory of FIG. 3, and FIG. 14 shows a processing flow chart of an embodiment at the time of data decompression. . A data compression / decompression function, which is another feature of the flash memory of this embodiment, and its effects will be described with reference to these drawings. FIG.
2 to 14, the flash memories FM1 to FM3 will be described with the description of the flash memory FM0. The memory cell MC1 of the memory array ARYUL
And MC2 are representative examples of the memory cells operating in the binary mode, and the memory cells MC3 of the memory array ARYDL are
Are typical examples of the memory cells operating in the multi-level mode, that is, the quaternary mode.

In this application example, the flash memory F
M0 exchanges data with a microcomputer MC or the like as an access device in a binary mode. For this reason, the flash memory FM0 first writes write data supplied from the microcomputer MC or the like in the binary mode to the memory cells MC1 and MC2, reads it out, and stores it in the memory cell MC3 in the multilevel mode, that is, the quaternary mode. Data compression function to be written by microcomputer and microcomputer M
Prior to the output of the read data to C or the like, the data held in the memory cell MC3 is read in a quaternary mode,
A data decompression function for writing to the memory cells MC1 and MC2 in the binary mode.

At the time of the writing operation, the microcomputer M
The write data of the logical values “00”, “01”, “10” and “11” given to the flash memory FM0 from C or the like are stored in the two memory cells MC1 and MC2 as they are, as illustrated in FIG. Written in binary mode with logical values. These write data are stored in the memory cell MC1 at a later time, as indicated by the solid line in FIG.
And MC2, and is subjected to data compression and written into one memory cell MC3.

At this time, in the flash memory FM0,
As shown in FIG. 13, first, in step ST131, the data held in the memory cell MC1 is read in the binary mode, and is amplified by the corresponding unit sense latch USL of the sense latch SLL. The data is transferred to the corresponding unit data latch UDLU of the DLU. Also, in step ST133, the data held in the memory cell MC2 is read in the binary mode in the same manner and amplified by the corresponding unit sense latch USL of the sense latch SLL.
At 34, the data is transferred to the corresponding unit data latch UDLD of the data latch DLD. Then, step ST1
By 35, the data held in the unit data latches UDLU and UDLD are subjected to data compression processing in accordance with FIG. 12, and the result is written to the corresponding memory cell MC3 in the multi-level mode, that is, the quaternary mode.

On the other hand, when there is an instruction to read data from an access device such as the microcomputer MC, the flash memory FM0 reads the held data from the memory cell MC3 of the corresponding storage area in the multi-value mode, that is, the quaternary mode. . These read data are subjected to data decompression processing and written in the corresponding two memory cells MC1 and MC2 in the binary mode, as shown by the dotted lines in FIG. 12, and then these memory cells MC1 and M2 are renewed.
The data is read from C2 in a binary mode and output to an access device such as a microcomputer MC.

At the time of data decompression, first, in the flash memory FM0, as shown in FIG.
As a result, the data held in the memory cell MC3 is read in the quaternary mode, subjected to the data decompression process according to FIG. 12, and then loaded into the corresponding unit data latches UDLU and UDLD of the data latches DLU and DLD. Among them, the data held in the unit data latch UDLU is
After being transferred to the corresponding unit sense latch USL of the sense latch SLL in step ST142, the data is written to the corresponding memory cell MC1 in the binary mode in step ST143. Also, the unit data latch UDLD
Is transferred to the corresponding unit sense latch USL in step ST144, and is written in the corresponding memory cell MC2 in the binary mode in step ST145.

As is well known, the time required for data read and write operations in the binary mode is about one third to one fifth of the time required for data read and write operations in the four value mode. To be short. However, when all the memory cells are operated in the binary mode,
The data density in the memory array section is halved compared to that in the quaternary mode, and the required layout area of the memory array section is correspondingly increased.
Chip size increases.

As described above, the flash memory FM0 has a data compression / decompression function, and the memory cells MC1 and MC2 operating in the binary mode are used as buffers, so that the access from the access device such as the microcomputer MC can be performed for two times. By accepting in the value mode, the substantial access time of the flash memory FM0 viewed from the microcomputer MC or the like can be reduced, and for example,
By setting the area of the memory cells MC1 and MC2 operating in the binary mode to only one sector and all the other storage areas to be in the quaternary mode, the data density of the memory array section is approximately doubled, and the layout required area is increased. Can be reduced. As a result, the chip size can be reduced while operating the flash memory at high speed.

The operation and effect obtained from the above embodiment are as follows. (1) In a semiconductor memory device such as a flash memory included in a system such as a flash file system, a two-layer gate structure type memory cell forming a memory array is
The storage area is selectively operated in a binary mode or a multilevel mode such as a quaternary mode in accordance with a command, and a storage area is selectively operated in a binary mode or a multilevel mode in units of, for example, word lines. 2 indicates whether a storage area in units of word lines, such as a flash memory, is allocated to a binary area or a multi-level area in a flash file system or the like.
By providing a value / multi-value management table, a binary region having a relatively low layout density but capable of high-speed operation and a multi-value region having a relatively low operation speed but high layout density can be realized on the same chip. Is obtained.

(2) According to the above item (1), a storage area of a flash memory or the like and a flash file system or the like containing the same can be selectively used according to the system configuration, and the configuration ratio can be set freely. The effect that it can be obtained is obtained.

(3) In the above items (1) and (2), the binary area of the flash memory or the like is used as a buffer area at the time of writing or reading data to or from the multi-level area. A data compression function for reading data written to, for example, two memory cells in a binary area, and writing data to one memory cell in a multi-level area, and reading data written to one memory cell in a multi-level area By providing a data decompression function for writing data to, for example, two memory cells in a binary area, it is possible to reduce the chip size while reducing the apparent access time from the side of an access device such as a flash memory. Is obtained. (4) According to the above items (1) to (3), it is possible to obtain the effect that the convenience of the flash memory and the like and the flash file system including the flash memory and the like can be improved while the speed is increased.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the flash file system FF
Can have an arbitrary number of flash memories FM, and the block configuration and bus configuration thereof can take various embodiments. In FIG. 2, the address configuration of the flash file system FF is only an example, and the correspondence and combination with the word line can be set arbitrarily.
In addition, the unit of the storage area allocated as the binary or multi-level area can be arbitrarily set, such as a plurality of sectors, that is, word lines.

In FIG. 3, a flash memory represented by flash memory FM0 can have an arbitrary number of memory mats, and the array configuration of each memory mat and the configuration of a direct peripheral circuit are also arbitrary. The number of data input / output terminals provided in the flash memory can be set arbitrarily, and the block configuration, the names and combinations of the start control signals, the connection form, and the like can take various embodiments. In FIG. 4, memory arrays ARYUL and ARY
Each memory array represented by the DL can include an arbitrary number of redundant elements, and can be divided into an arbitrary number of sub-memory arrays. The specific circuit configuration of each unit circuit of the sense latch SLL and the data latches DLU and DLD is not limited by this embodiment.

In FIG. 5, the distribution characteristics of the two-layer gate structure type memory cell can take various embodiments, and the correspondence between the binary mode and the multi-level mode is arbitrary. The logical value of the data assigned to each distribution area can be set arbitrarily. In FIG. 6, the bit configuration of the memory command is
It can be set arbitrarily, and the bit positions and combinations assigned as the binary / multi-value designation bits can also be set arbitrarily.

In FIG. 7 to FIG. 9 and FIG. 11, the specific processing procedures of the read and write operations in the binary mode and the quaternary mode of the flash memory are not restricted by these embodiments. In FIG. 10, the level of the bit line during the multi-value read operation can be set arbitrarily. In FIGS. 12, 13 and 14, the specific method and procedure of the data compression / decompression processing of the flash memory can take various embodiments as long as the logic is maintained.

In each embodiment, the memory cell MC3 or the like operating in the multi-level mode can take an arbitrary multi-level mode such as an 8-level mode. Also, the flash memories FM0 to FM0
The polarity such as the power supply voltage and the boundary potential of the FM3 and the flash file system FF, and the conductivity type of the MOSFET are not restricted by each embodiment.

In the above description, the case where the invention made mainly by the present inventor is applied to a flash memory and a flash file system including the flash memory, which is the field of application, has been described. However, the present invention is not limited to this. For example, various types of memory integrated circuit devices such as a single unit configured as a flash memory, an electrically erasable and programmable read only memory (EEPROM), and various digital systems including such a memory integrated circuit device Also applicable to INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device having a memory array in which memory cells which can be switched and used in at least a binary mode and a multi-level mode are arranged in a lattice, and a system including such a semiconductor memory device.

[0085]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor memory device such as a flash memory included in a system such as a flash file system, a two-layer gate structure type memory cell constituting a memory array is selectively stored in a binary mode or multi-level in a four-level mode in accordance with a command. Operate in mode.
The storage area is, for example, a binary area which selectively operates in a binary mode or a multi-level area which operates in a multi-level mode in units of sectors, that is, word lines, and a flash file system or the like. A binary / multilevel management table is provided which indicates whether the storage area is assigned to a binary area or a multilevel area.

Further, a storage area allocated to a binary area such as a flash memory is used as a buffer area at the time of writing or reading data to / from a multi-level area. A data compression function for reading data written in a memory cell and writing it to one memory cell in a multi-value area, and reading data written in one memory cell in a multi-value area, for example, two pieces of data in a binary area And a data decompression function for writing data into the memory cells of

As described above, a binary area having a relatively low data density but capable of high-speed operation and a multi-value area having a relatively low operation speed but high data density can be realized on the same chip. Can be selectively used according to the system configuration, and the configuration ratio can be set freely. In addition, by using a binary area as a buffer area and providing a flash memory or the like with a data compression function and a data decompression function between a binary area and a multi-value area, an apparent device viewed from an access device side of the flash memory or the like is provided. The chip size can be reduced while shortening the access time. As a result, the speed of a flash file system including a flash memory and the like can be increased, and the convenience thereof can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a flash file system to which the present invention is applied.

FIG. 2 is an address configuration diagram showing an embodiment for explaining an address area of the flash file system of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of a flash memory included in the flash file system of FIG. 1;

FIG. 4 is a partial circuit diagram showing one embodiment of a memory array and peripheral portions of the flash memory of FIG. 3;

FIG. 5 is a distribution characteristic diagram showing an example of a threshold voltage of a memory cell of a two-layer gate structure forming a memory array of the flash memory of FIG. 3;

FIG. 6 is a bit configuration diagram showing an embodiment of a memory command for the flash memory of FIG. 3;

FIG. 7 is a processing flowchart showing one embodiment of a binary read operation of the flash memory of FIG. 3;

FIG. 8 is a processing flowchart showing one embodiment of a binary write operation of the flash memory of FIG. 3;

FIG. 9 is a processing flowchart showing an embodiment at the time of a multi-level (quaternary) read operation of the flash memory of FIG. 3;

FIG. 10 is an explanatory diagram showing one embodiment for explaining a bit line level at the time of a multi-level (quaternary) read operation of the flash memory of FIG. 3;

FIG. 11 is a processing flowchart showing one embodiment during a multi-level (quaternary) write operation of the flash memory of FIG. 3;

FIG. 12 is a conceptual diagram showing one embodiment for explaining data compression / decompression operations of the flash memory of FIG. 3;

FIG. 13 is a processing flowchart showing one embodiment of a data compression operation of the flash memory of FIG. 3;

FIG. 14 is a processing flowchart showing one embodiment of a data decompression operation of the flash memory of FIG. 3;

[Explanation of symbols]

FF: Flash file system, MC: Microcomputer, AB: Address bus, DB: Data bus, ST: Sector management table, WT: Write count management table, VT: Binary / multi-value management table , FM: flash memory, ECC: ECC circuit, WB: write buffer, BI: standard bus interface unit, BUS: standard bus. FM0 to FM3 ...
Flash memory, W0 to Wm ... word lines. MAT
U, MATD: Memory mat, MDU, MDD: Main decoder, SDUL, SDUR, SDML, SDM
R, SDDL, SDDR ... sub-decoder, WL ... word line, BL ... bit line, SLL, SLR ... sense latch, DLUL, DLUR, DLDL, DLDR ...
Data latch, ROMC ROM control system circuit, ROM
D: ROM decoder, ROM: Read only memory, WE: Write / erase control circuit, PC: Direct peripheral control circuit, CPG: Clock generation circuit, STR: Status register, MA0 to MA7: Main amplifier , ID
A: Input data operation circuit, CMD: Command decoder, ADC: Address counter, RC: Redundancy relief circuit, FC: Fuse circuit, ADG: Address generator, POWC: Power supply control circuit, VRG: Reference Power supply circuit, VC: Step-down circuit, POWS: Power supply switching circuit, CB: Control signal buffer, IOC: Input / output control circuit, RBB: Ready / busy signal buffer, IOB
0 to IOB7 Data input / output buffer. CEB: chip enable signal or its input terminal, WEB: write enable signal or its input terminal, OEB ... output enable signal or its input terminal, RESB ... reset control signal or its input terminal, CDEB ... command data enable Signal, SC: serial clock signal, R
/ BB: ready busy signal, IO0 to IO7: input / output data or input / output terminals. CIOS, CIOD…
... Common IO lines, WLU1-WLU2, WLD3 ... Word lines, BLU, BLD ... Bit lines, MC1-MC3
…… Memory cell, USL …… Unit sense latch, UDL
U, UDLD unit data latch, N11 to N14,
N21 to N28, N31 to N34 ... N channel MO
SFET. VRW1 to VRW3 ... boundary potential (word line selection potential). CMB0 to CMB7 ... command data.
ST71-ST73, ST81-ST82, ST91-
ST910, ST111 to ST117, ST131 to S
T135, ST141 to ST145 ... processing step.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Sato 3-16-16 Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. 5B025 AA03 AB01 AC01 AD03 AD04 AD05 AE08

Claims (9)

[Claims] 1. An apparatus according to claim 1, wherein said second instruction is selectively performed according to an instruction from said access device.
A semiconductor memory device comprising: a memory array in which memory cells operating in a value mode or a multi-value mode are arranged in a lattice. 2. The semiconductor memory according to claim 1, wherein the memory cell is a memory cell having a two-layer gate structure, and the multi-level mode is a quaternary mode. apparatus. 3. The storage area according to claim 1, wherein the storage area of the semiconductor memory device is a binary area that selectively operates in a binary mode or a multi-level area that operates in a multi-level mode in units of word lines. A semiconductor memory device characterized in that: 4. The semiconductor storage device according to claim 1, wherein the semiconductor storage device is included in a predetermined system, and the storage area of the semiconductor storage device is the second storage device.
A semiconductor memory device comprising a binary / multi-value management table indicating which of a value region and a multi-value region is assigned. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device reads data written in two memory cells of the binary region, and reads the data written in the two-valued region. Of 1
And a data decompression function for reading data written to one memory cell in the multi-value area and writing the data to two memory cells in the binary area. A semiconductor memory device characterized by the above-mentioned. 6. The data writing time and the data reading time required for the binary area according to claim 4, wherein the data writing time and the data reading time for the multi-value area are respectively shortened. The semiconductor memory device according to claim 1, wherein the binary area is used as a buffer area when writing or reading data to or from the multilevel area. 7. Selectively according to an instruction of an access device.
A system comprising a semiconductor memory device including a memory array in which memory cells operating in a value mode or a multi-value mode are arranged in a lattice. 8. The storage area according to claim 7, wherein the storage area of the semiconductor memory device is a binary area which operates selectively in a binary mode or a multi-level area which operates in a multi-level mode in units of word lines. Wherein the system includes a binary / multivalue management table indicating whether the storage area of the semiconductor storage device is assigned to the binary area or the multilevel area. . 9. The system according to claim 7, wherein said semiconductor memory device is a flash memory, and said system is a flash file system including a predetermined number of said flash memories.