JP2007251876A - Variable phase shifter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small and precise variable phase shifter, to which a phase quantity converted to time can be set. <P>SOLUTION: The relation between the phase quantity and the phase comparator output is obtained, in advance, by using two fixed delaying devices. Then, the output value of a phase comparator, corresponding to the phase quantity of time reference set by the relation, is obtained, and the control voltage of a variable delay device is adjusted so that the output of the phase comparator becomes this output value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a variable phase shifter capable of varying a phase amount used for a clock phase variable unit of a high bit error rate measuring instrument requiring high time accuracy, and in particular, a phase amount converted to time can be set. The present invention relates to a variable phase shifter.

  The variable phase shifter capable of controlling the phase is roughly classified into a semiconductor variable phase shifter and a mechanical variable phase shifter. The mechanical variable phase shifter changes a delay amount by expanding and contracting a trombone-shaped coaxial airline, and time accuracy and linearity are mainly determined by the accuracy of the coaxial airline and the positioning accuracy of the driving device.

  Many commercially available high-frequency semiconductor variable phase shifters of 10 GHz or more utilize clock reflection and synthesis. Therefore, although the frequency range of the clock signal is limited, it has a feature that it is smaller than the mechanical type and can control the phase steplessly with voltage, and is a portable error rate measuring instrument or SDH analyzer. And so on. The semiconductor variable phase shifter changes in degrees with respect to frequency and cannot be controlled by time. Further, since the characteristics change depending on the frequency, the time accuracy is not high.

  FIG. 7 shows a variable phase shifter capable of controlling the phase amount in terms of time. In FIG. 7, reference numeral 10 denotes a variable delay device that can control the phase amount (delay amount) with the control voltage VC, and receives a clock IN and outputs a clock OUT. The frequency of the clock OUT is measured by the frequency counter 11. A temperature sensor 12 measures the ambient temperature.

  Before using this variable phase shifter, the relationship between the control voltage VC using the frequency of the variable delay unit 10 as a parameter and the phase amount is measured using an oscilloscope or the like. An example of this relationship is shown in FIG. In FIG. 8, the horizontal axis represents the magnitude of the control voltage VC, and the vertical axis represents the phase amount in degrees. Since the phase amount changes depending on the frequency, it is measured for each frequency used. The frequency of the signal is measured by the frequency counter 11, the phase amount in degrees is obtained from the graph of FIG. 8, and is converted into the phase amount in time unit using the frequency of the signal. When the phase amount of the variable delay device 10 changes with temperature, the ambient temperature is measured by the temperature sensor 12 and corrected. In this way, when the relationship between the control voltage VC and the phase amount is nonlinear, the phase amount in an arbitrary time unit can be set even when the phase amount changes depending on the frequency and the ambient temperature.

  Patent Document 1 describes an invention of a variable delay device calibration method. The outline of the present invention will be described with reference to FIG. The period counter 21 divides the reference clock, which is the output of the reference clock generator 20, by a predetermined division ratio, and outputs it to the enable terminals CE of the coarse delay counters 22 and 23. The coarse delay counters 22 and 23 count the reference clock. Preset values are set in the coarse delay counters 22 and 23 from the coarse delay registers 22a and 23a, respectively.

  The outputs of the coarse delay counters 22 and 23 are input to the variable delay devices 24 and 25, respectively. The delay amounts of the variable delay devices 24 and 25 can be varied by setting values in the fine delay registers 24a and 25a, respectively. The outputs of the variable delay devices 24 and 25 are input to the phase comparator 26, and the phase difference between these outputs is measured.

  In such a configuration, the set values of the coarse delay registers 22a and 23a are set to N and N-1, respectively, the set value of the fine delay register 24a is kept constant, and the phase difference is 0 while looking at the output of the phase comparator 26. The set value of the fine delay register 25a is adjusted so that Next, the same operation is repeated by changing the period of the reference clock. By this series of operations, the variable delay device 24 can be calibrated.

  Patent Document 2 describes an invention of a jitter generator with a calibration function. The present invention will be described with reference to FIG. In FIG. 10, the output of the reference clock signal generator 30 is input to the in-phase / anti-phase clock output unit 31. The in-phase / anti-phase clock output unit 31 outputs in-phase and anti-phase signals of the input signal. The in-phase and anti-phase outputs and the output of the voltage controlled oscillator 36 are selected by the switching unit 32 controlled by the calibration means 38. In phase. The in-phase output of the anti-phase clock output unit 31 and the output of the switching unit 32 are input to the phase comparator 33, and the phase difference between these signals is detected. A high-frequency component is removed from the phase difference signal by the carrier filter 34, and the phase difference signal is input to the jitter applying unit 35 and added to the jitter signal. This addition signal is input to the voltage controlled oscillator 36. The output of the carrier filter 34 is input to the level detector 37.

  In such a configuration, calibration is performed first. That is, the switching unit 32 selects the in-phase output of the in-phase / anti-phase clock output unit 31 and stores the output of the level detector 37 at this time in the calibration unit 38. Next, the reverse phase output is selected, and the output of the level detector 37 at this time is stored in the calibration means 38.

  When the calibration is completed, the calibration means 38 controls the switching unit 32 to select the output of the voltage controlled oscillator 36 and apply the jitter signal. The level detector 37 measures the jitter amount, calibrates it with the reference value stored in the calibration means 38, and displays it on the display unit in the level detector 37.

  FIG. 11 shows the characteristics of the phase comparator. (A) is a characteristic of a phase frequency comparator. This phase comparator detects and averages the high and low pulse widths corresponding to the phase amount. The phase can be detected up to ± 360 °, and since it is fixed outside the upper and lower limits other than that, there is a feature that positive / negative determination can be made even outside the range. Since it is implemented by a plurality of logic circuits, it is relatively slow. Further, as can be seen from the figure, there is a dead zone in the region where the positive / negative phase detection is switched, and the linearity deteriorates in that region.

FIG. 8B shows characteristics of a phase comparator using a mixer or logic. The phase difference of the two input clocks is detected as a High and Low pulse width using a mixer, logic such as XOR, AND, etc., and used after averaging. Those using a mixer have high speed and low noise, but are limited to the solid line range in the figure and have a narrow linearity range. In addition, the one using logic has excellent linearity, but is slower than the one using a mixer and has a lot of noise.
JP-A-6-188700 JP-A-10-224213

  However, such a variable phase shifter and calibration method have the following problems. In order to use the variable phase shifter of FIG. 7, the relationship between the control voltage and the phase amount as shown in FIG. 8 must be measured in advance. However, data cannot be measured for all control voltages and frequencies, and the phase amount and frequency actually used are only known at that time. Therefore, there is a problem that data having no measured value must be calculated using interpolation, and an error occurs. In addition, there is a problem that a large amount of measurement data is required to reduce this error.

  The variable delay device calibration method of FIG. 9 has an advantage that the variable delay device can be calibrated with high accuracy, but has a problem that the apparatus becomes complicated. Further, although the jitter generation apparatus with a calibration function in FIG. 10 has a simple configuration, there is a problem that an error increases because calibration can be performed only at two points.

  Accordingly, an object of the present invention is to provide a variable phase shifter capable of setting a phase amount converted into time with a small size and high accuracy.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
A first fixed delay unit to which a signal is input and having a predetermined delay amount;
A second fixed delay having the predetermined delay amount including zero, to which the signal is input;
A selector that receives the outputs of the first and second fixed delay units and selects these outputs;
A phase comparator that has two input terminals and outputs a signal related to a phase difference between signals applied to these input terminals, and an output of the selector is input to one of the input terminals;
When the signal is input and the output is applied to the other input terminal of the phase comparator, a delay amount based on the time obtained by using the first and second fixed delay devices and the phase comparator A variable delay device in which the delay amount is set using the relationship with the output of
Is provided. Time-based phase amount can be set.

The invention according to claim 2
A first fixed delay unit to which a signal is input and having a predetermined delay amount;
A second fixed delay having the predetermined delay amount including zero, to which the signal is input;
A second variable delay device that receives the signal and can change a delay amount;
A selector that receives the output of the second variable delay device and the outputs of the first and second fixed delay devices and selects these outputs;
A phase comparator that has two input terminals and outputs a signal related to a phase difference between signals applied to these input terminals, and an output of the selector is input to one of the input terminals;
The signal is input, the output is applied to the other input terminal of the phase comparator, and the time obtained using the second variable delay device and the first and second fixed delay devices is used as a reference. A first variable delay device in which a delay amount is set using a relationship between the delay amount and the output of the phase comparator;
Is provided. Time-based phase amount can be set.

The invention according to claim 3 is the invention according to claim 1 or claim 2,
A wiring is used as the second fixed delay device. Configuration is simplified.

The invention according to claim 4 is the invention according to claim 2,
The delay amount of the first fixed delay device is set in the second variable delay device. The setting range can be expanded.

The invention according to claim 5 is the invention according to claim 2,
In the second variable delay device, a delay amount corresponding to the maximum phase difference that can be detected by the phase comparator is set. The setting range can be expanded.

As is apparent from the above description, the present invention has the following effects.
According to the first, second, third, fourth, and fifth inventions, the relationship between the phase amount based on time and the output of the phase comparator is obtained using two fixed delay devices, and an arbitrary value can be obtained using this relationship. Is set in the first variable delay device. Further, a delay amount corresponding to the reference phase is set in the second variable delay device, and the first variable delay device phase amount is set using the phase difference between the first and second variable delay device outputs.

  Since the delay amount of the fixed delay device is used as a reference, there is an effect that the phase amount based on time can be set. Moreover, since the phase amount is set using the output of the phase comparator, the phase amount can be set with the measurement accuracy of the phase comparator even if the delay amount of the variable delay device fluctuates due to the influence of the frequency or the ambient temperature. There is also an effect. Furthermore, even if the accuracy is lowered due to some influence, there is an effect that the setting accuracy can be maintained by recalibration using the fixed delay device again.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a variable phase shifter according to the present invention. In FIG. 1, reference numerals 40 and 41 denote variable delay devices to which a signal IN is input. The variable delay devices 40 and 41 are delay devices that can change the delay amount by changing the control voltage. Further, the output of the variable delay device 40 becomes the output OUT of this variable phase shifter.

  Reference numerals 42 and 43 denote fixed delay devices to which the signal IN is input. The fixed delay units 42 and 43 delay the input signal for a predetermined time and output it. This delay time is fixed and does not depend on the frequency of the input signal. Note that the fixed delay device 43 may be a wiring only without using a delay device. In this case, the delay amount becomes zero.

  A selection unit 44 has three input terminals A to C and one output terminal D, selects a signal applied to the input terminals A to C, and outputs the selected signal to the output terminal D. The outputs of the variable delay device 41 and the fixed delay devices 42 and 43 are input to the input terminals A to C, respectively.

  Reference numeral 45 denotes a phase comparator that outputs a signal related to the phase difference between the signals applied to the input terminals PIN1 and PIN2 to the output terminal POUT. The output of the variable delay device 40 is input to the input terminal PIN1, and the signal selected by the selector 44 is input to the PIN2. Reference numeral 46 denotes a control unit to which the output of the phase comparator 45 is input. Further, the control voltage VC2 is output to the variable delay device 40, the control voltage VC1 is output to the variable delay device 41, and the selector 44 is controlled. Note that the delay amounts of the fixed delay units 42 and 43 are fixed time regardless of the frequency. The output range of the phase comparator 45 is -Vo to + Vo, and 0 V is output when the phase difference between the signals input to the input terminals PIN1 and PIN2 is zero.

  Next, the operation of this embodiment will be described with reference to the flowchart of FIG. It is assumed that the delay amount of the fixed delay unit 43 is 0, that is, only the wiring. In FIG. 2, the control unit 46 operates the selector 44 to connect the fixed delay unit 43 to the input terminal PIN2 of the phase comparator 45 in step (S2-1). Then, the control voltage VC2 is set to 0V, and it is confirmed that the output of the phase comparator 45 is 0V (phase difference 0) (step (S2-2)). The phase at this time is set as a reference phase.

  As described above, since the fixed delay device 43 is only wiring, the delay amount is zero. Further, when the control voltage VC2 input to the variable delay device 40 is set to 0V, the delay amount is also reduced to zero. Therefore, the phase difference detected by the phase comparator 45 becomes 0, and its output also becomes 0V.

  Next, the controller 46 operates the selector 44 in step (S2-3) to connect the fixed delay device 42 to the input terminal PIN2 of the phase comparator 45. In step (S2-4), the relationship between the delay amount in units of time and the output of the phase comparator 45 is obtained from the output voltage of the phase comparator 45 and the delay amount (time) of the fixed delay device 42 at this time. .

  Next, the fixed delay device 43 is again connected to the input terminal PIN2 of the phase comparator 45 in step (S2-5), and the relationship between the delay amount and the output of the phase comparator 45 is used in step (S2-6). The control voltage VC2 is adjusted to set the delay amount (phase amount in time unit) of the variable delay device 40. In this embodiment, the variable delay device 41 is not used. Thereby, the delay amount of the variable delay device 40 can be set in units of time. Further, since the delay amount of the variable delay device 40 is set using the output of the phase comparator 45, the accuracy and linearity of the phase comparator 45 are not affected by the accuracy and nonlinearity of the variable delay device 40. Can be set.

  This will be described with reference to FIG. The horizontal axis in FIG. 3 represents the delay amount in time units, and the vertical axis represents the output voltage of the phase comparator 45. Assuming that the output voltage range of the phase comparator 45 is −Vo to + Vo, the setting range is a rectangular range 53 with vertical lines. A white circle 50 is a point confirmed in the step (S2-2). When the delay amount is 0, the output of the phase comparator 45 is 0. A white circle 51 is a point in the step (S2-3), DL2 is a delay amount of the fixed delay device 42 in time units, and Vdl2 is an output voltage of the phase comparator 45 at that time.

  A straight line 52 connecting the white circles 50 and 51 is a straight line representing the relationship between the delay amount in time units and the output of the phase comparator 45. By using this straight line 52, the output voltage value of the phase comparator 45 corresponding to the delay amount to be set is obtained, and the control voltage VC2 is adjusted so as to be this voltage value, whereby an arbitrary delay amount (time unit phase amount). ) Is obtained. For example, in order to obtain the delay amount DLx, the voltage Vdlx corresponding to DLx on the straight line 52 is obtained, and the control voltage VC2 may be adjusted so that the output voltage of the phase comparator 45 becomes this Vdlx.

  Since the slope of the straight line 52 is Vdl2 / DL2, the settable range of the delay amount is 0 to Vo · DL2 / Vdl2. Further, when the output of the phase comparator 45 does not become 0V in the step (S2-2), the point 50 may be moved along the vertical axis. Further, when the delay amount of the fixed delay device 43, which is a wiring, cannot be ignored, or when a fixed delay device having a non-zero delay amount is used as the fixed delay device 43, the point 50 is moved along the horizontal axis by the delay amount. Just do it.

  FIG. 4 is a flowchart showing the operation of another embodiment. Steps (S4-1) to (S4-4) are the same as steps (S2-1) to (S2-4) in the flowchart of FIG.

  In step (S4-5), the control unit 46 adjusts the control voltage VC2 so that the output voltage of the phase comparator 45 becomes 0V. In step (S4-6), the selector 44 is operated to connect the variable phase shifter 41 to the input terminal PIN2 of the phase comparator 45. In step (S4-7), the output voltage of the phase comparator 45 is set to 0V. Thus, the control voltage VC1 is adjusted. As a result, the delay amount of the fixed delay device 42 is set in the variable delay device 41. In step (S4-8), the control unit 46 sets a delay amount in a desired time unit in the variable delay device 40 using the relationship obtained in step (S4-4). The method for setting the delay amount is the same as the method described with reference to FIG.

  In this embodiment, since the variable delay device 41 having the delay amount DL2 is connected to the input terminal PIN2 of the phase comparator 45, the output of the phase comparator 45 is 0 when the delay amount of the variable delay device 40 is DL2. When the amount is 0, it becomes −Vdl2. That is, the reference phase is shifted by DL2 compared to FIG. This relationship is shown in FIG. In addition, the same code | symbol is attached | subjected to the same element as FIG. 3, and description is abbreviate | omitted.

  In FIG. 5, 54 is a straight line representing the relationship between the delay amount of the variable delay device 40 and the output voltage of the phase comparator 45. As described above, in this embodiment, when the delay amount of the variable delay device 40 is DL2, the output voltage of the phase comparator 45 becomes 0. Therefore, the straight line 54 is a straight line obtained by translating the straight line 52 downward by Vdl2. . Since the output range of the phase comparator 45 is −Vo to + Vo, the setting range of the delay amount of the variable delay device 40 is a vertical line range 55. That is, the setting range of the delay amount of the variable delay device 40 is 0 to Vo · DL2 / Vdl2 + DL2, which is increased by the delay amount (DL2) set in the variable delay device 41 as compared with FIG.

  The delay amount of the variable delay device 41 can be varied by the control voltage VC1. By utilizing this, the setting range of the delay amount of the variable delay device 40 can be further expanded. This will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the same element as FIG. 3, and description is abbreviate | omitted.

  56 represents the relationship between the delay amount of the variable delay device 40 and the output voltage of the phase comparator 45 when the delay amount of the variable delay device 41 is set to Vo · DL2 / Vdl2 (the right end of the setting range 53 in FIG. 3). Straight line. For the same reason as in FIG. 5, when the delay amount of the variable delay device 40 is Vo · DL2 / Vdl2, the output voltage of the phase comparator 45 becomes zero. Similarly, the output voltage when the delay amount is 0 is −Vo, 2 · Vo · DL2 / Vdl2, and the output voltage is + Vo. The setting range of the delay amount of the variable delay device 40 is a vertical line range 57, which can be doubled as compared with the embodiment of FIG.

  In order to set the delay amount Vo · DL2 / Vdl2 in the variable delay device 41, the output voltage of the phase comparator 45 corresponding to this delay amount is obtained using the straight line 54 of FIG. 5, and the output voltage becomes this value. Thus, the control voltage VC2 is set. Thus, the delay amount Vo · DL2 / Vdl2 can be set in the variable delay device 40. Next, the control voltage VC1 is adjusted so that the output voltage of the phase comparator 45 becomes 0V. In this way, the delay amount Vo · DL2 / Vdl2 can be set in the variable delay device 41.

  The delay amount of the variable delay device 41 can be set larger than Vo · DL2 / Vdl2. In this case, it is not possible to set the delay amount near 0 and the settable range does not change, but the maximum settable delay amount can be expanded. That is, the variable range of the variable delay units 40 and 41 can be utilized to the maximum without being restricted by the phase difference detection range of the phase comparator 45.

  In the case of FIG. 2 embodiment, if the step (S2-5) is omitted, that is, if the fixed delay device 42 is left connected to the input terminal PIN2 of the phase comparator 45, the same reason as shown in FIG. Thus, the delay amount setting range of the variable delay device 40 can be expanded by DL2.

  In addition, these embodiments are described on the assumption that an ideal phase comparator is used as the phase comparator 45, in which the output is 0 when the phase difference is 0, and the phase difference is 0 in the center of the phase difference detection range. However, a phase comparator that has a phase difference of 90 ° and an output of 0 as shown in FIG.

It is a block diagram which shows one Example of this invention. It is a flowchart which shows one Example of this invention. It is a characteristic view for demonstrating operation | movement of one Example of this invention. It is a flowchart which shows the other Example of this invention. It is a characteristic view for demonstrating operation | movement of the other Example of this invention. It is a characteristic view for demonstrating operation | movement of the other Example of this invention. It is a block diagram of the conventional variable phase shifter. It is a characteristic view which shows the relationship between the control voltage and phase amount of a variable phase shifter. It is a block diagram of the calibration apparatus of the conventional variable delay device. It is a block diagram of the conventional jitter generator with a calibration function. It is a characteristic view of a phase comparator.

Explanation of symbols

40, 41 Variable delay device 42, 43 Fixed delay device 44 Selector 45 Phase comparator 46 Control unit 50, 51 Measurement point 52, 54, 56 Straight line 55, 57 Setting range VC1, VC2 Control voltage

Claims (5)

A first fixed delay unit to which a signal is input and having a predetermined delay amount;
A second fixed delay having the predetermined delay amount including zero, to which the signal is input;
A selector that receives the outputs of the first and second fixed delay units and selects these outputs;
A phase comparator that has two input terminals and outputs a signal related to a phase difference between signals applied to these input terminals, and an output of the selector is input to one of the input terminals;
When the signal is input and the output is applied to the other input terminal of the phase comparator, a delay amount based on the time obtained by using the first and second fixed delay devices and the phase comparator A variable delay device in which the delay amount is set using the relationship with the output of
A variable phase shifter comprising: A first fixed delay unit to which a signal is input and having a predetermined delay amount;
A second fixed delay having the predetermined delay amount including zero, to which the signal is input;
A second variable delay device that receives the signal and can change a delay amount;
A selector that receives the output of the second variable delay device and the outputs of the first and second fixed delay devices and selects these outputs;
A phase comparator that has two input terminals and outputs a signal related to a phase difference between signals applied to these input terminals, and an output of the selector is input to one of the input terminals;
The signal is input, the output is applied to the other input terminal of the phase comparator, and the time obtained using the second variable delay device and the first and second fixed delay devices is used as a reference. A first variable delay device in which a delay amount is set using a relationship between the delay amount and the output of the phase comparator;
A variable phase shifter comprising:   The variable phase shifter according to claim 1, wherein the second fixed delay unit is a wiring.   The variable phase shifter according to claim 2, wherein a delay amount of the first fixed delay unit is set in the second variable delay unit. The variable phase shifter according to claim 2, wherein a delay amount corresponding to a maximum phase difference that can be detected by the phase comparator is set in the second variable delay block.

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