JP2007251210A - Capacitor and method of forming the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a ferroelectric film capacitor in which a sufficient yield for adapted to ULSI chips can be secured. <P>SOLUTION: In one embodiment, after the formation of a first ferroelectric film as the capacitor ferroelectric film, an extremely thin second ferroelectric film is deposited to fill a cavity generated between the crystal grains, thereby forming a capacitor in which a leakage current is reduced and a yield is high. In the other embodiment, the cavity is filled with an insulating layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device technology, and more particularly to a ferroelectric thin film capacitor having a small leakage current and a high yield when applied to a semiconductor memory.

  In order to achieve high integration of conventional semiconductor devices, miniaturization of the constituent elements is progressing, but in a dynamic memory (DRAM) that requires a fine and high-capacitance capacitor, a ferroelectric having an extremely high relative dielectric constant. The use of body thin films has attracted attention. For example, (P. J. Bhattacharya et al., Jpn. J. Appl. Phys. Vol. 32 (1993) pp. 4103-4106) can be considered as prior art.

However, according to the disclosure of Bhattacharya et al. Described above, when a (Ba, Sr) TiO ₃ (hereinafter abbreviated as “BST”) film is formed on a Pt substrate, the crystal of this film grows in a columnar shape. It has been found that a high relative dielectric constant of about 300 can be secured. However, when a capacitor is formed using these thin films, a capacitor having a very excellent insulating property can be formed. On the other hand, many of them have a large leakage current or an initial short circuit failure, which is suitable for mass production of a VLSI such as a DRAM. It was not enough to secure the yield. As a result of examining the cause in detail, it was discovered that cavities were generated at the grain boundaries. One of the objects of the present invention is to provide a capacitor and a method for manufacturing the same that can sufficiently secure a yield that can be applied to a VLSI.

Further, a semiconductor device, particularly a DRAM, requires a small area capacitor. In order to realize these capacitors, a ferroelectric thin film such as (Ba, Sr) TiO ₃ or Pb (Zr, Ti) O ₃ having a very high relative dielectric constant has attracted attention. However, when a capacitor is formed using these thin films, a capacitor having a very excellent insulating property can be formed. On the other hand, many of them have a large leakage current or an initial short circuit failure and can be applied to ULSI such as DRAM. Yield could not be secured. One of the objects of the present invention is to provide a capacitor capable of securing a yield that can be applied to ULSI and a method for manufacturing the same.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
That is, after the formation of the first ferroelectric thin film as the capacitor dielectric, a very thin second ferroelectric thin film is deposited to fill the cavity generated between the crystal grains. As a result, a capacitor with a small leakage current and a high yield is formed. In another aspect, an insulating layer is embedded in a cavity between crystal grains generated after the formation of the ferroelectric thin film, thereby forming a ferroelectric thin film for a capacitor with a small leakage current and a high yield. .

(Function)
According to the above-described invention, it is possible to reduce the initial short circuit failure while being excellent in insulation between the capacitor such as DRAM and the upper and lower electrodes and suppressing the leakage current.
As a result, the leakage of charge accumulated in the ferroelectric capacitor of the DRAM can be minimized, so that if the refresh cycle is made longer than the conventional one or if the same refresh cycle is maintained, the memory cell Therefore, the yield can be improved and a semiconductor memory device suitable for mass productivity can be provided.

First, one embodiment of the present invention will be described with reference to FIGS.
In FIG. 1 for explaining the premise of this embodiment, a TiN film 2 is formed as an adhesive layer on an oxidized silicon substrate 1 by a sputtering method to a thickness of about 50 nm, and a Pt film 3 having a thickness of 200 nm is formed by a sputtering method. Thereafter, the BST film 4 is deposited to a thickness of about 200 nm in an O ₂ / Ar mixed gas using a BST ceramic target material. At that time, film formation is performed at a substrate temperature of about 650 ° C., and a crystallized BST film 4 is grown. This is because the relative dielectric constant of amorphous BST formed at 500 ° C. or lower is about 30, which is smaller than the relative dielectric constant of about 300 of crystallized BST. Finally, a capacitor is formed by forming an upper electrode of Pt. As a result of evaluating the electrical characteristics of this capacitor, it was found that this crystalline BST film has many failures due to initial dielectric breakdown, and a sufficient yield as a capacitor for VLSI cannot be ensured. As a result of detailed analysis of the BST film using a transmission electron microscope and electrical characteristics, the initial dielectric breakdown of the BST film is possible due to the cavities generated at the grain boundaries of the BST film 5 as shown in FIG. You can understand that When the upper electrode Pt film is formed in the cavity by sputtering, it can be assumed that Pt penetrates and the upper electrode and the lower electrode are short-circuited. Therefore, in one aspect of the present invention, an attempt was made to repair the above-described defect by multilayering this ferroelectric thin film and filling the cavity.

Next, the concept of the first embodiment of the present invention will be described with reference to FIGS. Example 1 is a method of repairing defects by stacking SrTiO ₃ (STO) for defects due to cavities in the BST film 4. After the structure of FIG. 1 is formed, an amorphous STO film 5 is formed on the BST film 4 with a film thickness of about 10 nm or less at a substrate temperature of about 400 ° C. Thereafter, a Pt upper electrode is formed by sputtering to a thickness of about 200 nm. This can use capacitor fabrication by conventional lithography methods. The BST film 4 is crystallized and its relative dielectric constant is about 300, but the relative dielectric constant of the STO film 5 is as small as about 20. Therefore, in this laminated structure, the capacitance is reduced by about 25% compared to the single-layer structure of the BST film 4. However, this multi-layering can improve the leakage current of the film by about two orders of magnitude, and the initial dielectric breakdown rate that is thought to be due to the cavity of the BST film 4 is significantly reduced, so that the yield of the capacitor is further improved. is there. It will be understood that the effect of the present invention may be formed of multilayered ferroelectric thin films made of different materials, and that the effect is particularly high when formed of different materials.

  In the present invention, the effect can be further improved by crystallizing the amorphous STO film. That is, after this amorphous STO film is formed, if it is heated in oxygen at 650 ° C., crystallization occurs, and the relative dielectric constant can be increased to about 150. , About 10%. Moreover, it can contribute to the improvement of the yield.

Next, another embodiment of the present invention is shown in FIGS. In this embodiment, amorphous STO is deposited on the crystallized Pb (Zr, Ti) O ₃ film (PZT). As shown in FIG. 3, a TiN film 2 is formed as an adhesive layer on the oxidized silicon substrate 1 by a sputtering method to a thickness of about 50 nm, and further Pt3 having a thickness of 200 nm is formed by a sputtering method. Thereafter, the crystallized PZT film 6 is formed by a sol-gel method. In this step, an organic metal such as Pb, Zr, or Ti is usually dissolved in an organic solvent and deposited on the Pt film 3 to a thickness of about 200 nm by a spin coating method or the like. Thereafter, baking is performed at a temperature of about 150 ° C. to remove the organic solvent and moisture, and further, heat treatment is performed in an oxygen atmosphere at 650 ° C. in order to crystallize the amorphous film. However, since the PZT film 6 contracts during crystallization, a cavity as shown in FIG. 3 is generated at the crystal grain boundary. Thereafter, as shown in FIG. 4, an amorphous STO film 7 is formed on the PZT film 6 with a film thickness of about 10 nm or less at a substrate temperature of about 400.degree. Thereafter, a Pt upper electrode is formed to a thickness of about 200 nm by sputtering, and then a capacitor is formed by conventional lithography. The PZT film 6 has already been crystallized and its relative dielectric constant was about 600. However, the relative dielectric constant of the amorphous STO film 5 is as small as about 20. Therefore, it can be seen that in this laminated structure, the capacitance is reduced by about 60% compared to the single-layer structure of the PZT film 6. However, this multi-layering improves the leakage current of the film by about three orders of magnitude, and the initial dielectric breakdown rate that seems to be due to the cavity of the PZT film 6 is significantly reduced. Therefore, the yield related to capacitor formation can be improved.

  It can be understood that the present invention significantly improves the effect by crystallizing the amorphous STO film. That is, if this amorphous STO film is formed and heated in an oxygen atmosphere at 650 ° C., crystallization occurs, the relative dielectric constant increases to about 150, and the overall capacitance decreases by about 20%. Can be suppressed. Moreover, there is no adverse effect on the yield.

  Further, another embodiment of the present invention is shown in FIGS. In the above embodiment, the characteristics of the ferroelectric were improved by depositing amorphous STO on the crystallized BST film or PZT film. However, if an amorphous BST film having a higher relative dielectric constant is used than using an STO film having a relatively low relative dielectric constant, improvement in characteristics can be achieved while suppressing a decrease in the capacitance of the capacitor. FIG. 5 shows another ferroelectric thin film. First, a TiN film 2 is formed as an adhesive layer on the oxidized silicon substrate 1 with a thickness of about 50 nm by sputtering, and then Pt3 with a thickness of 200 nm is formed by sputtering. Thereafter, the crystallized PZT film 6 is formed by a sol-gel method to complete the film. In this step, an organic metal such as Pb, Zr, or Ti is usually dissolved in an organic solvent and deposited on the Pt film 3 so as to have a film thickness of about 200 nm by a spin coating method or the like. Thereafter, baking is performed at a temperature of about 150 ° C. to remove these organic solvents and moisture, and further, heat treatment is performed in an oxygen atmosphere at 650 ° C. in order to crystallize the amorphous film. However, the PZT film 6 contracts as described above during crystallization, and a cavity as shown in FIG. 3 is generated at the crystal grain boundary. FIG. 6 shows a cross section of a ferroelectric thin film. An amorphous BST film 8 is formed on the PZT film 6 with a film thickness of about 10 nm or less at a substrate temperature of about 500 ° C. on the surface where the cavity is formed. Thereafter, a Pt upper electrode is formed to a thickness of about 200 nm by sputtering, and then a capacitor is formed by conventional lithography. At that time, the PZT film 6 has already been crystallized, and its relative dielectric constant reaches about 600. On the other hand, since the relative dielectric constant of the amorphous BST film 8 is relatively large as about 30 compared to about 20 of the STO film, this laminated structure has an electrostatic capacity of about 30% that of the single layer structure of the PZT film 6. It can be seen that the reduction is only 30%. Furthermore, this multilayering can improve the leakage current of the film by about three orders of magnitude, and can significantly reduce the initial dielectric breakdown rate that is thought to be due to the cavity of the PZT film 6. Therefore, the yield related to the capacitor can be improved.

  In the present invention, the effect can be remarkably improved by crystallizing the amorphous BST film. That is, after the amorphous STO film is formed and heated in oxygen at 650 ° C., crystallization occurs, the relative dielectric constant increases to about 300, and the overall capacitance of the capacitor decreases to about 10%. In addition, the yield can be improved.

  A similar effect can be found even when an amorphous PZT film is deposited on top of the crystalline BST film. That is, since the relative dielectric constant of the amorphous PZT film is about 40, it is possible to form a ferroelectric thin film for capacitors with a smaller yield and a higher yield.

  In the above embodiment, even if the second ferroelectric is amorphous or crystalline, the overall film thickness is increased, so that the yield can be improved, but the decrease in capacitance cannot be avoided. . In another embodiment to solve this technical problem, the second ferroelectric can be removed by dry etching, leaving the second ferroelectric only in the underlying ferroelectric cavity. . This embodiment is shown in FIGS. On the oxidized silicon substrate 1, a TiN film 2 is formed as an adhesive layer with a thickness of about 50 nm by sputtering, and Pt3 having a thickness of 200 nm is further formed by sputtering. Thereafter, the crystallized PZT film 6 is formed by a sol-gel method. In this step, it can be deposited on the Pt film 3 so as to have a film thickness of about 200 nm by spin coating or the like in which an organic metal such as Pb, Zr, or Ti is usually dissolved in an organic solvent. Thereafter, baking is performed at a temperature of about 150 ° C. to remove the organic solvent and moisture, and further, heat treatment is performed in an oxygen atmosphere at 650 ° C. in order to crystallize the amorphous film. However, when the PZT film 6 is crystallized, cavities are generated in the contracted crystal grain boundaries as shown in FIG. Thereafter, as shown in FIG. 8, an amorphous STO film 7 is formed on the PZT film 6 with a film thickness of about 10 nm or less at a substrate temperature of about 500.degree. Thereafter, as shown in FIG. 9, the amorphous STO film 7 can be selectively left in the cavity portion of the crystal grain boundary of the PZT film 6 by performing etch back corresponding to 10 nm in Ar plasma. At this time, there is a problem that the leakage current is remarkably increased because defects such as oxygen vacancies occur in the underlying PZT film due to etch back in Ar plasma. According to this embodiment, after the STO film is etched back, an increase in leakage current can be prevented by performing heat treatment at a temperature that can repair this defect. By this method, the initial dielectric breakdown rate that seems to be due to the cavity of the PZT film 6 was reduced, and the yield of the capacitor was also improved.

  In this example, the capacitance of the capacitor did not decrease. In particular, the size of the cavity in the crystal grain boundary portion of the PZT film is often about several nanometers in width, and even if an insulating film having a low relative dielectric constant is embedded in this cavity, the change in capacitance of the capacitor can be ignored. It is.

  In the above embodiment, a method for forming an amorphous BST film on a PZT film has been described. However, a similar effect can be obtained by forming an amorphous PZT film on a BST film.

  In still another embodiment of the present invention, the second ferroelectric PZT film can be removed by dry etching, leaving the second ferroelectric only in the underlying ferroelectric cavity. Examples thereof are shown in FIGS. A TiN film 2 is formed as an adhesive layer on the oxidized silicon substrate 1 to a thickness of about 50 nm by sputtering, and Pt3 having a thickness of 200 nm is formed by sputtering. Thereafter, the crystallized BST film 4 is formed by a sol-gel method. In this step, deposition is usually performed on the Pt film 3 to a film thickness of about 200 nm by a spin coat method in which an organic metal such as Ba, Sr, or Ti is dissolved in an organic solvent. Thereafter, the substrate is baked at a temperature of about 150 ° C. to remove the organic solvent and moisture, and further heat-treated in an oxygen atmosphere at 650 ° C. in order to crystallize the amorphous film. However, the BST film 4 shrinks during the crystallization process, and a cavity as shown in FIG. 10 is generated at the crystal grain boundary. Thereafter, as shown in FIG. 11, an amorphous PZT film 9 is formed on the BST film 4 with a film thickness of about 10 nm or less at a substrate temperature of about 500.degree. As shown in FIG. 12, when an etch back corresponding to 10 nm is performed in Ar plasma thereafter, the amorphous PZT film 9 can be selectively left in the cavity portion of the crystal grain boundary of the BST film 4. At that time, there is a problem that a leakage current is remarkably increased due to defects such as oxygen vacancies in the underlying BST film due to etch back in Ar plasma. Therefore, in this embodiment, after the PZT film is etched back, an increase in leakage current can be prevented by performing heat treatment at a temperature that can repair this defect. By this method, the initial dielectric breakdown rate considered to be due to the cavity of the BST film 4 was remarkably reduced, and the yield of the capacitor was improved.

Also in this example, the capacitance of the capacitor did not decrease.
The present invention can also be applied to ferroelectric materials other than BST. That is, the ferroelectric thin film of the above embodiment may include SrTiO ₃ , BaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , Pb (Zr, Ti) O ₃ , PbTiO _3, etc. as constituent elements. Needless to say, it has a substantial effect.

  In the present invention, the sputtering method and the sol-gel method have been described as examples of the growth method of the ferroelectric thin film, but a known CVD method, MOD method, or the like may be used as this growth method. In particular, when a ferroelectric thin film is formed using the sol-gel method, cavities are often generated at the grain boundaries during crystallization, and the effects of the present invention are remarkable.

  In the above description, the case where the invention made by the present inventor is mainly applied to the DRAM capacitor dielectric film as the background has been described. However, the present invention is not limited to this. It is also possible to apply to a semiconductor integrated circuit device such as a capacitor for a general purpose.

Next, another embodiment of the present invention will be described with reference to FIGS.
FIG. 13 for explaining the premise of this embodiment shows that a Ti film 103 is formed as an adhesive layer on an oxidized silicon substrate 101 by sputtering to a thickness of about 50 nm, a Pt film 104 having a thickness of 200 nm is formed by sputtering, and then BST is formed. A structure is shown in which a film 105 is deposited to a thickness of about 200 nm in an O ₂ / Ar mixed gas using a BST ceramic target material. At that time, film formation is performed at a substrate temperature of about 650 ° C., and a crystallized BST film 105 is grown. The relative dielectric constant of amorphous BST formed at 500 ° C. or lower is about 18, which is smaller than the relative dielectric constant of about 300 of crystallized BST. Finally, a Pt upper electrode is formed to form a capacitor. It can be seen from the electrical characteristics that the crystal BST film is often spilled due to initial dielectric breakdown, so that a sufficient yield as a capacitor for ULSI cannot be secured. As a result of analysis of the BST film using a transmission electron microscope and detailed analysis of electrical characteristics, the initial breakdown of the BST film may be caused by a cavity generated at the grain boundary of the BST film 105 as shown in FIG. It turns out that the nature is high. When the upper electrode Pt film is formed in the cavity by sputtering, Pt enters and the upper electrode and the lower electrode are short-circuited. Therefore, in this aspect of the present invention, the yield of the BST film is improved by filling the cavity of the capacitor portion of the semiconductor device with an insulating film.

An embodiment (sixth embodiment) of the present invention will be described with reference to FIGS. FIG. 14 shows a structure in which a Ti film 103 as an adhesive layer is formed on an oxidized silicon substrate 101 by sputtering to a thickness of about 50 nm, and Pt 104 having a thickness of 200 nm is formed by sputtering. Thereafter, a BST film 105 was deposited to a thickness of about 200 nm in an O ₂ / Ar mixed gas using a BST ceramic target. At that time, the substrate temperature is kept at about 650 ° C., and the BST film 105 is crystallized. In this embodiment, the cavity of the BST film 105 is filled with silicon oxide called spin-on-glass (SOG). A liquid SOG precursor is coated on the entire wafer surface using a spinner (rotary applicator) at a rotational speed of 1000 to 5000 rpm. Then, in order to evaporate a solvent, after baking at 100-200 degreeC (it changes with the boiling points of a solvent), final cure is finally performed at 350-450 degreeC. FIG. 14 shows a structure in which the SOG film 106 having a composition almost similar to SiO ₂ is formed so as to fill the cavity of the BST film 105 as a result. FIG. 15 shows a structure in which the cavity portion is filled with the SOG film 106 by etching away the film thickness equivalent of the SOG film 106 with hydrofluoric acid (HF) diluted to about 1%. In FIG. 14, the cavities are exaggerated and drawn large, but the actual size is about several nanometers or less, and it is easy to leave SOG in the cavities during etching. After this structure is formed, the Pt upper electrode 107 is formed to a thickness of about 200 nm by sputtering, and then a capacitor is formed by a known lithography method. The yield of the capacitor formed by this method is very high, and it is possible to obtain a sufficient yield as a future DRAM capacitor. Further, the effective relative dielectric constant is as very large as about 300.

  In this embodiment, the SOG is etched by the wet method, but the same effect can be obtained by the dry etching method.

16 and 17 show another embodiment of the present invention. A BST film 105 is formed by the same method as in the sixth embodiment. Then, the oxide film 108 is formed by plasma CVD in an Ar / O ₂ atmosphere using organooxysilane such as Si (OC ₂ H ₅ ) ₄ at about 450 ° C. Usually, this oxide film is called a TEOS film. FIG. 16 shows a cross-sectional view in which the TEOS film 108 having a composition almost similar to SiO ₂ is formed so as to fill the cavity of the BST film 105 as a result. Thereafter, as shown in FIG. 17, the TEOS film 108 is etched away by hydrofluoric acid (HF) diluted to about 1%. A structure in which the cavity is filled with the TEOS film 108 is formed. At that time, many of the ferroelectric thin films such as the BST film are not etched by HF, and therefore the BST film is not damaged. After this structure is formed, the Pt upper electrode 107 is formed to a thickness of about 200 nm by sputtering, and then a capacitor is formed by a known lithography method. The yield of the capacitor formed by this method is very high, and a sufficient yield can be realized as a future DRAM capacitor. It was also confirmed that the effective dielectric constant of the BST film was as large as about 300. In this embodiment, the SOG is etched by the wet method, but the same effect can be obtained by the dry etching method.

18 and 19 show still another embodiment of the present invention. A BST film 105 is formed by the same method as in the above embodiment, and monosilane (SiH ₄ ) is reacted in oxygen at a temperature range of about 300 to 500 ° C. using an atmospheric pressure CVD method. A structure in which a CVD oxide film 110 is deposited is shown. As a result, a CVD oxide film 110 having a composition almost similar to SiO ₂ is formed so as to fill the cavity of the BST film 105. A portion corresponding to the thickness of the CVD oxide film 110 is removed by dry etching. In this case, as an etching gas for the CVD oxide film 110, a conventional etching gas for an oxide film, for example, a mixed gas such as CF ₄ / H ₂ mixed gas, CHF ₃ , CHF ₃ / SF ₆ / He may be used. If these etching gases are used, the selectivity of the etching rate with respect to the BST film 105 for etching the CVD oxide film 110 can be made very large, so that the BST film 105 is damaged as schematically shown in FIG. The CVD oxide film 110 can be selectively left in the cavity. In this embodiment, the method of removing the CVD oxide film 110 by the dry etching method has been described. However, a wet method as shown in the above embodiment may be used. Thereafter, the Pt upper electrode 107 is formed to a thickness of about 200 nm by a sputtering method, and then a capacitor is formed by a known lithography method. The yield of the capacitor formed by this method is very high, and it is possible to obtain a sufficient yield as a future DRAM capacitor. Further, the effective relative dielectric constant is as very large as about 300.

20 and 21 disclose still another embodiment of the present invention. A BST film 105 is formed by the same method as in the sixth embodiment, and, for example, tetraisopropoxy titanium Ti (i-OC ₃ H ₇ ) ₄ and oxygen are used at a temperature range of about 300 to 500 ° C. using a low pressure CVD method. FIG. 20 shows a structure in which a CVD-TiO ₂ film 111 is deposited on the BST film 105 by reacting with each other. As a result, it is formed so as to almost Ti O ₂ TiO ₂ film 111 having a composition close to fill the cavities of BST film 105. A portion corresponding to the film thickness of the CVD-TiO ₂ film 111 is removed by a dry etching method. In this case, as the etching gas for the CVD-TiO ₂ film 111, a conventional etching gas for an oxide film such as a mixed gas such as CF ₄ / H ₂ mixed gas, CHF ₃ , CHF ₃ / SF ₆ / He may be used. When these etching gases are used, the selectivity of the etching of the CVD-TiO ₂ film 111 with respect to the BST film 105 can be made very large. Therefore, the CVD-TiO ₂ is selectively formed in the cavity as schematically shown in FIG. The film 111 can be left. Thereafter, an upper electrode 107 of Pt is formed by sputtering to a thickness of about 200 nm, and then a capacitor is formed by conventional lithography. The yield of the capacitor formed by this method is very high, and a sufficient yield can be realized as a future DRAM capacitor. Further, the effective relative dielectric constant is as very large as about 300.

In the present embodiment, the concept of the present embodiment has been described by using the CVD method when forming the TiO ₂ film 111. Alternatively, a sol-gel method may be used. As a method for forming the TiO ₂ film, tetraisopropoxy titanium is used. An organic metal such as Ti (i-OC ₃ H ₇ ) _{4 is used} as an organic solvent, methoxyethanol (CH ₃ OCH ₂ CH ₂ OH), acetic acid (CH ₃ COOH), butanol (C ₄ H ₉ OH), or the like. The same effect can be obtained by diluting with an organic solvent to form a precursor, which is formed on the BST film by spin coating or the like. Further, although the TiO ₂ film is used here to fill the cavity of the BST film, ZrO ₂ , HfO, ScO, Y ₂ O ₃ , V ₂ O _5, Nb ₂ O _5, or the like may be used. For example, in order to form a ZrO ₂ film, fills the cavity of Zr _{(OCH 3} H _{7) 4} or Zr _{(OCH 4} H _{9) 4} and the like to form a ZrO ₂ film by a CVD method or a sol-gel method BST film May be.

Another embodiment of the present invention is shown in FIGS. A BST film 105 is formed by the same method as in the sixth embodiment, and then, for example, tantalum pentethoxy Ta ₂ (i-OC ₃ H ₇ ) ₅ is used at a temperature range of about 400 to 500 ° C. by using a low pressure CVD method. Then, a CVD-Ta ₂ O ₅ film 112 is deposited on the BST film 105. Figure 22 shows the structure _{of the Ta} 2 _{O 5} film 112 almost composition close to _Ta 2 _{O 5} is formed so as to fill the cavities of BST film 105. A portion corresponding to the thickness of the Ta ₂ O ₅ film 112 is removed by dry etching. In this case, as an etching gas for the Ta ₂ O ₅ film 112, a conventional etching gas for an oxide film, for example, a mixed gas such as CF ₄ / H ₂ mixed gas, CHF ₃ , CHF ₃ / SF ₆ / He may be used. These selectively _Ta 2 _{O 5} in the cavity as shown schematically in Figure 23 for take very large selectivity ratio to the etching of the BST film 105 _{the Ta} 2 _{O 5} film 112 by using the etching gas The membrane 112 can be left. Thereafter, a Pt upper electrode 107 was formed to a thickness of about 200 nm by sputtering, and then a capacitor was formed by conventional lithography. The yield of the capacitor formed by this method is very high, and a sufficient yield can be realized as a future DRAM capacitor. Further, the effective relative dielectric constant is as very large as about 300.

In the present embodiment, the concept of the present embodiment has been described using the CVD method when the Ta ₂ O ₅ film 112 is formed. In addition, a sputtering method may be used. Usually, the Ta ₂ O ₅ film can be easily formed by sputtering in Ar containing about 10% oxygen.

Next, another embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 24, a BST film 105 is formed by a method similar to that in the sixth embodiment, and then in a argon gas containing about 10% oxygen at a temperature range of about 400 to 500 ° C. using a sputtering method. Thus, the hafnium oxide film HfO film 113 is formed. As a result, a structure in which the hafnium HfO film 113 is formed so as to fill the cavity of the BST film 105 is shown in FIG. A portion corresponding to the film thickness of the hafnium oxide film HfO film 113 is removed by dry etching. In this case, as an etching gas for the hafnium oxide film 113, a known etching gas for an oxide film, for example, a mixed gas such as CF ₄ / H ₂ mixed gas, CHF ₃ , CHF ₃ / SF ₆ / He may be used. When these etching gases are used, the selectivity of the etching rate of the hafnium oxide film 113 can be made very large with respect to the BST film 105. Therefore, the hafnium oxide film 113 is selectively formed in the cavity as schematically shown in FIG. Can leave. Thereafter, a Pt upper electrode 107 was formed to a thickness of about 200 nm by a sputtering method, and then a capacitor was formed by a known lithography method. The yield of the capacitor formed by this method is very high, and a sufficient yield can be realized as a future DRAM capacitor. Further, the effective relative dielectric constant is as very large as about 300.

  In the present embodiment, the concept of the present embodiment has been described using the sputtering method when forming the hafnium oxide film HfO film 113, but in addition, the CVD method or the sol-gel method may be used.

26 and 27 show another embodiment of the present invention. When heat treatment is performed in an oxygen atmosphere for about 30 minutes at about 650 ° C., Ti from the adhesive layer Ti film 103 (or TiN) or the like underlying the Pt film 104 diffuses through the Pt film grain boundary and precipitates in a form covering the cavities. Then, it is oxidized in oxygen to form a TiO ₂ film 114. This phenomenon can also be confirmed by analysis using a transmission electron microscope. Furthermore, a structure formed so as to cover the crystal grain boundary of the BST film 105 in a portion without a cavity is also shown. When the upper electrode 107 of Pt was formed and the electrical characteristics were evaluated, not only the initial insulation failure of the capacitor but also the leakage current through the crystal grain boundary, which is usually a problem, was reduced. In this case, the relative dielectric constant of the BST film 105 is about 300, and there is no decrease in the relative dielectric constant due to the implementation of this embodiment.

28 and 29 show still another embodiment. In the embodiments so far, the manufacturing method of the capacitor using the Pt film 104 as the lower electrode of the ferroelectric BST film 105 has been described. However, the Pt film is very difficult to dry etch and contains radioactive impurities. However, it is a problem that a ferroelectric thin film is introduced into the ULSI manufacturing process due to the problem of easily causing a soft error. In the present embodiment, a method for manufacturing a capacitor without using the Pt film 104 will be described. In FIG. 28, the BST film 105 is directly formed on the TiN film 116 as an adhesive layer by the same method as in Example 6, and heat treatment is performed in an oxygen atmosphere at about 650 ° C. for about 30 minutes. 3 shows a structure in which Ti is diffused and oxidized through the grain boundaries of the BST film, and is deposited so as to cover the cavities and the grain boundaries, thereby forming TiO ₂ films 114 and 115. FIG. 29 shows a structure in which an electrode is formed on the ferroelectric film. The phenomenon of precipitation on the dielectric film can be confirmed by analysis using a transmission electron microscope. As a result, when the Pt upper electrode 107 was formed and the electrical characteristics were evaluated, it was found that not only the initial insulation failure of the capacitor but also the leakage current through the crystal grain boundary, which is usually a problem, was reduced. Also in this case, the relative dielectric constant of the BST film 105 decreased to about 100, and decreased to about one third of the relative dielectric constant 300 of the BST films of Examples 6 to 12. This is presumably because an extremely thin TiO ₂ film 117 was formed on the surface of the TiN 116 by the oxygen plasma during the formation of the BST film. However, the dielectric breakdown voltage of the BST film 105 increases about three times. Since the relative dielectric constant of an oxide film / nitride film conventionally used for a DRAM capacitor is about 4 to 7, the relative dielectric constant 100 according to this embodiment is an effective range.

Needless to say, the above embodiments can be applied to ferroelectric materials other than BST. That is, the ferroelectric thin film in the present invention may contain SrTiO ₃ , BaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , Pb (Zr, Ti) O ₃ , PbTiO _3, etc. as constituent elements. I do not care. Further, the insertion film for suppressing the growth of columnar crystals in these films may contain elements constituting these ferroelectrics or their oxides. In the present invention, the sputtering method has been described as an example of the growth method of the ferroelectric thin film. However, a CVD method, a sol-gel method using a spin coating method, or the like may be used as this growth method. In particular, when a ferroelectric thin film is formed by using the sol-gel method, an amorphous ferroelectric is usually crystallized by heat treatment, and the effect of the present invention is remarkable.

  In the above description, the case where the invention made by the present inventor is mainly applied to the DRAM capacitor dielectric film as the background has been described. However, the present invention is not limited to this. It is also possible to apply to a semiconductor integrated circuit device such as a capacitor for a general purpose.

(The invention's effect)
The effects obtained by typical inventions among the inventions disclosed in this application will be briefly described as follows.

  That is, in the present invention, a ferroelectric thin film having a low leakage current and a high yield is obtained by laminating a ferroelectric thin film or by embedding an insulating layer in a cavity generated between crystal grains after the ferroelectric thin film is formed. A thin film can be formed.

It is sectional drawing of the principal part intermediate process of the manufacturing process of the ferroelectric capacitor which is the 1st Example of this invention. It is principal part sectional drawing of the manufacturing process of the ferroelectric capacitor which is the 1st Example of this invention. It is sectional drawing of the intermediate process of the manufacturing process of the ferroelectric capacitor which is the 2nd Example of this invention. It is principal part sectional drawing of the intermediate process of the manufacturing process of the ferroelectric capacitor which is the 2nd Example of this invention. It is sectional drawing of the intermediate process of the manufacturing process of the ferroelectric capacitor which is the 3rd Example of this invention. It is sectional drawing of the intermediate process of the manufacturing process of the ferroelectric capacitor which is the 3rd Example of this invention. It is principal part sectional drawing of the manufacturing process of the ferroelectric capacitor which is the 3rd Example of this invention. It is sectional drawing of the intermediate process of the manufacturing process of the ferroelectric capacitor which is the 4th Example of this invention. It is sectional drawing of the intermediate process of the manufacturing process of the ferroelectric capacitor which is the 4th Example of this invention. It is principal part sectional drawing of the manufacturing process of the ferroelectric capacitor which is the 5th Example of this invention. It is sectional drawing of the intermediate process of the manufacturing process of the ferroelectric capacitor which is the 5th Example of this invention. It is principal part sectional drawing of the manufacturing process of the ferroelectric capacitor which is the 5th Example of this invention. 2 is a cross section of a ferroelectric (BST) capacitor film for explaining the premise of the present invention. It is a cross section of the intermediate process of the ferroelectric (BST) capacitor film which is the 6th example of the present invention. It is principal part sectional drawing of the manufacturing process of the ferroelectric (BST) capacitor which is the 6th Example of this invention. It is sectional drawing of the intermediate manufacturing process of the ferroelectric (BST) capacitor which is the 7th Example of this invention. It is principal part sectional drawing of the ferroelectric (BST) capacitor which is the 7th Example of this invention. It is sectional drawing of the intermediate manufacturing process of the ferroelectric (BST) capacitor which is the 8th Example of this invention. It is principal part sectional drawing of the ferroelectric (BST) capacitor which is the 8th Example of this invention. It is sectional drawing of the intermediate manufacturing process of the ferroelectric (BST) capacitor which is the 9th Example of this invention. It is principal part sectional drawing of the ferroelectric (BST) capacitor which is the 9th Example of this invention. It is sectional drawing of the intermediate manufacturing process of the ferroelectric (BST) capacitor which is the 10th Example of this invention. It is principal part sectional drawing of the ferroelectric (BST) capacitor which is the 10th Example of this invention. It is sectional drawing of the intermediate manufacturing process of the ferroelectric (BST) capacitor which is the 11th Example of this invention. It is principal part sectional drawing of the ferroelectric (BST) capacitor which is the 11th Example of this invention. It is sectional drawing of the intermediate manufacturing process of the ferroelectric (BST) capacitor which is the 12th Example of this invention. It is principal part sectional drawing of the ferroelectric (BST) capacitor which is the 12th Example of this invention. It is sectional drawing of the intermediate manufacturing process of the ferroelectric (BST) capacitor which is the 13th Example of this invention. It is principal part sectional drawing of the ferroelectric (BST) capacitor which is the 13th Example of this invention.

Explanation of symbols

1 Oxidized Si substrate 2 TiN film 3 Pt film (lower electrode)
4 Crystal BST film 5 Amorphous STO film 6 Crystal PZT film 7 Amorphous STO film 8 Amorphous BST film 9 Amorphous PZT film

Claims (13)

  A ferroelectric thin film capacitor including a laminated structure of a first crystalline ferroelectric thin film and a second ferroelectric thin film thinner than the first thin film.   2. The ferroelectric thin film capacitor according to claim 1, wherein the second ferroelectric thin film is made of a material different from that of the first ferroelectric thin film.   2. The ferroelectric thin film capacitor according to claim 1, wherein the second ferroelectric thin film is amorphous.   2. The ferroelectric thin film capacitor according to claim 1, wherein the ferroelectric thin film capacitor is formed by depositing the second ferroelectric thin film, etching the second ferroelectric thin film, and then performing a heat treatment in an oxidizing atmosphere. .   2. The ferroelectric thin film capacitor according to claim 1, wherein the second ferroelectric thin film is formed by crystallization from amorphous. The first and second ferroelectric thin films are (Ba, Sr) TiO ₃ , SrTiO ₃ , BaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , Pb (Zr, Ti) O ₃ , PbTiO _3. The ferroelectric thin film capacitor according to claim 1, wherein the ferroelectric thin film capacitor is one selected from the above materials or one of these materials.   A ferroelectric thin film capacitor having a ferroelectric thin film, wherein a crystal grain boundary of the ferroelectric is covered with an insulating oxide film different from the ferroelectric.   A ferroelectric thin film capacitor having a ferroelectric thin film, wherein a TiN film is formed as a base electrode of the ferroelectric.   A method of manufacturing a capacitor having a ferroelectric thin film, the method including a step of embedding an insulating material in a cavity portion generated between crystal grains of the thin film after the ferroelectric thin film is formed.   10. The method of manufacturing a capacitor according to claim 9, further comprising a step of further etching back the insulating layer after the insulating layer is formed.   10. The method of manufacturing a capacitor according to claim 9, wherein the insulating layer is formed by a diffusion phenomenon from an underlying material of the ferroelectric thin film. The ferroelectric thin film is selected from materials of (Ba, Sr) TiO ₃ , SrTiO ₃ , BaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , Pb (Zr, Ti) O ₃ , PbTiO _3. 10. The method of manufacturing a capacitor according to claim 9, wherein the capacitor includes one of these materials.   10. The method of manufacturing a capacitor according to claim 9, wherein the insulating layer is one selected from oxides of Si, Ta, Ti, Zr, Hf, Sc, Y, V, and Nb, or each of them. Method.

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