JP2007251046A - Semiconductor device and circuit board - Google Patents

Semiconductor device and circuit board Download PDF

Info

Publication number
JP2007251046A
JP2007251046A JP2006075331A JP2006075331A JP2007251046A JP 2007251046 A JP2007251046 A JP 2007251046A JP 2006075331 A JP2006075331 A JP 2006075331A JP 2006075331 A JP2006075331 A JP 2006075331A JP 2007251046 A JP2007251046 A JP 2007251046A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
semiconductor chip
electrode terminal
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006075331A
Other languages
Japanese (ja)
Inventor
Hidetsugu Nezu
英継 祢津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2006075331A priority Critical patent/JP2007251046A/en
Publication of JP2007251046A publication Critical patent/JP2007251046A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a circuit board planning to improve a heat dissipation. <P>SOLUTION: The semiconductor device 10 is equipped with: a semiconductor chip 11 provided with a primary principal plane on which a first electrode is arranged and a secondary principal plane on which a second electrode is arranged; a primary electrode terminal 12 which is arranged on the primary principal plane and is electrically connected with the first electrode and is thermally connected with the semiconductor chip 11; secondary electrode terminals 13, 14; a primary section which is arranged on the secondary principal plane and is electrically connected with the second electrode; a secondary section which electrically connects the primary section with the secondary electrode terminals 13, 14; and a tertiary section which is electrically connected with primary sections 13A, 14A. Moreover, the semiconductor device 10 is equipped with a sealing member 17 which seals connectors 15, 16 constituted by a conductive material, the semiconductor chip 11, the primary section 1 and the secondary section and exposes at least a part of the tertiary section as an electrode terminal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は，半導体装置および回路基板に関する。   The present invention relates to a semiconductor device and a circuit board.

コネクタ型の半導体装置に関する技術が公開されている（例えば，特許文献１参照）。コネクタ型の半導体装置は，例えば，外部との接続のための電極端子と半導体素子との間をコネクタで電気的に接続して構成され，プリント基板に搭載して用いられる。
従来のコネクタ型の半導体装置での放熱は，半導体装置の裏面によってなされる。即ち，半導体装置の裏面からプリント基板への熱伝導により，半導体装置を冷却している。
しかしながら，半導体装置の裏面からの放熱のみでは，必ずしも半導体装置の冷却が充分とは限らない。
特開２００４−３１５１６ A technique related to a connector-type semiconductor device is disclosed (for example, see Patent Document 1). A connector-type semiconductor device is configured, for example, by electrically connecting an electrode terminal for connection with the outside and a semiconductor element with a connector, and is used by being mounted on a printed circuit board.
Heat dissipation in the conventional connector type semiconductor device is performed by the back surface of the semiconductor device. That is, the semiconductor device is cooled by heat conduction from the back surface of the semiconductor device to the printed circuit board.
However, cooling of the semiconductor device is not always sufficient only by heat radiation from the back surface of the semiconductor device.
JP 2004-31516 A

本発明は，放熱の向上を図った半導体装置および回路基板を提供することを目的とする。   An object of the present invention is to provide a semiconductor device and a circuit board that improve heat dissipation.

本発明の一態様に係る半導体装置は，第１の電極が配置される第１の主面と，第２の電極が配置される第２の主面と，を備える半導体チップと，前記第１の主面上に配置され，前記第１の電極と電気的に接続され，かつ前記半導体チップと熱的に接続される第１の電極端子と，第２の電極端子と，前記第２の主面上に配置され，前記第２の電極と電気的に接続される第１の部分と，前記第１の部分と前記第２の電極端子とを電気的に接続する第２の部分と，前記第１の部分と電気的に接続される第３の部分と，を備え，かつ導電性材料から構成されるコネクタと，前記半導体チップと，前記第１の部分と，前記第２の部分と，を封止し，前記第３の部分の少なくとも一部を電極端子として露出させる封止部材と，を具備することを特徴とする。   A semiconductor device according to an aspect of the present invention includes a semiconductor chip including a first main surface on which a first electrode is disposed and a second main surface on which a second electrode is disposed; A first electrode terminal, a second electrode terminal, and a second main terminal that are electrically connected to the first electrode and thermally connected to the semiconductor chip. A first portion disposed on a surface and electrically connected to the second electrode; a second portion electrically connecting the first portion and the second electrode terminal; A third portion electrically connected to the first portion and made of a conductive material; the semiconductor chip; the first portion; the second portion; And a sealing member that exposes at least a part of the third portion as an electrode terminal.

本発明によれば，放熱の向上を図った半導体装置および回路基板を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device and circuit board which aimed at the improvement of heat dissipation can be provided.

以下，図面を参照して，本発明の実施の形態を詳細に説明する。
（第１の実施の形態）
本発明の第１の実施形態を説明する。
図１は，本発明の第１実施形態に係る半導体装置１０を上方から見た状態を表す上面図である。図１は，封止部１７の一部を除外した状態を表す。なお，これは後述の上面図（図３〜図５，図７）でも同様である。図２は，半導体装置１０を図１のII−IIで切断した状態を表す断面図である。
半導体装置１０は，半導体チップ１１，電極端子１２，１３，１４，コネクタ１５，１６，封止部１７を備える。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 is a top view showing a state in which the semiconductor device 10 according to the first embodiment of the present invention is viewed from above. FIG. 1 shows a state in which a part of the sealing portion 17 is excluded. This also applies to top views (FIGS. 3 to 5 and 7) described later. FIG. 2 is a cross-sectional view illustrating a state in which the semiconductor device 10 is cut along II-II in FIG.
The semiconductor device 10 includes a semiconductor chip 11, electrode terminals 12, 13 and 14, connectors 15 and 16, and a sealing portion 17.

半導体チップ（半導体装置本体）１１は，半導体基板に３端子素子であるＭＯＳ−ＦＥＴ（Field Effect Transistor）が形成されたものである。半導体チップ１１には，電極端子１２，１３，１４に対応して図示しないドレイン電極，ソース電極，ゲート電極を有する。即ち，半導体チップ１１の下面にドレイン電極が，半導体チップ１１の上面にソース電極，ゲート電極が配置される。これらドレイン電極，ソース電極，ゲート電極への信号の印加によりＭＯＳ−ＦＥＴが駆動される。なお，このＭＯＳ−ＦＥＴは，高電力用の半導体素子である。   The semiconductor chip (semiconductor device body) 11 is a semiconductor substrate on which a MOS-FET (Field Effect Transistor) that is a three-terminal element is formed. The semiconductor chip 11 has a drain electrode, a source electrode, and a gate electrode (not shown) corresponding to the electrode terminals 12, 13, and 14. That is, the drain electrode is disposed on the lower surface of the semiconductor chip 11, and the source electrode and the gate electrode are disposed on the upper surface of the semiconductor chip 11. The MOS-FET is driven by applying a signal to the drain electrode, the source electrode, and the gate electrode. The MOS-FET is a high power semiconductor element.

電極端子１２は，半導体チップ１１のドレイン電極との電気的接続および半導体チップ１１からの放熱のための部材である。電極端子１２は，例えば，金属（一例として，銅，銅系の合金）からなる導体平板から構成される。電極端子１２は，半導体チップ１１より縦横のサイズが大きい，半導体チップ１１からの効率的な放熱および半導体チップ１１等の安定的な載置のためである。   The electrode terminal 12 is a member for electrical connection with the drain electrode of the semiconductor chip 11 and heat dissipation from the semiconductor chip 11. The electrode terminal 12 is composed of a conductive flat plate made of, for example, metal (for example, copper or a copper-based alloy). The electrode terminals 12 are larger in size than the semiconductor chip 11 in order to efficiently dissipate heat from the semiconductor chip 11 and to stably place the semiconductor chip 11 and the like.

電極端子１２は，半導体チップ１１の下面に配置され，半導体チップ１１を載置する。電極端子１２は，ハンダ等の接続部１８Ａにより，半導体チップ１１のドレイン電極と電気的に接続される。この接続部１８Ａは，半導体チップ１１のほぼ全面において半導体チップ１１と電極端子１２とを接続する。即ち，この接続部は，半導体チップ１１と電極端子１２とを電気的に接続と共に，熱的にも接続する役割を担う。   The electrode terminal 12 is disposed on the lower surface of the semiconductor chip 11 and places the semiconductor chip 11 thereon. The electrode terminal 12 is electrically connected to the drain electrode of the semiconductor chip 11 through a connecting portion 18A such as solder. The connecting portion 18 </ b> A connects the semiconductor chip 11 and the electrode terminal 12 on almost the entire surface of the semiconductor chip 11. In other words, the connecting portion plays a role of connecting the semiconductor chip 11 and the electrode terminal 12 electrically as well as electrically.

電極端子１３，１４はそれぞれ，半導体チップ１１のソース電極およびゲート電極との電気的接続のための部材である。電極端子１３，１４は，例えば，金属（一例として，銅，銅系の合金）からなる導体平板から構成される。電極端子１３，１４はそれぞれ，部分１３Ａ〜１３Ｃおよび部分１４Ａ〜１４Ｃに区分することができる。例えば，金属（一例として銅，銅系の合金）からなる導体平板を折り曲げることで，部分１３Ａ〜１３Ｃおよび部分１４Ａ〜１４Ｃに区分される電極端子１３，１４を一体的に形成できる。   The electrode terminals 13 and 14 are members for electrical connection with the source electrode and the gate electrode of the semiconductor chip 11, respectively. The electrode terminals 13 and 14 are made of, for example, a conductive flat plate made of metal (for example, copper or a copper-based alloy). The electrode terminals 13 and 14 can be divided into portions 13A to 13C and portions 14A to 14C, respectively. For example, the electrode terminals 13 and 14 divided into the portions 13A to 13C and the portions 14A to 14C can be integrally formed by bending a conductor flat plate made of metal (for example, copper or a copper-based alloy).

部分１３Ａ，１４Ａはそれぞれ，封止部１７に埋め込み固定され，コネクタ１５，１６によって半導体チップ１１のソース電極およびゲート電極と電気的に接続される。部分１３Ｂ，１４Ｂはそれぞれ，部分１３Ａ，１３Ｃおよび部分１４Ａ，１４Ｃを電気的に接続する。部分１３Ｃ，１４Ｃは，プリント基板等と接続される部分である。   The portions 13A and 14A are embedded and fixed in the sealing portion 17, and are electrically connected to the source electrode and the gate electrode of the semiconductor chip 11 by the connectors 15 and 16, respectively. The portions 13B and 14B electrically connect the portions 13A and 13C and the portions 14A and 14C, respectively. The parts 13C and 14C are parts connected to a printed circuit board or the like.

コネクタ１５は，半導体チップ１１のソース電極と電極端子１３との電気的接続および半導体チップ１１の放熱のための部材である。コネクタ１５は，部分１５Ａ〜１５Ｅに区分される。例えば，金属（一例として，銅やアルミニウム）からなる導体薄板を折り曲げることで，部分１５Ａ〜１５Ｅに区分されるコネクタ１５を一体的に構成できる。   The connector 15 is a member for electrical connection between the source electrode of the semiconductor chip 11 and the electrode terminal 13 and heat dissipation of the semiconductor chip 11. The connector 15 is divided into portions 15A to 15E. For example, the connector 15 divided into the portions 15A to 15E can be integrally configured by bending a conductive thin plate made of metal (for example, copper or aluminum).

部分１５Ａは，ハンダ等の接続部１８Ｂにより，半導体チップ１１のソース電極と電気的に接続される。この接続部１８Ｂは，部分１５Ａのほぼ全面において半導体チップ１１と部分１５Ａとを接続する。即ち，この接続部１８Ｂは，半導体チップ１１と部分１５Ａとを電気的に接続と共に，熱的にも接続する役割を担う。
部分１５Ｂは，部分１５Ａ，１５Ｃを電気的に接続する。
部分１５Ｃは，ハンダ等の接続部１８Ｃにより，電極端子１３と電気的に接続される。 The portion 15A is electrically connected to the source electrode of the semiconductor chip 11 by a connecting portion 18B such as solder. The connecting portion 18B connects the semiconductor chip 11 and the portion 15A over almost the entire surface of the portion 15A. That is, the connecting portion 18B plays a role of connecting the semiconductor chip 11 and the portion 15A electrically as well as thermally.
The part 15B electrically connects the parts 15A and 15C.
The portion 15C is electrically connected to the electrode terminal 13 through a connecting portion 18C such as solder.

部分１５Ｄは，部分１５Ａ，１５Ｅを電気的および熱的に接続する。
部分１５Ｅは，半導体チップ１１からの放熱のための機能を有する部分（放熱板）である。部分１５Ｅをプリント基板等に熱的に接続することで，半導体チップ１１からの熱が部分１５Ａ，１５Ｄ，１５Ｅを通って，プリント基板等に放出される。部分１５Ｅは，半導体チップ１１より大きな幅Ｄを有する。半導体チップ１１からの効率的な放熱のためである。また，部分１５Ｅは，ソース電極への信号入力用の電極端子としての機能を有する。 The part 15D electrically and thermally connects the parts 15A and 15E.
The portion 15E is a portion (heat radiating plate) having a function for radiating heat from the semiconductor chip 11. By thermally connecting the portion 15E to a printed circuit board or the like, heat from the semiconductor chip 11 is released to the printed circuit board or the like through the portions 15A, 15D, and 15E. The portion 15E has a larger width D than the semiconductor chip 11. This is for efficient heat dissipation from the semiconductor chip 11. Further, the portion 15E functions as an electrode terminal for signal input to the source electrode.

コネクタ１６は，半導体チップ１１のゲート電極と電極端子１４との電気的接続のための部材である。コネクタ１６は，部分１６Ａ〜１６Ｃに区分される。例えば，金属（一例として，銅，銅系の合金）からなる導体薄板を折り曲げることで，部分１６Ａ〜１６Ｃに区分されるコネクタ１６を一体的に構成できる。   The connector 16 is a member for electrical connection between the gate electrode of the semiconductor chip 11 and the electrode terminal 14. The connector 16 is divided into portions 16A to 16C. For example, the connector 16 divided into the portions 16A to 16C can be integrally formed by bending a conductive thin plate made of metal (for example, copper or a copper-based alloy).

部分１６Ａは，ハンダ等の接続部により，半導体チップ１１のゲート電極と電気的に接続される。
部分１６Ｂは，部分１６Ａ，１６Ｃを電気的に接続する。
部分１６Ｃは，ハンダ等の接続部により，電極端子１４と電気的に接続される。 The portion 16A is electrically connected to the gate electrode of the semiconductor chip 11 through a connection portion such as solder.
The portion 16B electrically connects the portions 16A and 16C.
The portion 16C is electrically connected to the electrode terminal 14 through a connection portion such as solder.

封止部１７（パッケージ）は，半導体チップ１１，コネクタ１６の全体および電極端子１２〜１４，コネクタ１５の一部を封止する。これらを保護，固定するためである。封止部１７は，略直方体状の形状を有し，その側面からコネクタ１５の部分１５Ｄ，１５Ｅが延伸している。封止部１７には，例えば，エポキシ樹脂等の樹脂材料（封止材料）を用いることができる。   The sealing part 17 (package) seals the semiconductor chip 11, the entire connector 16 and the electrode terminals 12 to 14 and a part of the connector 15. This is to protect and fix these. The sealing portion 17 has a substantially rectangular parallelepiped shape, and the portions 15D and 15E of the connector 15 extend from the side surface. For the sealing portion 17, for example, a resin material (sealing material) such as an epoxy resin can be used.

半導体装置１０は，次のようにして作成できる。即ち，電極端子１２上にドレイン電極を介して半導体チップ１１を固定し，コネクタ１５，１６を介して，ソース電極，ゲート電極に電極端子１３，１４を接続し，樹脂等の封止材料で封止する。なお，型を用いたモールド加工をこの封止に利用することができる。   The semiconductor device 10 can be created as follows. That is, the semiconductor chip 11 is fixed on the electrode terminal 12 via the drain electrode, the electrode terminals 13 and 14 are connected to the source electrode and the gate electrode via the connectors 15 and 16, and sealed with a sealing material such as resin. Stop. Note that mold processing using a mold can be used for this sealing.

（回路基板）
図３は，半導体装置１０を搭載する回路基板２０を上方から見た状態を表す上面図である。なお，見やすさのために，導体パターン２２〜２５の表面にハッチングを付している。
回路基板２０は，基板２１，導体パターン２２〜２５を有し，２つの半導体装置１０（１），１０（２）が並列して配置される。２つの半導体装置１０（１），１０（２）を電気的に並列に接続することで，大電力への対応および電力損失の低減を図っている。 (Circuit board)
FIG. 3 is a top view illustrating a state in which the circuit board 20 on which the semiconductor device 10 is mounted is viewed from above. For the sake of easy viewing, the surfaces of the conductor patterns 22 to 25 are hatched.
The circuit board 20 includes a board 21 and conductor patterns 22 to 25, and two semiconductor devices 10 (1) and 10 (2) are arranged in parallel. The two semiconductor devices 10 (1) and 10 (2) are electrically connected in parallel to cope with large power and reduce power loss.

基板２１は，例えば，ガラスエポキシ系の材料から構成されるプリント基板である。
導体パターン２２〜２５は，基板２１上に配置され，例えば，金属（一例として，銅，銅系の合金）からなる導体膜から構成される。
導体パターン２２は，電極端子１２と対応して配置され，ハンダ等の接続部により，電極端子１２と電気的および熱的に接続される。
導体パターン２３は，電極端子１３と対応して配置され，ハンダ等の接続部により，電極端子１３と電気的に接続される。
導体パターン２４は，電極端子１４と対応して配置され，ハンダ等の接続部により，電極端子１４と電気的に接続される。
導体パターン２５は，コネクタ１５の部分１５Ｅと対応して配置され，ハンダ等の接続部により，部分１５Ｅと電気的に接続される。 The board | substrate 21 is a printed circuit board comprised from a glass epoxy type material, for example.
The conductor patterns 22 to 25 are disposed on the substrate 21 and are made of a conductor film made of, for example, metal (for example, copper or a copper-based alloy).
The conductor pattern 22 is disposed corresponding to the electrode terminal 12 and is electrically and thermally connected to the electrode terminal 12 by a connecting portion such as solder.
The conductor pattern 23 is disposed corresponding to the electrode terminal 13 and is electrically connected to the electrode terminal 13 through a connecting portion such as solder.
The conductor pattern 24 is disposed corresponding to the electrode terminal 14 and is electrically connected to the electrode terminal 14 through a connection portion such as solder.
The conductor pattern 25 is disposed corresponding to the portion 15E of the connector 15, and is electrically connected to the portion 15E by a connecting portion such as solder.

半導体装置１０では，コネクタ１５の部分１５Ｅおよび電極端子１２によって，基板２１と熱的に接続される。この結果，半導体装置１０から効率的に放熱がなされる。即ち，コネクタ１５に放熱板の機能を有する部分（部分１５Ｄ，１５Ｅ）が付加され，半導体チップ１１の表面からコネクタ１５を介して放熱がなされる。
また，半導体装置１０では，導体パターン２３，２５の双方によって，電極端子１３およびコネクタ１５の部分１５Ｅを介して，半導体装置１０のソース電極に信号を入力している。このため，導体パターン２３の幅Ｗを狭くしても充分な信号量を確保することが容易となる。 The semiconductor device 10 is thermally connected to the substrate 21 by the portion 15E of the connector 15 and the electrode terminal 12. As a result, heat is efficiently radiated from the semiconductor device 10. That is, portions (parts 15D and 15E) having a function of a heat radiating plate are added to the connector 15, and heat is radiated from the surface of the semiconductor chip 11 through the connector 15.
In the semiconductor device 10, a signal is input to the source electrode of the semiconductor device 10 through the electrode terminal 13 and the portion 15 </ b> E of the connector 15 by both the conductor patterns 23 and 25. For this reason, even if the width W of the conductor pattern 23 is narrowed, it is easy to ensure a sufficient signal amount.

（第２の実施の形態）
本発明の第２の実施形態を説明する。
図４は，本発明の第２実施形態に係る半導体装置３０を上方から見た状態を表す上面図である。図５は，半導体装置３０を図４のV−Vで切断した状態を表す断面図である。 (Second Embodiment)
A second embodiment of the present invention will be described.
FIG. 4 is a top view illustrating a state in which the semiconductor device 30 according to the second embodiment of the present invention is viewed from above. FIG. 5 is a cross-sectional view illustrating a state in which the semiconductor device 30 is cut along VV in FIG.

半導体装置３０の電極端子３３，３４の部分３３Ｃ，３４Ｃが曲げられず，封止部３７から真横に突き出ている。コネクタ３５の部分３５Ｅが，曲げられず，封止部３７から真横に突き出ている。また，部分３５Ｅに開口３９が形成されている。
部分３３Ｃ，３４Ｃ，部分３５Ｅが封止部３７の側面から真横一直線に突き出ているのは，他の回路構成要素との接続の関係である。開口３９は，放熱用の部材との固定のためのネジ穴として用いられる。
外部との接続関係を除いて，第２の実施形態は，第１の実施形態と同様な構成を有するので，第２の実施形態の詳細な説明を省略する。 The portions 33 </ b> C and 34 </ b> C of the electrode terminals 33 and 34 of the semiconductor device 30 are not bent and protrude directly from the sealing portion 37. The portion 35E of the connector 35 is not bent and protrudes directly from the sealing portion 37. An opening 39 is formed in the portion 35E.
The portions 33C, 34C, and the portion 35E protrude in a straight line from the side surface of the sealing portion 37 because of the connection with other circuit components. The opening 39 is used as a screw hole for fixing to the member for heat dissipation.
Except for external connection, the second embodiment has the same configuration as that of the first embodiment, and thus the detailed description of the second embodiment is omitted.

（第３の実施の形態）
本発明の第３の実施形態を説明する。
図６は，本発明の第３実施形態に係る半導体装置４０を上方から見た状態を表す上面図である。図７は，半導体装置４０を図７のVI−VIで切断した状態を表す断面図である。
半導体装置４０は，半導体チップ４１，電極端子４２，４３，コネクタ４５，封止部４７を備える。 (Third embodiment)
A third embodiment of the present invention will be described.
FIG. 6 is a top view illustrating a state where the semiconductor device 40 according to the third embodiment of the present invention is viewed from above. 7 is a cross-sectional view illustrating a state in which the semiconductor device 40 is cut along VI-VI in FIG.
The semiconductor device 40 includes a semiconductor chip 41, electrode terminals 42 and 43, a connector 45, and a sealing portion 47.

半導体チップ４１は，半導体基板に２端子素子であるダイオードが形成されたものである。半導体チップ４１には，電極端子４２，４３に対応して図示しないアノード電極，カソード電極を有する。即ち，半導体チップ４１の下面にカソード電極が，半導体チップ４１の上面にアノード電極が配置される。これらアノード電極，カソード電極への信号の印加によりダイオードが駆動される。   The semiconductor chip 41 is a semiconductor substrate on which a diode that is a two-terminal element is formed. The semiconductor chip 41 has an anode electrode and a cathode electrode (not shown) corresponding to the electrode terminals 42 and 43. That is, the cathode electrode is disposed on the lower surface of the semiconductor chip 41 and the anode electrode is disposed on the upper surface of the semiconductor chip 41. The diode is driven by the application of signals to the anode and cathode electrodes.

半導体装置４０は，半導体装置１０と端子数が異なることから，半導体装置１０の電極端子１４，コネクタ１６に対応する構成要素を有しない。また，構成要素が減った関係で，電極端子４３およびコネクタ４５の形状が半導体装置１０の電極端子１３およびコネクタ１５と相違する。   Since the number of terminals is different from that of the semiconductor device 10, the semiconductor device 40 does not have components corresponding to the electrode terminals 14 and the connectors 16 of the semiconductor device 10. Further, the shape of the electrode terminal 43 and the connector 45 is different from that of the electrode terminal 13 and the connector 15 of the semiconductor device 10 due to the reduced number of components.

以上を除いて，第３の実施形態は，第１の実施形態と同様な構成を有するので，第３の実施形態の詳細な説明を省略する。
半導体装置４０は，コネクタ４５の部分４５Ｅおよび電極端子４２によって，基板と熱的に接続可能であり，効率的な放熱が可能である。また，コネクタ４５の部分４５Ｅおよび電極端子４３を介して，半導体装置４０のカソード電極への信号入力が可能である。 Except for the above, the third embodiment has a configuration similar to that of the first embodiment, and thus detailed description of the third embodiment is omitted.
The semiconductor device 40 can be thermally connected to the substrate by the portion 45E of the connector 45 and the electrode terminal 42, and efficient heat dissipation is possible. Further, a signal can be input to the cathode electrode of the semiconductor device 40 via the portion 45E of the connector 45 and the electrode terminal 43.

（その他の実施形態）
本発明の実施形態は上記の実施形態に限られず拡張，変更可能であり，拡張，変更した実施形態も本発明の技術的範囲に含まれる。
上記実施形態では，３端子素子としてＭＯＳ−ＦＥＴを挙げている。本発明の実施形態はＭＯＳ−ＦＥＴのみならず，３端子素子一般，例えば，バイポーラトランジスタにも適用できる。
また，ダイオードは，ツェナーダイオードであっても良い。 (Other embodiments)
Embodiments of the present invention are not limited to the above-described embodiments, and can be expanded and modified. The expanded and modified embodiments are also included in the technical scope of the present invention.
In the above embodiment, a MOS-FET is cited as the three-terminal element. The embodiment of the present invention can be applied not only to a MOS-FET but also to a general three-terminal element, for example, a bipolar transistor.
The diode may be a Zener diode.

本発明の第１実施形態に係る半導体装置を上方から見た状態を表す上面図である。It is a top view showing the state which looked at the semiconductor device concerning a 1st embodiment of the present invention from the upper part. 本発明の第１実施形態に係る半導体装置の断面の状態を表す断面図である。It is sectional drawing showing the state of the cross section of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置を有する回路基板を上方から見た状態を表す上面図である。It is a top view showing the state which looked at the circuit board which has a semiconductor device concerning a 1st embodiment of the present invention from the upper part. 本発明の第２実施形態に係る半導体装置を上方から見た状態を表す上面図である。It is a top view showing the state which looked at the semiconductor device concerning a 2nd embodiment of the present invention from the upper part. 本発明の第２実施形態に係る半導体装置の断面の状態を表す断面図である。It is sectional drawing showing the state of the cross section of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る半導体装置を上方から見た状態を表す上面図である。It is a top view showing the state which looked at the semiconductor device concerning a 3rd embodiment of the present invention from the upper part. 本発明の第３実施形態に係る半導体装置の断面の状態を表す断面図である。It is sectional drawing showing the state of the cross section of the semiconductor device which concerns on 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１０…半導体装置，１１…半導体チップ，１２，１３，１４…電極端子，１５，１６…コネクタ，１７…封止部，２０…回路基板，２１…基板，２２〜２５…導体パターン   DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Semiconductor chip, 12, 13, 14 ... Electrode terminal, 15, 16 ... Connector, 17 ... Sealing part, 20 ... Circuit board, 21 ... Substrate, 22-25 ... Conductor pattern

Claims (5)

第１の電極が配置される第１の主面と，第２の電極が配置される第２の主面と，を備える半導体チップと，
前記第１の主面上に配置され，前記第１の電極と電気的に接続され，かつ前記半導体チップと熱的に接続される第１の電極端子と，
第２の電極端子と，
前記第２の主面上に配置され，前記第２の電極と電気的に接続される第１の部分と，前記第１の部分と前記第２の電極端子とを電気的に接続する第２の部分と，前記第１の部分と電気的に接続される第３の部分と，を備え，かつ導電性材料から構成されるコネクタと，
前記半導体チップと，前記第１の部分と，前記第２の部分と，を封止し，前記第３の部分の少なくとも一部を電極端子として露出させる封止部材と，
を具備することを特徴とする半導体装置。 A semiconductor chip comprising: a first main surface on which a first electrode is disposed; and a second main surface on which a second electrode is disposed;
A first electrode terminal disposed on the first main surface, electrically connected to the first electrode, and thermally connected to the semiconductor chip;
A second electrode terminal;
A first portion disposed on the second main surface and electrically connected to the second electrode; a second portion electrically connecting the first portion and the second electrode terminal; A connector made of a conductive material, and a third portion electrically connected to the first portion;
A sealing member that seals the semiconductor chip, the first portion, and the second portion, and exposes at least a portion of the third portion as an electrode terminal;
A semiconductor device comprising: 前記第３の部分の幅が，前記半導体チップの幅より大きい
ことを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein a width of the third portion is larger than a width of the semiconductor chip. 前記第２の主面上に第３の電極が配置され，
第３の電極端子と，
前記第３の電極と前記第３の電極端子とを電気的に接続する接続部と，をさらに具備する
ことを特徴とする請求項１または２記載の半導体装置。 A third electrode is disposed on the second main surface;
A third electrode terminal;
The semiconductor device according to claim 1, further comprising a connection portion that electrically connects the third electrode and the third electrode terminal. 前記コネクタの第３の部分が，前記封止部材の側面から延伸される
ことを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。 4. The semiconductor device according to claim 1, wherein a third portion of the connector extends from a side surface of the sealing member. 5. 第１の電極が配置される第１の主面と，第２の電極が配置される第２の主面と，を備える半導体チップと，
前記第１の主面上に配置され，前記第１の電極と電気的に接続される第１の電極端子と，
第２の電極端子と，
前記第２の主面上に配置され，前記第２の電極と電気的に接続される第１の部分と，前記第１の部分と前記第２の電極端子とを電気的に接続する第２の部分と，前記第１の部分と電気的に接続される第３の部分と，を備え，かつ導電性材料から構成されるコネクタと，
前記半導体チップと，前記第１の部分と，前記第２の部分と，を封止し，前記第３の部分の少なくとも一部を露出させる封止部材と，
前記第１の電極端子を載置する基板と，
前記基板と前記第１の電極端子との間に配置され，前記第１の電極端子と電気的に接続される第１の導体パターンと，
前記基板上に配置され，前記第２の電極端子と電気的に接続される第２の導体パターンと，
前記基板上に配置され，前記コネクタの第３の部分と電気的に接続される第３の導体パターンと，
を具備することを特徴とする回路基板。 A semiconductor chip comprising: a first main surface on which a first electrode is disposed; and a second main surface on which a second electrode is disposed;
A first electrode terminal disposed on the first main surface and electrically connected to the first electrode;
A second electrode terminal;
A first portion disposed on the second main surface and electrically connected to the second electrode; a second portion electrically connecting the first portion and the second electrode terminal; A connector made of a conductive material, and a third portion electrically connected to the first portion;
A sealing member that seals the semiconductor chip, the first portion, and the second portion, and exposes at least a portion of the third portion;
A substrate on which the first electrode terminal is placed;
A first conductor pattern disposed between the substrate and the first electrode terminal and electrically connected to the first electrode terminal;
A second conductor pattern disposed on the substrate and electrically connected to the second electrode terminal;
A third conductor pattern disposed on the substrate and electrically connected to a third portion of the connector;
A circuit board comprising:
JP2006075331A 2006-03-17 2006-03-17 Semiconductor device and circuit board Withdrawn JP2007251046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006075331A JP2007251046A (en) 2006-03-17 2006-03-17 Semiconductor device and circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006075331A JP2007251046A (en) 2006-03-17 2006-03-17 Semiconductor device and circuit board

Publications (1)

Publication Number Publication Date
JP2007251046A true JP2007251046A (en) 2007-09-27

Family

ID=38594987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006075331A Withdrawn JP2007251046A (en) 2006-03-17 2006-03-17 Semiconductor device and circuit board

Country Status (1)

Country Link
JP (1) JP2007251046A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014068935A1 (en) * 2012-11-05 2014-05-08 日本精工株式会社 Semiconductor module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014068935A1 (en) * 2012-11-05 2014-05-08 日本精工株式会社 Semiconductor module
JP5892250B2 (en) * 2012-11-05 2016-03-23 日本精工株式会社 Semiconductor module
US9402311B2 (en) 2012-11-05 2016-07-26 Nsk Ltd. Semiconductor module

Similar Documents

Publication Publication Date Title
EP2073263A1 (en) Electronic device
US7804105B2 (en) Side view type LED package
JP2008091714A (en) Semiconductor device
JP6528620B2 (en) Circuit structure and electrical connection box
US20180027645A1 (en) Substrate unit
JP2015005681A (en) Semiconductor device and method of manufacturing the same
KR20110134258A (en) Semiconductor module and semiconductor device
JP2006086536A (en) Electronic control device
US10674596B2 (en) Electronic component, electronic component manufacturing method, and mechanical component
US20070104926A1 (en) Circuit device in particular frequency converter
JP2002171087A (en) Electronic equipment
JP2007251046A (en) Semiconductor device and circuit board
JP2006311714A (en) Switching unit
JP2008028311A (en) Semiconductor device
JP2000252657A (en) Heat dissipation unit for control apparatus
JP2005354118A (en) Hybrid ic device
JP2006294729A (en) Semiconductor device
JP2011066281A (en) Heat generating device
US20240096738A1 (en) Power semiconductor component and method for producing a power semiconductor component
JP2014229804A (en) Electronic control device
JP2014103270A (en) Semiconductor module
JP2018148125A (en) Electronic equipment and manufacturing method of electronic equipment
JP2009188192A (en) Circuit device
US9508639B2 (en) Package-in-substrate, semiconductor device and module
JP2013038119A (en) Attachment structure of module

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20090602