JP2007250007A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a band gap circuit capable of generating optional voltage, without being restricted by band gap voltage. <P>SOLUTION: The semiconductor integrated circuit includes a current generation circuit for generating first current that is substantially proportional to absolute temperature; and a voltage generation circuit for generating a reference voltage that does not substantially depend upon the absolute temperature, on the basis of the first current generated by the current generation circuit, wherein the voltage generation circuit includes a first element for generating voltage that is substantially in negative proportion to the absolute temperature; a resistance voltage division circuit connected to the first element in parallel, a second element connected to the parallel connection of the first element and the resistance voltage division circuit to supply second current that is proportional to the first current; and a third element, connected to a node between resistances of the resistance voltage division circuit, to supply third current that is proportional to the first current. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generally relates to semiconductor integrated circuits, and particularly relates to a band gap circuit capable of low voltage operation, a bias current generation circuit, and a low voltage detection circuit using the band gap circuit.

  In analog integrated circuits, when a reference voltage that does not depend on temperature or power supply voltage is required, a reference voltage circuit called a band gap circuit is widely used. Even in a CMOS analog integrated circuit that can be easily mixed with a digital circuit, the bandgap circuit is widely used as a circuit that generates a stable reference voltage.

  In a bandgap circuit, a reference voltage independent of temperature is obtained by adding a forward-biased pn junction potential and a voltage proportional to absolute temperature (T) (commonly referred to as PTAT: Proportional To Absolute Temperature). Is generated. Various circuits for realizing such operations have been put to practical use.

  FIG. 1 is a diagram illustrating an example of a configuration of a conventional bandgap circuit. FIG. 2 is a diagram showing another example of the configuration of a conventional bandgap circuit. FIG. 3 is a diagram showing an example of the configuration of a conventional bias current generating circuit.

  In FIG. 1, Q1, Q2 and Q3 are pnp bipolar transistors, R1 and R2 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, NM1 and NM2 are NMOS transistors, PM1, PM2, and PM3 are PMOS transistors, 10 is a bias potential of the PMOS transistor, 20 is a bias potential of the NMOS transistor, and 30 to 33 are internal nodes.

  For example, it is assumed that W1 / L (W: gate width, L: gate length) of PM1, PM2, and PM3 is equal, and W / L of NM1 and NM2 are also equal. Furthermore, the emitter junction area ratio between Q1 and Q2 is, for example, 1: 6.

  When the base-emitter voltage of the bipolar transistor or the forward voltage of the pn junction is expressed by Vbe, it is known that the relationship between the forward voltage of the pn junction and the absolute temperature T can be approximated by the following equation (1). ing.

Vbe = Veg−aT (1)
Here, Vbe is a forward voltage of a pn junction, Veg is a band gap voltage of silicon, which is about 1.2 V, a is a temperature dependence of Vbe, about 2 mV / ° C., and T is an absolute temperature.

  Further, it is known that the relationship between the emitter current I of the bipolar transistor and the voltage Vbe can be approximated by the following equation (2).

I = I0exp (qVbe / kT) (2)
Here, I is the bipolar transistor emitter current or diode current, I0 is a constant (proportional to the area), q is the electron charge, and k is the Boltzmann constant.

In the circuit of FIG. 2, since the gate electrodes of PM1 and PM2 are common, the currents flowing through PM1, PM2, NM1, NM2, Q1, and Q2 are equal. Since the currents flowing through NM1 and NM2 are equal, the potentials of internal nodes 30 and 31 are equal. Since the junction area ratio between Q1 and Q2 is 1: 6, if Vbe of Q1 is Vbe1, and Vbe of Q2 is Vbe2,
Current of Q1 = I0exp (qVbe1 / kT)
Current of Q2 = 6I0exp (qVbe2 / kT)
It is. When the current of Q1 is equal to the current of Q2, and Vbe1-Vbe2 is obtained, the potential difference VR1 between both ends of the resistor R1 is expressed by the following formula (3).

VR1 = (kT / q) ln (6) (3)
Since the potential difference VR1 between both ends of the resistor R1 is expressed by the equation (3), the current Ip flowing through PM1 and PM2 is
Ip = (1 / R1) (kT / q) ln (6) (4)
(R1: resistance value of resistor R1). Since the same current as this current flows to PM3, the voltage drop VR2 at the resistor R2 is
VR2 = (R2 / R1) (kT / q) ln (6) (5)
(R2: resistance value of the resistor R2).

  The sum of the voltage drop VR2 at the resistor R2 and Vbe of Q3 becomes the reference voltage Vref. The forward voltage Vbe of the pn junction has a negative temperature dependency that decreases as the temperature rises (equation (1)), and the voltage drop VR2 at the resistor R2 increases in proportion to the temperature. By selecting, it is possible to design so that the value of the reference voltage Vref does not depend on the temperature. The value of the reference voltage Vref at that time is about 1.2 V corresponding to the band gap voltage of silicon.

  As described above, in the conventional circuit of FIG. 1, PM1, PM2, PM3, NM1, NM2, the junction area ratio of Q1 and Q2, and the values of R2 and R1 are appropriately selected, so that the bandgap voltage independent of temperature can be set relatively. It can be generated with a simple circuit.

  Although the configuration of the conventional circuit of FIG. 2 is different, a voltage independent of temperature can be generated based on the same principle. The circuit of FIG. 2 is disclosed in Patent Document 1 or Patent Document 2. Similar circuit configurations are shown in Patent Document 3, Patent Document 4, Patent Document 5, Patent Document 6, Patent Document 7, Non-Patent Document 1, and the like.

  In FIG. 2, D1 is a diode, R1, R2, and R3 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, NM3 and NM4 are NMOS transistors, PM1 to PM3, and PM7. , PM8 is a PMOS transistor, 10 is a bias potential of the PMOS transistor, 21 is a bias potential of the NMOS transistor, 33, 35, and 90 are internal nodes. In FIG. 2, elements having the same functions as in FIG. Referenced with the same sign.

  For example, it is assumed that W / L (W: gate width, L: gate length) of PM1, PM2, and PM3 is equal. Further, the W / L ratio of NM3 and NM4 is set to 1: 6, for example. NM3 and NM4 are designed to operate in the subthreshold region.

  When the gate-source voltage of the NMOS transistor is represented by Vgs, it is known that the relationship between the drain current ID and the voltage Vgs in the subthreshold region can be approximated by Expression (6).

ID = I0exp (qVgs / nkT) (6)
Where ID is a drain current in the subthreshold region, I0 is a constant proportional to W, q is an electron charge, k is a Boltzmann constant, T is an absolute temperature, and n is determined by a capacitance division of an oxide film capacitance and a depletion layer capacitance. For example, about 1.3 is common for NMOS transistors.

  In the circuit of FIG. 2, since the gate electrodes of PM1 and PM2 are common, the currents flowing through PM1, PM2, NM3, NM4, and R1 are equal. Since the currents flowing through NM3 and NM4 are equal and the W / L ratio of NM3 and NM4 is 1: 6, the potential difference VR1 between both ends of the resistor R1 is expressed by the following formula ( 7).

VR1 = (nkT / q) ln (6) (7)
Since the potential difference VR1 between both ends of the resistor R1 is expressed by Expression (7), the current Ip flowing through PM1 and PM2 is
Ip = (1 / R1) (nkT / q) ln (6) (8)
It becomes. This current Ip also flows through PM3. Therefore, when the temperature dependency of the resistance is ignored, the current flowing through PM3 becomes a current proportional to the temperature as shown in Expression (8). Since this current flows through the resistor R2 and the diode D1, the reference potential Vref is expressed by the following equation (9).

Vref = Vbe + (R2 / R1) (nkT / q) ln (6) (9)
Here, Vbe is the forward potential of D1, and R2 is the resistance value of the resistor R2.

  Since Vbe in equation (9) has a negative temperature dependency with respect to temperature, a constant such that the term (R2 / R1) (nkT / q) ln (6) cancels the negative temperature dependency of Vbe. By selecting, the reference potential Vref can be set so as not to depend on temperature. The value of the reference potential Vref at that time is substantially a silicon bandgap voltage (about 1.2 V).

  As described above, in the conventional circuit of FIG. 2 as well, by selecting the values of PM1, PM2, PM3, NM3, NM4, R2 and R1, a band gap voltage independent of temperature can be generated with a relatively simple circuit. Can do. The circuit of FIG. 1 can achieve high accuracy because it uses a bipolar transistor, but operates at a low voltage because it includes a series connection of a PMOS transistor, an NMOS transistor, and a bipolar transistor, as will be described later. There is a problem that can not be. On the other hand, the circuit of FIG. 2 can be driven with a low operating voltage.

  FIG. 3 shows an example of the configuration of a conventional bias current generating circuit for generating a bias current. A bias current proportional to the absolute temperature is generated by the circuit of FIG. 3, and the reference voltage Vref is generated based on the bias current using, for example, a circuit including PM3, R2, and D1 of FIG. 3, elements having the same functions as those in FIG. 2 are referred to by the same reference numerals.

  The conventional circuit of FIG. 3 generates a bias current (equation (8)) proportional to the absolute temperature by the same operation as the conventional circuit of FIG.

  In FIG. 3, the circuit portion BLK1 functions as a startup circuit. In the loop composed only of PM1, PM2, NM3, NM4, and R1, there is a problem that the circuit is stabilized even when all currents are 0, in addition to the stable point represented by the equation (8). In order to solve this problem, the startup circuit BLK1 is used.

  When an undesired operating point, that is, when all the currents are 0, the potential of the internal node 10 is Vdd, and the potential of the internal node 21 is GND. At this time, since NM6 is OFF, the potential of the internal node 34 becomes Vdd due to the current flowing through PM4. When the potential of the internal node 34 becomes Vdd, NM5 is turned on and current starts to flow through PM2. When current begins to flow through PM2, current also begins to flow through PM1, and the circuit reaches the stable point represented by equation (8).

  When current begins to flow through PM1, PM2, NM3, NM4, and R1, current also flows through NM6, the potential of the internal node 34 becomes about the GND potential, and NM5 is turned OFF. As a result, the startup circuit BLK1 is disconnected from the loop constituted by PM1, PM2, NM3, NM4, and R1.

  FIG. 4 is a diagram showing still another example of the configuration of a conventional bandgap circuit.

  In FIG. 4, Q1 and Q2 are pnp bipolar transistors, R1, R2 and R2 ′ are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, PM1 and PM2 are PMOS transistors, 11 is a bias potential (op-amp output) of the PMOS transistor, 30, 31 and 32 are internal nodes, and OP1 is an operational amplifier. 4, elements having the same functions as those in FIG. 1 are referred to by the same reference numerals.

  For example, W1 / L (W: gate width, L: gate length) of PM1 and PM2 is equal, and the junction area ratio between Q1 and Q2 is, for example, 1: 6. Further, it is assumed that the resistance value of the resistor R2 is equal to the resistance value of R2 ′.

  The base-emitter voltage of the bipolar transistor or the forward voltage Vbe of the pn junction is expressed by the above-described equation (1). Further, the relationship between the emitter current I of the bipolar transistor and the voltage Vbe is expressed by the above equation (2).

  In the circuit of FIG. 4, since the gate electrodes of PM1 and PM2 are common, the currents flowing through PM1, PM2, Q1, Q2, R1, R2, and R2 ′ are equal. Due to the negative feedback action of OP1, the potentials of the nodes 30 and 31 become substantially equal and the circuit is stabilized. Since the potentials of the nodes 30 and 31 are equal and the junction area ratio between Q1 and Q2 is 1: 6, the potential difference VR1 between both ends of the resistor R1 is expressed by the above-described equation (3). Further, the current Ip flowing through PM1 and PM2 is expressed by the above-described formula (4). Since this current flows through the resistor R2, the voltage drop VR2 at the resistor R2 is expressed by the above equation (5). The sum of the voltage drop VR2 at the resistor R2 and Vbe of Q3 becomes the reference voltage Vref. Since the forward voltage Vbe of the pn junction has a negative temperature dependency and the voltage drop VR2 at the resistor R2 has a positive temperature dependency, the value of the reference voltage Vref is changed to a temperature by appropriately selecting a constant. It can be designed to be independent. The value of Vref at that time is about 1.2 V corresponding to the band gap voltage of silicon.

  As described above, in the conventional circuit of FIG. 4, the size of PM1 and PM2, the junction area ratio between Q1 and Q2, and the values of R2 and R1 are appropriately selected, and an operational amplifier is used. It can be generated with a simple circuit. Conventional bandgap circuits using such an operational amplifier are shown in Non-Patent Document 2, Non-Patent Document 3, and Non-Patent Document 4, for example.

One of the important applications of the bandgap circuit described with reference to FIGS. 1, 2, and 4 is a low voltage detection circuit. By comparing the reference potential of the band gap circuit, which is constant regardless of the power supply voltage and temperature, with the potential obtained by dividing the power supply voltage, it is possible to detect whether the voltage voltage is larger or smaller than a predetermined value. For example, when it is detected that the power supply voltage is lower than the minimum operating voltage of the circuit, control such as generating a reset signal and stopping the operation of the circuit block can be executed in order to avoid malfunction.
Japanese Patent No. 3071654 Japanese Patent No. 3338814 JP 2002-99336 A JP 2003-78366 A Japanese Patent No. 2994293 Japanese Patent Laid-Open No. 5-204479 JP-A-6-309052 Gee. Zanatheas et al., “CMOS Bandgap Voltage Reference”, EI, Journal of Solid State Circuits, Volume SC-14, Number 3, June 1979, pages 655-657 (G. Tzanateas, CAT Salama, and YP Tsividis , "A CMOS Bandgap Voltage Reference," IEEE Journal of Solid-State Circuits, Vol. SC-14, No.3, pp.655-657, June 1979.) K. N. Lung et al., “Asub-1-V 15-ppm / ° C CMOS Bandgap Voltage Reference With Out Rewiring Low Threshold Voltage Devices”, EI, Journal of Solid State Circuits, Volume 37, Number 4, April 2002, pages 526-530 (KN Leung, and PKT Mok, "A Sub-1-V 15-ppm / ° C CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Devices," IEEE Journal of Solid-State Circuits , Vol. 37, No.4, pp.526-530, April 2002.) A Boni, “Op Amps and Startup Circuits for CMOS Bandgap Reference with With 1-V Supply”, IE, Journal of Solid State Circuits, Volume 37, Number 10, October 2002, pages 1339 to 1343 (A. Boni, "Op-Amps and Startup Circuits for CMOS Bandgap References With Near 1-V Supply," IEEE Journal of Solid-State Circuits, Vol. 37, No. 10, pp. 1339-1343, October 2002.) H. Bamba et al., “A CMOS Bandgap Reference Circuit with Sub-1-V Operation”, IEE, Journal of Solid State Circuits, Volume 34, Number 5, May 1999, pages 670-674 (H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, "A CMOS Bandgap Reference Circuit with Sub-1-V Operation," IEEE Journal of Solid-State Circuits, Vol. 34, No.5, pp.670-674, May 1999.)

  With the recent miniaturization of semiconductor integrated circuits, the operating voltage of the circuit decreases, and the analog circuit is also required to reduce the operating voltage. In particular, for a CMOS bandgap circuit which is an important component of a CMOS analog integrated circuit, it is desired to reduce the operating voltage.

  Further, in battery-driven electronic devices such as portable electronic devices, low power consumption of analog circuits is strongly desired from the viewpoint of battery life. In order to reduce the power consumption, it is common not only to reduce power consumption during operation, but also to devise control such as stopping the circuit except when necessary.

  Furthermore, from the viewpoint of LSI cost, it is desired to configure a circuit with a small occupied area.

  The various band gap circuits and bias current generating circuits described above have the following problems.

  The conventional circuit of FIG. 1 can generate a bandgap voltage with a relatively simple circuit, but has a problem that the minimum operating voltage of a portion that generates a PTAT current proportional to temperature is large. This includes the pnp bipolar transistor Q1 and the NMOS transistor NM1 connected in series, or Q2 and the PMOS transistor PM2 in the same current path, and the sum of the forward voltage Vbe of the pnp bipolar transistor and the threshold voltage Vth of the MOS transistor. This is because a power supply voltage of the order is required. For example, if Vbe is 0.7 V and Vth is 0.9 V, the minimum voltage is required to be about 1.6 V to 1.7 V, which is a value that has almost no margin for the power supply voltage 1.8 V of recent digital circuits. End up.

  In the circuit of FIG. 2, a band gap voltage is generated without using a series connection of a pnp bipolar transistor (diode) and an NMOS transistor. This solves the problem of the minimum operating voltage. The circuit shown in FIG. 2 has a startup circuit composed of PM7, PM8, a resistor R3, and a capacitor C2, and has the following problems.

  The first problem is that the circuit of FIG. 2 is premised on that the circuit always operates in a state where a power supply voltage is applied, and consideration is given for stopping the circuit in a state where the power supply voltage is applied. It is not. For example, when a band gap circuit is used as a reference potential of a series regulator, it may be desirable to place the circuit in a standby state with a power supply voltage applied, but the circuit in FIG. 2 answers such a requirement. I can't.

  The second problem is that the circuit shown in FIG. 2 uses the capacitor C2 for the startup circuit. Even if the circuit configuration shown in FIG. 2 is changed so as to be controllable to the standby state, the startup time is increased. Is a point. In the circuit of FIG. 2, in order to stop the operation while the power supply voltage is applied, means for setting the bias potential 10 of the PMOS transistor to Vdd, means for setting the bias potential of the NMOS transistor to GND, and the node 90 to Vdd. What is necessary is just to add the means to do. However, when the startup circuit returns to normal operation from the standby state, the potential of the node 90 must be lowered to the potential at which PM8 is turned on. In the circuit configuration of FIG. 2, since the time constants of C2 and R3 are designed to be larger than the rise time of the power supply, there is a problem that the time until the start-up circuit starts operating is large.

  Unlike the circuit of FIG. 1, the circuit of FIG. 3 generates a PTAT current proportional to the temperature by the W / L ratio of the MOS transistor. Since no pnp bipolar transistor (or diode) is used, the minimum operating voltage is reduced by Vbe compared to the circuit of FIG. However, the circuit of FIG. 3 has a problem that the minimum operating voltage is increased by the startup circuit, as will be described below.

  The startup circuit BLK1 in FIG. 3 sets the potential of the node 34 to Vdd and turns on NM5 by turning on NM5 when current does not flow through the loop constituted by PM1, PM2, NM3, NM4, and R1. Start to pass current. When a current flows through a loop constituted by PM1, PM2, NM3, NM4, and R1 and the circuit reaches a stable point, it is necessary to set the potential of the node 34 to about the GND potential and to turn off NM5. Since current flows through the loop composed of PM1, PM2, NM3, NM4, and R1 and the circuit steadily flows even after the circuit reaches a stable point, PM4 is used for low power consumption. It is necessary to set the flowing current small.

  In order to reduce the current flowing through PM4, it is only necessary to decrease W and increase L of PM4. However, when this is done, Vth of PM4 increases due to the narrow channel effect. Assuming that the threshold voltage Vth of the PMOS transistors PM1 and PM2 is 0.9 V and the threshold voltage Vth of PM4 is 1.1 V, PM4 is not turned on when the power supply voltage is 1.1 V or less, and the potential of the node 34 is Vdd. I can't. Therefore, even if the startup circuit BLK1 does not function and the voltage is such that the loop constituted by PM1, PM2, NM3, NM4, and R1 can operate, a bias current cannot be generated.

  In the circuit of FIG. 4, as shown in Non-Patent Documents 2 to 4, the operational amplifier circuit OP1 is generally configured with a differential circuit composed of PMOS transistors as an input section (or a low threshold voltage Vth). Requires special NMOS transistor). This is because the potential of the nodes 30 and 31 to be matched by negative feedback control by the operational amplifier is approximately Vbe (for example, approximately 0.6 V) and a potential close to GND. When a general NMOS transistor having a threshold voltage of about 0.6 V is used, there is almost no operational margin, and when the temperature rises, the forward voltage decreases to about 0.4 V due to temperature dependence. There is a problem.

  However, if the operational amplifier circuit OP1 is a differential circuit composed of PMOS transistors and a potential of about Vbe is input, the minimum operating power supply voltage is about Vbe + Vth (the threshold voltage of the PMOS transistor). As a result, the minimum operating power supply voltage is limited to Vbe + Vth, and there is a problem that it does not operate with a power supply voltage smaller than that.

  In addition, as a problem common to the circuits of FIGS. 1 to 4 described above, in the conventional technique, the output reference voltage is limited to a band gap voltage (about 1.2 V), and in principle, a power supply voltage higher than the band gap voltage. Is necessary.

  An object of the present invention is to provide a band gap circuit capable of generating an arbitrary voltage without being limited to the band gap voltage (about 1.2 V).

  A semiconductor integrated circuit includes a current generation circuit that generates a first current that is substantially proportional to an absolute temperature, and a reference that is substantially independent of the absolute temperature based on the first current generated by the current generation circuit. A voltage generating circuit for generating a voltage, the voltage generating circuit comprising: a first element that generates a voltage that is substantially negatively proportional to the absolute temperature; and a resistance component connected in parallel to the first element. A voltage circuit, a second element connected in parallel with the first element and the resistance voltage divider circuit, for supplying a second current proportional to the first current, and a resistance of the resistance voltage divider circuit And a third element connected to a node between the first element and a third element for supplying a third current proportional to the first current.

  In the semiconductor integrated circuit, the original band gap is obtained by using the first element that generates a voltage that is substantially negatively proportional to the absolute temperature and the resistance voltage dividing circuit that is connected in parallel to the first element. The voltage can be divided by the resistance voltage dividing circuit, and further, a current having a positive temperature dependency can be supplied to the resistance dividing circuit to cancel the divided negative temperature dependency. This makes it possible to generate a reference voltage that does not depend on absolute temperature.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 5 is a circuit diagram showing a first embodiment of a band gap circuit according to the present invention.

  In FIG. 5, Q3 is a pnp bipolar transistor, R1, R2, and R5 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, NM3 to NM8 are NMOS transistors, and PM1. PM3, PM5, and PM12 are PMOS transistors, 10 is a bias potential of the PMOS transistor, 21 is a bias potential of the NMOS transistor, 33 to 35 are internal nodes, and EN and ENX are control signals. In FIG. 5, elements having the same functions as those in FIGS. 1 to 3 and corresponding nodes are referred to by the same reference numerals.

  For example, it is assumed that W / L (W: gate width, L: gate length) of PM1, PM2, and PM3 is equal. Further, the W / L ratio of NM3 and NM4 is set to 1: 6, for example. NM3 and NM4 are designed to operate in the subthreshold region.

  The band gap circuit of FIG. 5 is in a normal operation state when the control signal EN is H and the control signal ENX is L. First, the operation in this normal state will be described. When EN becomes H and ENX becomes L, PM12, NM7, and NM8 are turned off and are not related to the operation of the circuit of FIG. At this time, PM5 is ON.

  When the gate-source voltage of the NMOS transistor is represented by Vgs, the relationship between the drain current ID and the voltage Vgs in the subthreshold region is represented by the above-described equation (6).

  In the circuit of FIG. 5, since the gate electrodes of PM1 and PM2 are common, the currents flowing through PM1, PM2, NM3, NM4, and R1 are equal. Since the currents flowing through NM3 and NM4 are equal and the W / L ratio of NM3 and NM4 is 1: 6, the potential difference VR1 between both ends of the resistor R1 is expressed by the above-described equation (7). Since the potential difference VR1 between both ends of the resistor R1 is expressed by Expression (7), the current Ip flowing through PM1 and PM2 is expressed by Expression (8) described above.

  Although this current Ip also flows through PM3, the current value is a current proportional to temperature, as is apparent from equation (8). As a result, the reference potential Vref is expressed by the above equation (9). Vbe in the first term of the formula (9) has a negative temperature dependence on the temperature, and (R2 / R1) (nkT / q) ln (6) in the second term is a positive temperature with respect to the temperature. Has dependency. Therefore, if a constant is selected so that a term having a negative temperature dependency and a term having a positive temperature dependency cancel each other, the reference potential Vref can be set not to depend on the temperature. At this time, the value of the reference potential Vref is substantially a band gap voltage (about 1.2 V) of silicon.

  In the above description, for ease of explanation, the reference voltage is expressed by Expression (9). However, as described in Non-Patent Document 1, for example, the voltage drop VR2 at the resistor R2 is expressed by Expression (5). It is also known that However, since there is only a difference in the constant n, the explanation has been made here based on the formula (9). Also in the following description, when the current is expressed, the description is advanced by Expression (8), but it is the same that it can be expressed by Expression (4).

  In FIG. 5, the circuit portion BLK2 functions as a startup circuit. In the loop composed only of PM1, PM2, NM3, NM4, and R1, there is a problem that the circuit is stabilized even when all currents are 0, in addition to the stable point represented by the equation (8). In order to solve this problem, the startup circuit BLK2 is used.

  When an undesired operating point, that is, when all the currents are 0, the potential of the internal node 10 is Vdd, and the potential of the internal node 21 is GND. Since NM6 is OFF at this time, the potential of the internal node 34 becomes Vdd due to the current flowing through PM5 and the resistor R5. When the potential of the internal node 34 becomes Vdd, NM5 is turned on and current starts to flow through PM2. When current begins to flow through PM2, current also begins to flow through PM1, and the circuit reaches the stable point represented by equation (8).

  When current begins to flow through PM1, PM2, NM3, NM4, and R1, current also flows through NM6, the potential of the internal node 34 becomes about the GND potential, and NM5 is turned OFF. As a result, the startup circuit BLK1 is disconnected from the loop constituted by PM1, PM2, NM3, NM4, and R1.

  As described above, in the conventional start-up circuit BLK1 of FIG. 3, it is necessary to set the steady current flowing in PM4 to be small in order to realize low power consumption. However, when W of PM4 is made small and L is made large, the threshold voltage Vth of PM4 becomes large due to the narrow channel effect, and there is a problem that the start-up circuit BLK1 cannot function at a low power supply voltage and fails to generate a bias current. That is, the conventional circuit has a problem that the minimum operating voltage is increased by the startup circuit.

  On the other hand, in the circuit of the present invention shown in FIG. 5, the current flowing through PM5 and the resistor R5 can be set small by sufficiently increasing the resistance value of the diffusion resistor R5. With such a circuit configuration, a MOS transistor having a sufficiently large W / L can be used, an increase in Vth due to the narrow channel effect can be avoided, and operation at a low voltage can be achieved.

  The above-described conventional circuit shown in FIG. 2 is based on the premise that the circuit is always operating in a state where a power supply voltage is applied, and consideration is given to stopping the circuit in a state where the power supply voltage is applied. There was a problem that not. In the circuit configuration of FIG. 2, the time constant of C2 and R3 is designed to be larger than the rise time of the power supply, so there is a problem that the time until the start-up circuit starts to operate is large.

  On the other hand, in the start-up circuit BLK2 of the present invention, means PM12 for setting the bias potential of the PMOS transistor to Vdd, means NM7 for setting the bias potential of the NMOS transistor to GND, means NM8 for fixing the gate of the MOS transistor NM5 for supplying the start-up current, and By providing PM5, the circuit can be set to the standby state in a state where the power supply voltage is applied to the circuit. Further, when returning from the standby state to the operating state, the time constant of the gate potential 34 of the MOS transistor NM5 through which the startup current flows is determined by the parasitic capacitance and the resistance R5, so that the large capacity C2 is charged and discharged as in the conventional circuit of FIG. There is no need to do so, and high speed can be achieved.

  FIG. 6 is a diagram illustrating an example of characteristics of the power supply voltage Vdd and the reference voltage Vref of the band gap circuit of FIG. The characteristics shown in FIG. 6 are those at temperatures of −40 ° C., 25 ° C., and 100 ° C.

  Since the negative feedback by the high gain circuit is not used, when the power supply voltage Vdd increases, the circuit current increases (due to the Early effect or the channel length modulation effect), and the reference voltage Vref increases gently. However, it can be seen that the output potential Vref does not change according to a change in temperature, indicating an operation as a bandgap circuit. In the circuit of FIG. 5, since the value of the reference voltage Vref is about 1.2V, the power supply voltage is required to be about 1.2V. From the characteristics of FIG. 6, it can be seen that the circuit operates from the power supply voltage of about 1.2V. .

  Hereinafter, in the circuit of FIG. 5, an operation at the time of standby when the control signal EN is L and the control signal ENX is H will be described.

  When the control signal EN is L and the control signal ENX is H, PM12, NM7 and NM8 are turned on and PM5 is turned off. Since PM12 is turned on, the bias potential 10 of the PMOS transistor becomes Vdd. Since NM7 is turned on, the bias potential 21 of the NMOS transistor becomes GND. Since NM8 is turned ON, the potential of the node 34 is also GND.

  Since the bias potential 10 of the PMOS transistor becomes Vdd, PM1, PM2, and PM3 are turned off. Since the bias potential 21 of the NMOS transistor becomes GND, NM3, NM4, and NM6 are also turned OFF. Further, since the node 34 becomes GND, NM5 is also turned OFF. As a result, no current flows through the circuit of FIG. 5 and a standby state (standby state) is established.

  In the description of the first embodiment of the band gap circuit, the W / L of PM1, PM2, and PM3 is equal, and the W / L ratio of NM3 and NM4 is 1: 6. Obviously, even if it is changed, the design can be based on the same principle.

  FIG. 7 is a circuit diagram showing an example when the circuit of FIG. 5 is used as a bias current generating circuit. In FIG. 7, the same elements as those of FIG. 5 are referred to by the same reference numerals, and a description thereof will be omitted.

  As shown in FIG. 7, a part of the circuit of FIG. 5 can be used as a bias current generating circuit. When used as a bias current generating circuit, the current flowing through the startup circuit can be adjusted by the series equivalent resistance of PM5 and resistor R5. For example, if the resistance value of diffused resistor R5 is sufficiently large, the W / L of PM5 Can be increased. This makes it possible to use a MOS transistor having a sufficiently large W / L, avoid an increase in Vth due to the narrow channel effect, and enable an operation with a low voltage.

  FIG. 8 is a circuit diagram showing a second embodiment of the band gap circuit according to the present invention.

  In FIG. 8, Q3 is a pnp bipolar transistor (pnp bipolar transistor), R1, R5, R6, and R7 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, NM3 to NM6 Denotes an NMOS transistor, PM1 to PM3, PM5 and PM6 are PMOS transistors, 10 is a bias potential of the PMOS transistor, 21 is a bias potential of the NMOS transistor, and 33 to 35 are internal nodes. In FIG. 8, elements having the same functions as those in FIG. 5 and corresponding nodes are referred to by the same reference numerals. In FIG. 8 as well, the circuit can be stopped by using signals similar to the control signals EN and ENX in FIG. 5, but the control portion for stopping the circuit is omitted for simplification of the drawing.

  The portion for generating the bias current of the circuit of FIG. 8 is the same as the configuration of the circuit of FIG. The difference between the circuit of FIG. 8 and the circuit of FIG. 5 is PM3, PM6, R6, R7, and Q3, which generate the reference voltage. In the circuit of FIG. 8, the circuit is configured to generate a voltage other than 1.2V, for example, a voltage of 0.6V.

  For example, it is assumed that W / L (W: gate width, L: gate length) of PM1, PM2, PM3, and PM6 is equal. Further, the W / L ratio between NM3 and NM4 is set to 1: 6, for example. NM3 and NM4 are designed to operate in the subthreshold region.

  The current Ip flowing through PM1 and PM2 is expressed by the above-described equation (8) and becomes a PTAT current proportional to the temperature. A current having the same value as this current flows in PM3. For simplicity of explanation, it is assumed that the resistance values of R6 and R7 are the same. Since a current flows from PM3 to Q3, the potential of the node 33 becomes Vbe (Vbe: pn junction forward voltage). The potential of the node 33 is divided into Vbe / 2 by the resistors R6 and R7 having the same resistance value (in this case, the current flowing through R6 and R7 does not significantly reduce the Vbe of Q3). Set the resistance value to some extent).

  Further, the PTAT current represented by the equation (8) also flows through PM6. In order to simplify the explanation, it is assumed that all the current flowing from PM6 flows to R7. Assuming that the current of PM6 flows through R7, the potential of the reference voltage Vref is approximately expressed by the following formula (10).

Vref = (1/2) Vbe + (R7 / R1) (nkT / q) ln (6) (10)
Vbe has a negative temperature dependence on the temperature, and (R7 / R1) (nkT / q) ln (6) has a positive temperature dependence on the temperature. If a constant is selected so as to cancel a term having a positive temperature dependency and a term having a negative temperature dependency, the reference potential Vref can be set so as not to depend on the temperature. The value of the reference potential Vref at that time is approximately band gap voltage / 2 = about 0.6V.

  In the above example, the case where the resistance values of R6 and R7 are set equal to each other and the reference voltage is set to about 0.6 V has been described. However, these constants are required as long as the condition that the value of Vref does not depend on temperature is satisfied. You may change it freely. The value of Vref can also be designed to an arbitrary value such as 0.9V.

For example, the resistance value of R1 is set to 300 kΩ. The current Ip flowing through PM1 and PM2 is calculated from the equation (8).
Ip = (1 / R1) (nkT / q) ln (6)
= (1.3 × 26mV × ln (6)) / 300kΩ = 61mV / 300kΩ = 0.2uA
(N is 1.3). Since the current of PM3 flows not only in Q3 but also in R6 and R7, the W / L of PM3 and PM6 is doubled with respect to PM1 and PM2.

  A current of 0.4 uA flows through PM3. If a current does not flow to Q3 to some extent, Vbe cannot be generated at node 33, so the series resistance values of R6 and R7 must be somewhat large. Here, it is assumed that R6 is 1500 kΩ and R7 is 4500 kΩ. The series resistance of R6 and R7 is 6MΩ. Considering only the current of PM3, if Vbe is 0.6V, a current of 0.6V / 6MΩ = 0.1uA flows through R6 and R7. Since the current flowing through PM3 is 0.4uA, about 1/4 of that flows through resistors R6 and R7, and the rest flows through Q3. Since a current of about 3 uA flows through Q3, the potential of the node 33 is Vbe, for example, 0.6V. This voltage is divided into 3/4 by R6 and R7 and appears as a reference voltage Vref. That is, when only the current of PM3 is considered, the potential of Vref is 3/4 × Vbe (= 0.45V).

  Furthermore, a current of 0.4 uA also flows from PM6 to Vref. Since the equivalent resistance of Vref viewed from PM6 is a parallel resistance of R6 and R7, when R6 is 1500 kΩ and R7 is 4500 kΩ, the parallel equivalent resistance is 1.125 MΩ. When a current of 0.4 uA is passed through the parallel equivalent resistance of 1.125 MΩ, the voltage drop is 0.45V. Since this voltage drop is added to the value 0.45V obtained by dividing Vbe as described above, the final potential of Vref becomes 0.9V.

  In this way, the diode voltage is divided by the parallel combined resistance of R6 and R7 and the current of PM6 so that the diode voltage can be divided by the ratio of the original band gap voltage and the voltage to be finally output. The values of R6 and R7 may be determined so as to cancel the negative temperature dependence of the voltage.

  When the reference voltage generating portion is configured as in the circuit of FIG. 8, Vbe can be divided by R6 and R7, and positive temperature dependence that cancels the temperature dependence for the arbitrarily divided Vbe. Can be added. When Vbe is divided into 1/3, a potential that cancels the temperature dependence of Vbe / 3 can be generated by the PM6 current and the equivalent parallel resistance of R6 and R7, and when Vbe is divided into 5/6 A potential that cancels the temperature dependence of 5 Vbe / 6 can be generated by the PM6 current and the equivalent parallel resistance of R6 and R7. It is clear from the above description that the final Vref potential at that time is Veg / 3 and 5 Veg / 6, respectively. In the above description, n is assumed to be 1.3. However, the value of n varies depending on the transistor, and more precisely depends on the current density. Therefore, it is desirable to accurately design the necessary resistance and current by detailed circuit simulation.

  FIG. 9 is a diagram illustrating an example of characteristics of the power supply voltage Vdd and the reference voltage Vref of the circuit of FIG. FIG. 9 shows the case where the temperatures are −40 ° C., 25 ° C., and 100 ° C.

  When the power supply voltage Vdd increases, the circuit current increases (due to the Early voltage or channel length modulation effect), and the reference voltage Vref increases slowly. However, it can be seen that the output potential Vref does not change with respect to a change in temperature, indicating an operation as a reference voltage circuit independent of temperature. In the characteristic example of FIG. 8, the value of the reference voltage Vref is about 0.6V. It can be seen that a minimum operating power supply voltage of about 1.0 V can be realized.

  In the band gap circuit of the second embodiment of FIG. 8, the reference voltage Vref is set to a value smaller than the band gap potential, so that the band gap circuit of the second embodiment of FIG. Operation with low power supply voltage is possible.

  FIG. 10 is a circuit diagram showing a second embodiment of the bias current generating circuit according to the present invention. In FIG. 10, R1 and R5 are resistors, Vdd is a positive power supply, GND is a GND terminal, NM3 to NM7 are NMOS transistors, PM1, PM2, PM5, and PM12 are PMOS transistors, and 10 is a bias of the PMOS transistor. Reference numeral 21 denotes a bias potential of the NMOS transistor, reference numerals 34 and 36 denote internal nodes, and reference numerals EN and ENX denote control signals. 10, elements having the same functions as those in FIG. 7 and corresponding nodes are referred to by the same reference numerals.

  The operation of the bias current generating circuit of FIG. 10 is substantially the same as the operation of the circuit of FIG. Hereinafter, differences from the circuit of FIG. 7 will be described.

  In the circuit of FIG. 7, the current is designed with the W / L ratio of NM3 and NM4 and the resistance value of the resistor R1, but it is also possible to design the current with the W / L ratio of PM2 and PM1 and the resistance value of the resistor R1. It is. By designing PM1 to be six times larger than PM2, for example, the voltage between the gate and the source when PM2 and PM1 flow is different, and this difference voltage is added to the resistor R1. In this way, the current value can be designed in the same manner as the circuit of FIG.

  FIG. 11 is a diagram showing another circuit example of the bias current generating circuit of the present invention.

  In FIG. 11, R1, R5 are resistors, Vdd is a positive power supply, GND is a GND terminal, NM3, NM4, NM7, NM9 are NMOS transistors, PM1, PM2, PM7, PM8, PM12 are PMOS transistors. 10 denotes a bias potential of the PMOS transistor, 21 denotes a bias potential of the NMOS transistor, 35 and 37 denote internal nodes, and EN and ENX denote control signals. In FIG. 11, elements having the same functions as those in FIG. 7 and corresponding nodes are referred to by the same reference numerals.

  The circuit of FIG. 11 operates substantially the same as the bias current generation circuit of FIGS. A difference from the circuit of FIG. 7 is a startup circuit. The circuit of FIG. 11 will be described below with a focus on the operation of the startup circuit. Here, the control signal EN is H and the control signal ENX is L.

  It is the same as that of the circuit of FIG. 7 to determine the current in the loop constituted by PM1, PM2, NM3, NM4, and R1. The startup circuit is configured with PM7, PM8, R5, and NM9 so that the circuit is not stabilized at an undesirable operating point where the total current is zero. When all the currents are 0, the bias potential 10 of the PMOS transistor is Vdd, and the bias potential 21 of the NMOS transistor is GND. Since PM7 is OFF at this time, the potential of the node 37 becomes GND due to the current flowing through NM9 and resistor R5. When the potential of the node 37 becomes GND, PM8 is turned on and current starts to flow through NM3. When current begins to flow through NM3, current begins to flow through NM4, and the circuit reaches a stable point.

  When current begins to flow through PM1, PM2, NM3, NM4, and R1, current also flows through PM7. As a result, the potential of the node 37 becomes about Vdd potential, PM8 is turned OFF, and the startup circuit is disconnected from the loop constituted by PM1, PM2, NM3, NM4, and R1.

  Also in the circuit of FIG. 11, in order to reduce power consumption, it is necessary to set the current flowing through NM9 and resistor R5 small. In order to set the current flowing through the NM9 and the resistor R5 small, the resistance value of the resistor R5 may be sufficiently increased. By configuring the circuit in this way, the series resistance value of the diffusion resistance and the MOS transistor can be determined by the resistance value of the diffusion resistance, and the W / L of the MOS transistor can be designed large. By increasing the W / L of the MOS transistor, an increase in the threshold voltage Vth due to the narrow channel effect can be avoided and a low voltage operation can be performed.

  As described above, in FIG. 11, the startup circuit is configured by replacing the roles of the NMOS transistor and the PMOS transistor with respect to the startup circuit of FIGS. 5 and 7.

  FIG. 12 is a circuit diagram showing a configuration of still another embodiment of the band gap circuit according to the present invention.

  The circuit of FIG. 12 operates in substantially the same manner as the circuit of FIG. 5, but the power supply voltage dependency is improved by adopting a configuration in which a MOS transistor as a current source is connected in cascode.

  In FIG. 12, Q3 is a pnp bipolar transistor, R1, R2, R5, R8, R9 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, NM3 to NM8, NM10, NM11 is an NMOS transistor, PM1 to PM3, PM5, PM9, PM10, PM11, PM12 are PMOS transistors, 10 and 12 are the bias potential of the PMOS transistor, 21 and 22 are the bias potential of the NMOS transistor, and 33 to 35 are Internal nodes EN and ENX indicate control signals.

  For example, W1 / L (W: gate width, L: gate length) of PM1, PM2, and PM3 is equal, and W / L of PM9, PM10, and PM11, and W / L of NM10 and NM11 are also equal. The W / L ratio between NM3 and NM4 is set to 1: 6, for example. NM3 and NM4 are designed to operate in the subthreshold region.

  When the control signal EN is L and the control signal ENX is H, the circuit is stopped as in the case of the configuration of FIG. When the control signal EN is H and the control signal ENX is L, the circuit operates normally. The operation in this state will be described. Since EN is H and ENX is L, PM12, NM7, and NM8 are OFF and are not related to the operation of the circuit of FIG. PM5 is ON.

  In the circuit of FIG. 12, since the gate electrodes of PM1, PM2 are common, the gate electrodes of PM9, PM10 are common, and the gate electrodes of NM10, NM11 are common, PM1, PM2, PM9, PM10, R8, R9, NM10, The currents flowing through NM11, NM3, NM4, and R1 are equal. Since the currents flowing through NM3 and NM4 are equal and the W / L ratio of NM3 and NM4 is 1: 6, the potential difference VR1 between both ends of the resistor R1 is expressed by the above equation (7) as in the circuit of FIG. . Therefore, the current Ip flowing through PM1 and PM2 is also expressed by Expression (8) as in the circuit of FIG.

  Here, in order for the current to be in the state represented by the expression (8), the drain-source voltages of PM1, PM2, PM9, PM10, NM10, NM11, NM3, and NM4 are effective gate voltages (Vgs− Vth and Vth must be larger than the threshold voltage. The size of PM1, PM2, PM9, PM10, NM10, NM11, NM3, NM4 and the values of resistors R8, R9, R1 are designed so as to satisfy this condition. This is achieved by designing the voltage drop at the resistors R8 and R9 when the current of the equation (8) flows to be 0.2 V, for example.

  Since the gate voltages of PM9 and PM10 are, for example, 0.2 V lower than the gate voltages of PM1 and PM2, even if the sizes of PM1, PM2, PM9, and PM10 are the same, the source potentials of PM9 and PM10 are Vdd. The potential is lower by 0.2V. The size may be determined so that the drain currents of PM1 and PM2 operate in the saturation region with this drain voltage. The size ratio between PM1 and PM9 may be 1: 1, PM9 may be four times larger than PM1, or conversely, PM1 may be four times larger than PM9. These cascode circuits themselves are general circuits, and can be appropriately designed in size so as to realize desired characteristics.

  Similarly, the gate potentials of NM10 and NM11 can be designed to be, for example, 0.2 V higher than the gate potentials of NM3 and NM4 by the resistor R8, so that cascode circuits of NM10, NM3, and NM11, NM4 can be realized. By using the cascode circuit in this way, the power supply voltage dependency due to the channel length modulation effect of the MOS transistor can be relaxed.

  In the circuit of FIG. 12, since the bias current generation portion that generates the current of the equation (8) is a cascode circuit, the PMOS transistors PM3 and PM11 of the voltage generation portion are also cascode circuits. Since the generated bias current value itself is the same as that of the circuit of FIG. 5, the value of the reference voltage Vref is the same as that of the circuit of FIG.

  The circuit in FIG. 12 uses a cascode circuit to improve the power supply voltage dependency as compared with the circuit in FIG.

  FIG. 13 is a diagram illustrating an example of characteristics of the power supply voltage Vdd and the reference voltage Vref of the circuit of FIG. FIG. 13 shows the cases where the temperatures are −40 ° C., 25 ° C., and 100 ° C.

  It can be seen that the output potential Vref does not change with respect to the change in temperature, indicating an operation as a band gap circuit. It can also be seen that the power supply voltage dependency is improved by using the cascode circuit as compared with the circuit of FIG. In the circuit of FIG. 12, it can be seen that the circuit operates from a power supply voltage of about 1.2V. This is because the minimum operating voltage of the bias current generating portion increases due to the cascode circuit, but when the operating voltage of the current generating portion is lower than 1.2 V, the final circuit operating voltage is the voltage generating portion. This is because the voltage is limited to 1.2V.

  In the above description, the case where the cascode circuit is applied to the configuration of FIG. 5 has been described. For example, only the PMOS side or only the NMOS side may be used as the cascode circuit. Further, it goes without saying that the cascode circuit can be similarly applied to the configurations shown in FIGS.

  FIG. 14 is a diagram showing an example of the configuration of a low voltage detection circuit according to the present invention. FIG. 15 is a diagram for explaining the operating characteristics of the circuit of FIG.

  The circuit of FIG. 14 uses the reference voltage Vref generated by the circuit of FIG. 5 to detect that the value of the power supply voltage has become smaller than a predetermined value, and when the power supply voltage becomes lower than the predetermined value, the reset signal Functions as a circuit that outputs. When the value of the power supply voltage becomes larger than a predetermined value, the reset signal is canceled. Further, the circuit of FIG. 14 is configured to appropriately output the reset signal RST even when the voltage is low enough that the circuit of FIG. 5 that generates the reference voltage does not operate sufficiently.

  In FIG. 14, C1 is a capacitance, R10, R11, R12, and R13 are resistors, Vref is a reference potential, Vdd is a positive power supply, GND is a GND terminal, and vdiv1 is a power supply voltage divided by a resistor. NM12 to NM19 are NMOS transistors, PM13 to PM20 are PMOS transistors, 10 is the bias potential of the PMOS transistor, 21 is the bias potential of the NMOS transistor, 40 to 42 are internal nodes, and EN and ENX are control signals. RST, RSTX, RST2 are output reset signals, and sch1 is a Schmitt circuit. The reference voltage Vref is generated by the circuit of FIG. 5 and supplied to the circuit of FIG.

  FIG. 15 is a diagram illustrating the power supply voltage Vdd on the horizontal axis and the potentials (reference voltages Vref, vdiv1, RST) of the respective units in FIG. 14 on the vertical axis. The full scale on the horizontal axis corresponds to 1 second, and corresponds to the operation when the power supply voltage is raised from 0V to 4V and then lowered from 4V to 0V. The horizontal axis corresponds to a time of 1 second, but for easy understanding, the corresponding power supply voltage Vdd is used as a scale.

  Since the reference voltage Vref is generated by the circuit of FIG. 5 and supplied to the circuit of FIG. 14, the relationship between the reference voltage Vref and the power supply voltage Vdd is substantially the same as that of FIG. When the power supply voltage Vdd is increased from 0V to 4V, the reference voltage generation circuit of FIG. 5 starts to operate when the power supply voltage exceeds 1V. When the power supply voltage exceeds 1.2V, the reference voltage Vref becomes approximately 1.2V.

  Control signals EN and ENX in FIG. 14 are signals for stopping the circuit, and the circuit is stopped when EN is L and ENX is H. During normal operation, EN is set to H and ENX is set to L. First, the normal operation in this state will be described.

  PM20 and resistors R10, R11, and R12 function as a voltage dividing circuit that divides power supply voltage Vdd by a resistor to generate vdiv1. The PM 20 functions as a switch for controlling so that a steady current does not flow when the circuit is stopped. The ratio of the resistors R10 and R11 is determined by the voltage to be detected. In the example of FIG. 14, the resistor R10: R11 = 1: 2.2. Thereby (when NM18 is ON), the potential of vdiv1 = 2.2Vdd / 3.2 = 0.69Vdd. Since the power supply potential at which the divided potential is 1.2 V is 1.74 V, whether the value of the power supply voltage is larger than a certain value (1.74 V) by comparing this voltage vdiv1 with the reference voltage 1.2 V. Whether it is small or not can be detected. If the power supply voltage is smaller than a certain value, the circuit may malfunction, so that the low voltage detection circuit detects a drop in the power supply voltage and generates a reset signal.

  Signal RST is a signal for this purpose. When RST is H, it indicates that the power supply voltage is smaller than a predetermined value.

  The resistors R12 and NM18 are elements for giving a hysteresis characteristic to the circuit so that the output RST does not vibrate near the detection voltage. When the power supply voltage Vdd is smaller than a predetermined value, RST is H and NM18 is ON. When the power supply voltage rises and RST changes to L, NM18 is turned OFF and the potential of the divided output vdiv1 rises. Once RST changes to L, RST does not change to H until the divided voltage determined by the resistors R10, R11, and R12 (greater than when NM18 is ON) becomes smaller than the reference potential Vref.

  In the example of FIG. 14, it was set as resistance R10: R11: R12 = 1: 2.2: 0.47. When NM18 is ON (assuming that the ON resistance of NM18 is sufficiently small), the potential of vdiv1 is 0.69 Vdd, whereas when NM18 is OFF, the potential of vdiv1 is 2.67 Vdd / 3.67 = 0.73 Vdd. Become. In each case, the power supply voltage at which the potential of vdiv1 becomes 1.2V becomes 1.74V and 1.64V, and a hysteresis characteristic of 0.1V can be given.

  PM15, PM16, PM17, PM18, NM13, NM14, NM12, NM16, NM17, and resistor R13 function as a comparison circuit that compares the reference potential Vref with the divided power supply voltage vdiv1. NM12 functions as a tail current source for the differential circuits NM13 and NM14. The gate bias can be supplied from the bias potential 21 of the NMOS transistor of FIG.

  When EN is H and ENX is L, the gate potential of PM20 is 0V. When the power supply voltage Vdd of the circuit of FIG. 14 is increased from 0V to 4V, the waveform of the divided power supply voltage vdiv1 has characteristics as shown in FIG. In a region where the power supply voltage Vdd is small, the potential of vdiv1 is approximately 0 V, and a correctly divided voltage is not output to vdiv1. This is because, even if the gate potential of PM20 is 0V, PM20 is not sufficiently turned on when the power supply voltage Vdd is lower than the threshold voltage of PM20.

  In the following, a case where the power supply voltage Vdd is less than 1V and both the vdiv1 and the reference potential Vref are potentials near 0V will be described.

  When both vdiv1 and reference potential Vref are near 0V, NM13 and NM14 are turned off regardless of the gate potential of NM12. Therefore, no current flows through NM13 and NM14, and no current flows through the load circuits PM15 and PM16 of the differential circuit. In addition, since no current flows through PM15 and PM16, no current flows through PM17 and PM18. Since no current flows through PM17, no current flows through NM16 and NM17. Since PM18 and NM17 are both OFF, the potential of the comparison circuit output RST is determined by the resistor R13, and the potential of the output RST becomes Vdd.

  When the power supply voltage Vdd exceeds 1V and becomes about 1.2V, the reference potential Vref becomes 1.2V. The power supply voltage is not sufficiently high, the reference potential Vref does not reach the design voltage 1.2V, and the value of the divided voltage vdiv1 reaches a value determined by the voltage dividing ratio of the resistor R10: R11 = 1: 2.2. The operation of the circuit of FIG.

  When the circuit of FIG. 14 and the circuit of FIG. 5 are combined, a characteristic that the reference potential Vref becomes higher than vdiv1 can be realized as shown in FIG.

  This is because if the size of PM1, PM2, and PM3 in FIG. 5 is the same as the size of PM20 in the circuit in FIG. 14, when the power supply voltage Vdd is near the threshold voltage of the PMOS transistor, PM1, PM2, and PM3. , The current flowing in PM20 has the same value. By the way, the relationship between the potential of the reference potential Vref and the current becomes an exponential relationship due to Q3 (even if the current flowing through PM3 becomes small, the potential node 33 of the diode does not decrease rapidly, and the current decreases by one digit. Even if it decreases only 60mV). On the other hand, the relationship between the divided voltage vdiv1 and the current flowing through PM20 is substantially proportional (when the current flowing through PM20 is small, the potential of vdiv1 is proportional to the flowing current).

  Therefore, when the power supply voltage is small and the current flowing through the circuit is small, the reference potential Vref can be higher than the divided voltage vdiv1 even if the reference potential Vref does not reach the design voltage 1.2V.

  Since the reference potential Vref is higher than the divided voltage vdiv1, when a current starts to flow through NM13 and NM14, a larger current flows from NM13 to NM14, and a larger current flows from PM15 to PM16. Since a larger current flows from PM15 to PM16, a larger current flows from PM17 to PM18. The current of PM17 flows to NM16 (NM16 and NM17 have the same size), and the same current flows to NM17. Since the current of PM18 is larger than the current of NM17, the potential of the output RST becomes Vdd.

  Thus, the comparison circuit (PM15, PM16, PM17, PM18, NM13, NM14, NM12, NM16, NM17, resistor R13), the reference potential generation circuit, and the voltage divider circuit (PM20, resistors R10, R11, R12) are provided. By devising, the potential of the reset signal RST can be correctly set to Vdd even when the power supply voltage is low enough that the reference voltage generation circuit cannot generate a desired reference potential.

  After the power supply voltage becomes sufficiently large, the reference potential Vref reaches the design voltage 1.2V, and the value of the divided voltage vdiv1 reaches a value determined by the voltage dividing ratio of the resistor R10: R11 = 1: 2.2 The comparison circuit (PM15, PM16, PM17, PM18, NM13, NM14, NM12, NM16, NM17, resistor R13) operates as a normal differential circuit. Needless to say, the resistance value of the resistor R13 and the current value of the NM17 are designed so that the potential of the RST can be set to L when the NM17 is turned on.

  When the power supply voltage becomes sufficiently large, the reference potential Vref reaches the design voltage 1.2V, and the value of the divided voltage vdiv1 reaches a value determined by the voltage dividing ratio of the resistor R10: R11 = 1: 2.2 The operation will be described below.

  When the reference potential Vref is higher than the divided voltage vdiv1, a larger current flows from NM13 to NM14, and a larger current flows from PM15 to PM16. Since a larger current flows from PM15 to PM16, a larger current flows from PM17 to PM18. The current of PM17 flows to NM16 (NM16 and NM17 have the same size), and the same current flows to NM17. Since the current of PM18 is larger than the current of NM17, the potential of the output RST becomes Vdd.

  When the divided voltage vdiv1 is higher than the reference potential Vref, a larger current flows from NM14 to NM13, and a larger current flows from PM16 to PM15. Since a larger current flows from PM16 to PM15, a larger current flows from PM18 to PM17. The current of PM17 flows to NM16 (NM16 and NM17 have the same size), and the same current flows to NM17. Since the current of PM17 is larger than the current of NM18, the potential of the output RST becomes GND.

  When the change in the power supply voltage is gradual as shown in FIG. 15, as described above, the reset signal RST can be generated according to the relationship between the divided voltage vdiv1 and the reference potential Vref. On the other hand, when the power supply voltage changes abruptly, for example, even when the power supply voltage suddenly changes from 0 V to 3 V in a stepped manner, a reset signal for initializing the circuit is required (power-on reset signal).

  The circuit of FIG. 14 is configured to generate a reset signal even in such a case.

  The power-on reset signal is used to initialize the circuit when the power is turned on. Therefore, it is required to generate the reset signal in a state where the power supply voltage has reached a certain value that can initialize the circuit. For example, even when the power supply voltage Vdd changes stepwise from 0V to 3V, the circuit may be configured so that the signal remains in a state indicating reset for a while.

  PM19 and capacitors C1 and NM19 are circuits for this purpose. Even when the power supply voltage Vdd changes stepwise from 0V to 3V, the potential of RSTX changes to Vdd over a time determined by the current of the capacitors C1 and PM19. Charged. The potential of RSTX indicates a reset state when GND. The time constant for charging may be about the time from when the reference voltage circuit of FIG. When the band gap circuit starts to operate, the reference potential Vref becomes the design voltage 1.2V, and therefore the potential of RST is determined by the magnitude relationship with the divided voltage vdiv1.

  In the circuit of FIG. 14, the example in which RSTX is charged by PM 19 having a potential of 10 applied to the gate is shown, but charging may be performed by a resistor. The advantage of using PM19 is that when it is desired to increase the charging time of RSTX, it is not necessary to use a resistor with a large area, and PM19 requires a small area. However, in the circuit of FIG. 5 that generates the bias potential 10, for example, a large current flows through NM5 during the period in which the startup circuit BLK2 is operating, and this current may cause the potential of the bias 10 to be lower than the steady state. is there. Since C1 in FIG. 14 may be charged in this state, PM19 may be used as shown in FIG. If it is necessary to accurately design the charging current of C1 when the generation circuit of the bias potential 10 is not in a steady state, it is desirable to replace PM19 with a resistor.

  Since the charging time of RSTX means the release of reset, that is, the start of circuit operation, there is often no practical problem even if the time is somewhat longer. On the other hand, when the voltage decreases, it is necessary to detect the voltage decrease in a short time to avoid malfunction of the circuit. Therefore, the circuit of FIG. 14 is configured such that RSTX is quickly discharged by the NM 19 when the power supply voltage decreases and RST becomes H.

  The reset signal RSTX is further shaped by a Schmitt circuit.

  In the above description, the circuit of FIG. 14 is used in combination with the band gap circuit of FIG. 5, but may be combined with a band gap circuit of another configuration of the present invention or a conventional band gap circuit.

  FIG. 16 is a circuit diagram showing still another embodiment of the band gap circuit according to the present invention.

  The circuit of FIG. 16 operates in substantially the same manner as the circuit of FIG. The band gap circuit of FIG. 16 will be described focusing on differences from the band gap circuit of FIG.

  In FIG. 16, Q3 is a pnp bipolar transistor, R1, R2 and R5 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, NM3 to NM8, NM10, NM11, NM21, NM22 and NM23 are NMOS transistors, PM1 to PM3, PM5, PM9, PM10, PM11, PM12, PM21, PM22 and PM23 are PMOS transistors, 10 and 12 are bias potentials of the PMOS transistors, and 21 and 22 are NMOS transistors. Bias potentials, 33 to 35 are internal nodes, and EN and ENX are control signals. In FIG. 16, elements having the same functions as those in FIG. 8 and corresponding nodes are referred to by the same reference numerals.

  The circuit of FIG. 16 is different from the circuit of FIG. 12 in the method of generating the bias potentials 22 and 12 of the cascode circuit. A method for generating the bias potentials 22 and 12 of the cascode circuit in the configuration of FIG. 16 will be described below.

  In the circuit of FIG. 12, the resistor R9 generates a low potential 12 determined by the resistance value R9 and the current amount from the bias potential 10 of the PMOS transistor. On the other hand, in the circuit of FIG. 16, current is passed through PM21 at NM21 and NM22 to generate gate and source potentials determined thereby, and this is used as bias potential 12.

  In the circuit of FIG. 12, the resistor R8 generates a high potential 22 determined by the resistance value R8 and the current amount from the bias potential 21. On the other hand, in the circuit of FIG. 16, current is supplied to NM 23 at PM 22 and PM 23 to generate gate and source potentials determined thereby, which are used as bias potential 22.

  At this time, if the W / L of PM21 is designed to be smaller than that of PM1, PM2, PM3, PM9, PM10, PM11, PM22, and PM23, the value of bias potential 12 is required to be greater than the value of bias potential 10. Can only be set low. If the W / L of NM23 is designed to be smaller than that of NM3, NM4, NM10, NM11, NM21, and NM22, the value of bias potential 22 can be set as high as necessary.

  In the circuit of FIG. 16, the bias potential 12 is generated by the PM 21 independently of the bias potential 10. Correspondingly, NM20 is added as an NMOS transistor for flowing a startup current to PM21.

  FIG. 17 is a circuit diagram showing still another embodiment of the band gap circuit according to the present invention.

  The circuit of FIG. 17 operates in substantially the same manner as the circuit of FIG. The description will be focused on the difference between the band gap circuit of FIG. 16 and the band gap circuit of FIG.

  In FIG. 17, Q3 is a pnp bipolar transistor, R1, R2, R5, R14, and R15 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, NM3 to NM8, NM10, NM11, NM21, NM22 and NM23 are NMOS transistors, PM1 to PM3, PM5, PM9, PM10, PM11, PM12, PM21, PM22 and PM23 are PMOS transistors, 10 and 12 are bias potentials of the PMOS transistors, and 21 and 22 Denotes a bias potential of the NMOS transistor, 33 to 35 denote internal nodes, and EN and ENX denote control signals. In FIG. 17, elements having the same functions as those in FIG. 16 and corresponding nodes are referred to by the same reference numerals.

  The circuit of FIG. 17 differs from the circuit of FIG. 16 in the method of generating the bias potentials 22 and 12 of the cascode circuit. A method for generating the bias potentials 22 and 12 of the cascode circuit in the configuration of FIG. 17 will be described below.

  In the circuit of FIG. 16, the bias potential 12 is generated by the PM 21 designed to have a small W / L. In the circuit of FIG. 17, even if the W / L of PM21 is approximately the same as the W / L of PM1, PM2, PM3, PM9, PM10, PM11, PM22, and PM23, the potential of the bias potential 12 is provided by providing the resistor R14. Can be designed to be lower than the value of the bias potential 10 by a desired value.

  In the circuit of FIG. 15, the bias potential 12 is generated by the NM 23 designed to have a small W / L. In the circuit of FIG. 17, even if the W / L of NM23 is substantially the same as the W / L of NM3, NM4, NM10, NM11, NM21, and NM22, by providing the resistor R15, the potential of the bias potential 22 is changed to the bias potential 21. It can be designed to be higher by a desired value than the value of.

  When the cascode bias 22 is generated by connecting the resistor R15 and the NM23 in series and causing a current to flow therethrough, there is an advantage that the temperature dependence of the potential of the 22 can be arbitrarily designed. This is because the temperature dependence of the gate-source voltage is negative, whereas the potential difference when the PTAT current is passed through the resistor has a positive temperature dependence.

  The potential of the node 35 in the circuit of FIG. 17 increases in proportion to the (absolute) temperature (because the circuit bias current becomes a PTAT current proportional to the absolute temperature). If the drain potential of NM4 is constant regardless of the temperature, the potential difference between the drain and source of NM4 decreases as the temperature increases. Ideally, if the potential difference between the drain and source of NM4 is large to some extent, the current flowing through the circuit becomes a PTAT current, but the current of the actual MOS transistor is also affected by the potential difference between the drain and source. If the decrease in the potential difference between the drain and the source of NM4 is large when the temperature rises, the current that actually flows will be less than the ideal PTAT current. In order to prevent this and to generate an accurate PTAT current and to ensure the accuracy of the reference potential, it is necessary to prevent the potential difference between the drain and source of the NM4 from greatly decreasing due to temperature rise. Since the potential of the node 35 increases in proportion to the temperature, it is desirable that the drain potential of the NM4 also increases as the temperature rises. Therefore, the cascode bias 22 is desirably designed to be a potential obtained by adding the threshold voltage of the NMOS transistor to the ideal drain potential of NM4. That is, by generating the cascode bias 22 in consideration of the temperature dependency of the gate-source voltage and the temperature dependency of the PTAT current, it is possible to generate a more accurate PTAT current and thus a reference voltage.

  As described above, in the circuit of the present invention shown in FIG. 17, the temperature dependence of the cascode bias 22 can be designed freely, so that the temperature characteristics of the source potential of the NM11 can also be designed freely. Therefore, the temperature characteristic of the potential difference between the drain and source of the MOS transistor NM4 that generates a current proportional to the absolute temperature can be arbitrarily designed. That is, there is an advantage that the potential difference between the drain and source of NM4 can be finely adjusted by the temperature dependency of the cascode bias 22, and the temperature dependency of the bias current can be finely adjusted to a desired characteristic.

  FIG. 18 is a circuit diagram showing another embodiment of the band gap circuit according to the present invention.

  The circuit of FIG. 18 operates in substantially the same manner as the circuits of FIGS. The description will be focused on the difference between the band gap circuit of FIG. 18 and the band gap circuit of FIG.

  In FIG. 18, Q3 is a pnp bipolar transistor, R1, R2, R5, and R8 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, NM3 to NM8, NM10, NM11, NM21 and NM22 are NMOS transistors, PM1 to PM3, PM5, PM9, PM10, PM11, PM12 and PM21 are PMOS transistors, 10 and 12 are bias potentials of the PMOS transistors, 21 and 22 are bias potentials of the NMOS transistors, Reference numerals 33 to 35 denote internal nodes, and EN and ENX denote control signals. 18, elements having the same functions as those in FIGS. 12, 16, and 17 and corresponding nodes are referred to by the same reference numerals.

  The circuit of FIG. 18 differs from the circuit of FIG. 16 in the method of generating the bias potentials 22 and 12 of the cascode circuit. Hereinafter, a method of generating the bias potentials 22 and 12 of the cascode circuit in the configuration of FIG. 18 will be described.

  In the circuit of FIG. 16, the bias potential 12 is generated by the PM 21 designed to have a small W / L. This is the same in the circuit of FIG. 18, but the method for generating the bias potential of the NMOS transistor is different. In the circuit of FIG. 18, the bias potential 22 is generated by the resistor R8 as in the circuit of FIG. As in this example, the bias generation method of the circuit of FIG. 12 and the bias generation method of the circuit of FIG. 16 or the circuit of FIG. 17 can be combined.

  The advantage of the circuit for generating the cascode bias 22 of the NMOS transistor is substantially the same as the advantage of the circuit for generating the cascode bias 22 of the NMOS transistor of the circuit of FIG.

  Since the potential of the cascode bias 22 in the circuit of FIG. 18 is a level shift of the potential of the bias potential 21 of the NMOS transistor by the resistor R8 and the PTAT current, the temperature dependency thereof is the temperature dependency of the gate-source voltage. And a voltage drop at the resistor R8 having a positive temperature dependence.

  As in the case of the circuit of FIG. 17, when the temperature rises, if the decrease in the potential difference between the drain and source of NM4 is large, the current that actually flows will be less than the ideal PTAT current. In order to prevent this and to generate an accurate PTAT current and to ensure the accuracy of the reference potential, it is necessary to prevent the potential difference between the drain and source of the NM4 from greatly decreasing due to temperature rise. Since the potential of the node 35 increases in proportion to the temperature, it is desirable that the drain potential of the NM4 also increases as the temperature rises. From this, it is possible to obtain a characteristic in which the potential difference between the drain and the source of the NM4 does not decrease due to the temperature rise, provided that the potential of the cascode bias 22 rises at least as the temperature rises. This makes it possible to generate a more accurate PTAT current and thus a reference voltage.

  On the other hand, the bias potential of the PMOS transistor is not for determining the bias current (PTAT current) of the entire circuit, but only needs to operate as a current mirror. Therefore, an optimum generation circuit for the cascode bias 12 of the PMOS transistor may be selected from the viewpoint of occupied area, power consumption, and minimum operating voltage. When the level shift by the resistor R9 is used for generating the cascode bias 12 of the PMOS transistor as in the circuit of FIG. 12, it is advantageous in terms of power consumption but disadvantageous in terms of the minimum operating voltage and area.

  In the circuit of FIG. 18, in order to reduce the minimum operating voltage by reducing the area as much as possible, the generation circuit of the cascode bias 12 of the PMOS transistor having a small influence on the PTAT current accuracy and the reference voltage accuracy uses a level shift by the resistor R9. Instead, the circuit is the same as in FIG. Further, the cascode bias 12 of the PMOS transistor is separately generated in the PMOS transistor PM21 having a small W / L. As a result, the potential difference between the drain and source of the NM4 cascode transistor NM11 that generates a current proportional to the absolute temperature is prevented from decreasing as the temperature rises. This also contributes to prevention of deterioration of PTAT current accuracy.

  As described above, in the circuit of the present invention of FIG. 18, the level shift by the resistor R8 is used only for the generation of the cascode bias 22, and the generation of the cascode bias 12 of the PMOS transistor is generated separately in the PMOS transistor PM21 having a small W / L. This ensures the accuracy of the PTAT current.

  FIG. 19 is a circuit diagram showing another embodiment of the low voltage detection circuit according to the present invention.

  The circuit of FIG. 19 uses the reference voltage Vref of the circuits of FIG. 12, FIG. 16, FIG. 17, and FIG. When it becomes low, it works as a circuit that outputs a reset signal. 19, elements having the same functions as those in FIG. 14 and corresponding nodes are referred to by the same reference numerals.

  In FIG. 19, C1 is a capacitor, R10, R11, R12, R13, and R16 are resistors, Vref is a reference potential, Vdd is a positive power supply, GND is a GND terminal, and vdiv1 is a power supply divided by a resistor. NM12 to NM19, NM24, and NM25 are NMOS transistors, PM13 to PM20 are PMOS transistors, 10 is a PMOS transistor bias potential, 21 and 22 are NMOS transistor bias potentials, and 40 to 42 are internal nodes. EN, ENX are control signals, RST, RSTX, RST2 are output reset signals, and sch1 is a Schmitt circuit. When the power supply voltage is smaller than a predetermined value, the potential of RST is Vdd.

  The circuit shown in FIG. 19 is almost the same as the circuit shown in FIG. 14, but the voltage is divided in accordance with the generation of the band gap voltage using the cascode circuit as shown in FIGS. 12, 16, 17, and 18. There is a structural difference in the portion that generates the voltage vdiv1.

  In the circuit of FIG. 14, PM20 and resistors R10, R11, and R12 are used to generate the divided voltage vdiv1. The control signal ENX was directly applied to the gate electrode of PM20.

  In the circuit of FIG. 19, the gate signal of PM20 is generated by the resistor R16 and NM24 and NM25. Thus, by generating the gate signal of PM20 using the resistors R16, NM24, and NM25, even if the power supply voltage is small and the reference potential Vref does not reach the design voltage 1.2V, the reference potential Vref Can be reliably set to a potential higher than the divided voltage vdiv1.

  For example, it is assumed that Vref is supplied by the band gap circuit of FIG.

  In the circuit of FIG. 14, when the power supply voltage Vdd is lower than the threshold voltage of PM20, even if the gate potential of PM20 is 0V, the potential of the divided voltage vdiv1 is substantially 0V because PM20 is not sufficiently turned on. When the power supply voltage Vdd exceeds the threshold voltage Vth of PM20, the ON resistance of PM20 starts to decrease, and the potential of the divided voltage vdiv1 starts to increase. However, the power supply voltage at which Vref of the bandgap circuit of FIG. 15 begins to rise is larger than the threshold voltage of the MOS transistor. This is because the bias potentials 22 and 12 of the cascode circuit are larger than the threshold voltage of the MOS transistor.

  When the circuit of FIG. 14 and the circuit of FIG. 16 are combined, the power supply voltage is not large, the reference potential Vref does not reach the design voltage 1.2V, and the value of the divided voltage vdiv1 is the voltage dividing ratio of the resistors R10 and R11. There is a possibility that the divided voltage vdiv1 becomes higher than the reference potential Vref in a state where the fixed value has not been reached. In applications where this is not a problem, the circuit of FIG. 14 and the circuit of FIG. 16 may be used in combination, but the power supply voltage is not large, the reference potential Vref does not reach the design voltage of 1.2 V, and the divided voltage vdiv1 When the reference potential Vref is set to a potential higher than the divided voltage vdiv1 in a state where the value does not reach the value determined by the voltage dividing ratio of the resistors R10 and R11, the circuit of FIG. 19 and the circuit of FIG. 16 can be combined. That's fine.

  By applying the bias potentials 22 and 21 of the bandgap circuit to NM24 and NM25, the same current (or a constant multiple difference) as the current flowing through the cascode circuit of the bandgap circuit flows through NM24 and NM25. If the current flowing through the bandgap circuit is sufficiently close to the final value and the voltage drop of R16 is designed to be large, the PM20 can be configured not to be turned on until the current flows through the bandgap circuit.

  As a result, the bias potentials 22 and 21 of the band gap circuit of FIG. 16 are increased, and the PM 20 of FIG. 19 can be turned on after the band gap circuit starts operating. Therefore, even when the power supply voltage is not large and the reference potential Vref does not reach the design voltage 1.2V, the reference potential Vref can be reliably set to a potential higher than the divided voltage vdiv1.

  FIG. 20 is a circuit diagram showing another embodiment of the band gap circuit according to the present invention.

  The circuit of FIG. 20 operates in substantially the same manner as the circuits of FIGS. The MOS transistor serving as the current source of the circuit of FIG. 7 is cascode-connected as in the circuit of FIG.

  The operation of the circuit of FIG. 20 can be easily understood from the operation of the circuits of FIG. 12 and FIG. The circuit of FIG. 20 is configured to generate a voltage other than 1.2 V, for example, a voltage of 0.6 V, similarly to the circuit of FIG. Similarly to the circuit of FIG. 12, the dependence of the reference voltage on the power supply voltage is mitigated by using cascode connection.

  21, FIG. 22, and FIG. 23 are circuit diagrams showing other embodiments of the low voltage detection circuit according to the present invention.

  The reference voltage circuit of FIG. 21 is the same circuit as the circuit of FIG. 5, the reference voltage circuit of FIG. 22 is a circuit partially using the conventional reference voltage circuit of FIG. 1, and FIG. The low voltage detection circuit which detects a power supply voltage using a reference voltage is shown.

  22 differs from the circuit of FIG. 1 in PM30 and NM29. After the power supply voltage at which the circuit of FIG. 22 can operate is reached, a current flows through PM30, and a bias potential corresponding to the current is generated at node 21 ′ by NM29.

  The reference voltage circuit (band gap circuit) of FIG. 21 is suitable for low voltage operation as described in the description of the circuit of FIG. On the other hand, the reference voltage circuit (bandgap circuit) of FIG. 22 generates a PTAT current at the emitter junction area ratio of the pnp bipolar transistor, and therefore has the advantage that it is less susceptible to fluctuations in MOS transistor characteristics. That is, the circuit of FIG. 22 has an advantage that it is easy to ensure the reference voltage accuracy while the minimum operating power supply voltage is larger than the circuit of FIG.

  Therefore, the low voltage detection circuit of FIG. 23 uses the reference voltage Vref2 of the circuit of FIG. 22 which is highly accurate for a normal power supply voltage, and uses the reference voltage Vref1 of the circuit of FIG. 21 for a power supply voltage at which the circuit of FIG. Use. Thus, by using the two reference voltage circuits in combination, a low voltage detection circuit having both the features of high accuracy of the reference voltage output of the circuit of FIG. 22 and the features of low minimum operating voltage of the circuit of FIG. Is realized.

  23 uses the reference voltages Vref1 and Vref2 of the circuits of FIGS. 21 and 22 to detect that the value of the power supply voltage is smaller than a predetermined value, and the power supply voltage becomes lower than the predetermined value. Functions as a circuit that outputs a reset signal. When the value of the power supply voltage becomes larger than a predetermined value, the reset signal is canceled. Further, the circuit of FIG. 23 is configured to appropriately output the reset signal RST even when the voltage is low enough that the circuits of FIGS. 21 and 22 that generate the reference voltage do not operate sufficiently.

  In FIG. 23, C1 is a capacitance, R11, R12, R13, R19, R20, and R21 are resistors, Vref1 and Vref2 are reference potentials, Vdd is a positive power supply, GND is a GND terminal, and vdiv1 and vdiv2 are resistors. NM12 to NM19, NM30 to NM36 are NMOS transistors, PM13 to PM18, PM20, PM31 to PM37 are PMOS transistors, 21 and 21 ′ are NMOS transistor bias potentials, 40 to 42. , 40 ', 41' and 42 'denote internal nodes, EN and ENX denote control signals, RST, RST', RSTX and RST2 denote output reset signals, and sch1 denotes a Schmitt circuit.

  Since the configuration and operation of the circuit in FIG. 23 are similar to the configuration and operation of the circuit in FIG. 14, differences from the circuit in FIG. 14 will be mainly described.

  The upper half of FIG. 23, C1, R11, R12, R13, R20, R21, Vref2, vdiv1, NM12 to NM19, PM13 to PM18, and PM20 have almost the same configuration as the circuit of FIG. The only difference is that PM31 and R19 are connected in series to charge C1, the voltage divider circuit composed of R11, R12, R13, R20, and R21 newly generates vdiv2, and the tail current of the comparison circuit The bias of the source NM12 is 21 ′ generated in the circuit of FIG. 22, and the object to be compared with the divided voltage vdiv1 is Vref2 generated in the circuit of FIG.

  In FIG. 22, EN and ENX are control signals for stopping the circuit. When EN is L and ENX is H, the circuit is stopped. Since EN is H and ENX is L during normal operation, this state will be described first.

  The minimum operating voltage of the circuit of FIG. 21 is 1.3V, the minimum operating voltage of the circuit of FIG. 22 is 1.7V, the reference voltages Vref1 and Vref2 are 1.2V, and the voltage at which the reset of the circuit of FIG. The ratio of the voltage dividing resistors R20, R21, and R11 of the circuit of FIG. 23 is 4V, and R20: R21: R11 = 4: 1: 5 will be described.

  The resistors R20, R21, and R11 function as a voltage dividing circuit that divides the power supply voltage Vdd by a resistor and generates vdiv1. In the example of FIG. 23 (when NM18 is ON), the potential of vdiv1 = (R11) Vdd / (R20 + R21 + R11) = Vdd / 2 = 0.5Vdd. The power supply potential at which the divided potential vdiv1 becomes 1.2V is 2.4V. Therefore, by comparing the voltage vdiv1 with the reference voltage 1.2V (Vref2), the value of the power supply voltage is a certain value (2.4V). ) It is possible to detect whether it is larger or smaller.

  The signal RST is a signal for this purpose. When RST is H, it indicates that the power supply voltage is smaller than a predetermined value. Resistors R12 and NM18 are elements for giving a hysteresis characteristic to the circuit so that the output RST does not vibrate in the vicinity of the detection voltage, similarly to the circuit of FIG.

  If the minimum operating voltage of the circuit of FIG. 23 is 1.7V, the bias potential 21 ′ and the reference voltage Vref2 may become indefinite when the power supply voltage is 1.7V or lower. In such a case, a circuit portion constituted by the lower half of FIG. 23, Vref1, vdiv2, NM30 to NM36, and PM32 to PM37 is added so that RSTX can be reliably fixed to L. The circuit portion composed of the lower half of FIG. 23, Vref1, vdiv2, NM30 to NM36, and PM32 to PM37 operates as a comparison circuit, and the operation is substantially the same as the comparison circuit of the circuit of FIG. Description of the operation will be omitted, and a device for reliably fixing RSTX to L at the minimum operating voltage of 1.7 V or less of the circuit of FIG. 22 will be described.

  The second comparison circuit composed of NM30 to NM36 and PM32 to PM37 compares the reference voltage output Vref1 of the circuit of FIG. 21 with the divided voltage vdiv2, and when the divided voltage vdiv2 is smaller than Vref1, When it is turned on and the divided voltage vdiv2 is larger than Vref1, NM36 is turned off. RSTX can be fixed to L by turning on NM36.

  When NM18 is ON, the potential of vdiv2 = (R21 + R11) Vdd / (R20 + R21 + R11) = (1 + 5) Vdd / (4 + 1 + 5) = (6) Vdd / (10) = 3Vdd / 5 = 0.6Vdd. Since the power supply potential at which the divided potential vdiv2 becomes 1.2V is 2V, by comparing the divided voltage vdiv2 with the reference voltage 1.2V (Vref1), the NM36 is also turned on when the power supply voltage is 2V or less. As a result, the reset output RSTX is fixed to L. Thereby, even if the circuit of FIG. 22 is not operating, RSTX can be set to L reliably.

  FIG. 24 is a circuit diagram showing a configuration of a bandgap circuit using an operational amplifier according to the present invention.

  In FIG. 24, Q1 and Q2 are pnp bipolar transistors, R1, R30, R30 ′, R31, and R31 ′ are resistors, Vref and Vref ′ are output reference potentials, Vdd is a positive power supply, and GND is a GND terminal. PM1, PM2 are PMOS transistors, 10 is a bias potential (op-amp output) of the PMOS transistor, 30, 31, 32, 50 and 51 are internal nodes, and OP1 is an operational amplifier. 24, elements having the same functions as those of the circuit of FIG. 4 and corresponding nodes are referred to by the same reference numerals.

  The operation of the circuit of the present invention shown in FIG. 24 will be described.

  For example, W1 / L (W: gate width, L: gate length) of PM1 and PM2 is equal, and the junction area ratio between Q1 and Q2 is, for example, 1: 6. Further, it is assumed that the resistance values of the resistors R30 and R30 ′ are equal, and the resistance values of the resistors R31 and R31 ′ are equal.

  As described in the description of the prior art, when the base-emitter voltage of the bipolar transistor or the forward voltage of the pn junction is represented by Vbe, the relationship between the forward voltage of the pn junction and the absolute temperature T can be expressed by the above equation (1 ) Is known.

  Further, it is known that the relationship between the emitter current I of the bipolar transistor and the voltage Vbe is expressed by the above-described equation (2).

  In the circuit of FIG. 24, since the gate electrodes of PM1 and PM2 are common, the currents flowing through PM1, PM2, Q1, Q2, R1, R30, R30 ′, R31, and R31 ′ are equal. Due to the negative feedback action of OP1, the potentials of the nodes 50 and 51 become substantially equal and the circuit is stabilized.

  Since the resistance values of R30 and R30 ′ are equal and the resistance values of R31 and R31 ′ are equal, when the same current flows, the voltage drops at R30 and R30 ′ and R31 and R31 ′ are equal.

  Further, as shown in the equation (2), since the relationship between the emitter current of the bipolar transistor and the forward voltage Vbe is expressed by an index, even if the current changes by one digit, the voltage changes only by 60 mV. Therefore, when the same current is supplied to Q1 and Q2, the potential of 30 hardly changes even if the current changes. On the other hand, since the potential of 31 is the sum of the voltage drop of the resistor R1 and the forward voltage of Q2, when the current increases, the potential increases substantially in proportion to the current. Therefore, when the current is large, the potential of 31 is higher than the potential of 30, and when the current is small, the potential of 31 is smaller than the potential of 30.

  Since the voltage drop at R31 and R31 ′ is the same, the relationship between the potential of 50 and the potential of 51 is the same as the potential of 30 and 31, and the potential of 51 is 50 when the current is large. When it is higher and the current is small, the potential of 51 becomes smaller than the potential of 50.

  Since the 50 and 51 potentials are input to OP1, when the current is large and the 51 potential is higher than the 50 potential, the potential of the operational amplifier output 10 becomes high and the currents PM1 and PM2 decrease. When the current is small and the potential of 51 is smaller than the potential of 50, the potential of the operational amplifier output 10 becomes low and the currents of PM1 and PM2 increase. Eventually, the potentials of the nodes 51 and 50 become substantially equal and the circuit is stabilized.

  Since the potentials 51 and 50 are equal and the currents PM1 and PM2 are equal, the potentials 30 and 31 are equal. That is, the resistors R31 ′ and R31 function as a level shift circuit for level-shifting the potentials 30 and 31 in the + direction.

  Since the junction area ratio between Q1 and Q2 is 1: 6, the potential difference VR1 between both ends of the resistor R1 is expressed by the above-described equation (3). Since the potential difference VR1 between both ends of the resistor R1 is expressed by Expression (3), the current Ip flowing through PM1 and PM2 is expressed by Expression (4) described above. Since this current flows through the resistors R30 and R31, the voltage drop VR3031 at the resistors R30 and R31 is expressed by the following equation (11).

VR3031 = (R3031 / R1) (kT / q) ln (6) (11)
(R3031: Series combined resistance value of resistors R30 and R31)
The sum of the voltage drop VR3031 and the Vbe at the resistors R30 and R31 becomes the reference voltage Vref. The forward voltage Vbe of the pn junction has a negative temperature dependency that decreases with increasing temperature (formula (1)), and the voltage drop VR3031 at the resistors R30 and R31 increases in proportion to the temperature (formula ( 11)), the value of the reference voltage Vref can be designed so as not to depend on temperature by appropriately selecting a constant. The value of Vref at that time is about 1.2 V corresponding to the band gap voltage of silicon. Since Vref and Vref ′ in FIG. 24 have the same potential, any of them may be used as the reference potential.

  24 differs from the conventional circuit of FIG. 4 in that the input of the operational amplifier OP1 is the potential of the nodes 30 and 31 in the conventional circuit of FIG. This is that the potential obtained by level shifting the potential in the + direction and 50 and 51 are input to the operational amplifier OP1.

  For example, Vbe is 0.6V and Vth is 0.8V. Since the potentials 30 and 31 are 0.6 V, the circuit does not operate even if the signals 30 and 31 are directly input to the gate electrode of the NMOS transistor. It is assumed that the voltage drop across the resistors R31 and R31 is 0.3V due to the current flowing through the resistors R31 ′ and R31. As a result, the potentials of 50 and 51 become potentials obtained by shifting the potentials of 30 and 31 by a level of 0.3V in the + direction, and the potential becomes 0.9V. If the threshold voltage Vth of the NMOS transistor is 0.8 V, it can be input to the gate electrode of the NMOS transistor.

  At this time, for example, the potential of each part is 0.6V for potentials 30 and 31, 0.9V for potentials 50 and 51, and 1.2V for Vref and Vref '. Since the potential that does not depend on temperature is the potential Vref and Vref ′ of 1.2 V, the potentials 50 and 51 vary depending on the temperature. Since the potentials 30 and 31 having a negative dependence on temperature and the potentials Vref and Vref ′ that do not depend on the temperature are intermediate potentials, the potentials 50 and 51 have a negative dependence on the temperature. . However, the dependence is smaller than the dependence of potentials 30 and 31. Taking this temperature variation into account, the potentials 50 and 51 are determined so that the operational amplifier operates within the operating temperature range.

  For example, as the circuit of the operational amplifier OP1, the circuit shown in FIG. 40 can be used most generally. In FIG. 40, Vdd is a positive power supply, GND is a GND terminal, PM40 and PM41 are PMOS transistors, NM40, NM41 and NM42 are NMOS transistors, 50 and 51 are operational amplifier inputs, and 10 is an operational amplifier output. , 55 indicate internal nodes. The parts corresponding to the circuit of FIG. 24 are given the same reference numerals. The positive phase input terminal 51 of the operational amplifier input shows + in the figure, and the negative phase input terminal 50 of the operational amplifier input shows-in the figure. When the potential of 51 is higher than the potential of 50, the potential of 10 becomes higher, and when the potential of 51 is lower than the potential of 50, the potential of 10 becomes lower.

  By inputting the potentials 50 and 51 of FIG. 24 to the NMOS transistor differential circuit as shown in FIG. 40, the operation can be performed even when the potentials of 50 and 51 are 0.9V. If the threshold voltage Vth of the NMOS transistor is 0.8 V, the potential of the node 55 can be about 0.1 V. Therefore, the NM42 can be operated as a current source and functions as a differential circuit.

  Thus, in the circuit of FIG. 24 of the present invention, by finally controlling the potentials of 30 and 31 equally, a current proportional to the absolute temperature is generated and a reference voltage independent of temperature is obtained. The operation principle is the same as that of the conventional circuit of FIG. 1, but in the conventional technique, the node 31 corresponding to the emitter 30 of the pnp bipolar transistor is directly input to the operational amplifier, whereas in the circuit of FIG. The point shifted in level by R31 is used as the input of the operational amplifier, thereby achieving low voltage operation. In the circuit of FIG. 24, details are omitted in order to explain the basic concept of the circuit. A more detailed circuit diagram is shown in FIG.

  In FIG. 25, Q1 and Q2 are pnp bipolar transistors, R1, R30, R30 ′, R31, R31 ′ and R32 are resistors, C10 and C11 are capacitors, Vref is an output reference potential, and Vdd is a positive power supply. , GND is the GND terminal, PM1, PM2, PM40 to PM46 are PMOS transistors, NM40, NM41, NM42, NM43 are NMOS transistors, 10 is an operational amplifier output, 30, 31, 32, 50, 51, 52, 53 , 54, 55, pgst are internal nodes, EN is a control signal, and NB1 is a bias potential of the NMOS transistor. The same reference numerals are given to elements having the same functions as those of the conventional circuit of FIG. 23, the circuits of FIGS. 24 and 40, and the corresponding nodes. Also, Vref ′ in FIG. 24 corresponds to 54 in FIG.

  Since the basic concept of the circuit has been described in the description of FIG. 24, portions not described in FIG. 24 will be described.

  When the control signal EN in FIG. 25 is H, the normal operation is performed. When EN is L, the circuit is stopped.

  Hereinafter, an operation when the control signal EN is H will be described.

  PM42, PM43, R32, C11, and NM43 function as a startup circuit. When no current flows in PM1 and PM2, the potential of 50 and 51 becomes GND, and the operational amplifier composed of PM40, PM41, NM40, NM41, and NM42 will not function, so if there is no startup circuit, the circuit will start up Disappear. In order to avoid this, a startup circuit is provided.

  When no current flows through PM1 and PM2, no current flows through PM42, which has a common gate electrode 10. Since EN is H, the potential of pgst becomes GND, and a current flows through PM43. When a current flows through PM43, the potential of Vref increases and the potential of 50 also increases. Since the potential of 51 is increased to GND and the potential of 50 is increased, the potential of 10 starts to decrease and current starts to flow through PM1 and PM2. When current flows through PM1 and PM2, the operational amplifier functions, and the potentials of the nodes 50 and 51 become equal to each other, and the circuit is stabilized.

  When the circuit reaches the above stable state, a current flows through PM42, the potential of pgst becomes Vdd, and the startup circuit is disconnected. R32 limits the current of PM42 after the circuit reaches a steady state and works to set the potential of pgst to Vdd. C11 is for adjusting the time constant of the node pgst. C10 functions as a general phase compensation capacitor.

  FIG. 26 is a diagram illustrating an example of a circuit that generates the bias potential NB1 of the tail current source NM42 of the operational amplifier.

  In FIG. 26, Vdd is a positive power supply, GND is a GND terminal, PM47 and PM48 are PMOS transistors, NM44 and NM45 are NMOS transistors, 10 is a bias potential (op-amp output) of the PMOS transistor, and pgst is an internal voltage. Node, ENX indicates a control signal, and NB1 indicates a bias potential of the NMOS transistor. Elements and nodes corresponding to those in FIG. 25 are given the same reference numbers.

  When the control signal ENX in FIG. 26 is L, the operation is normal, and when ENX is H, the circuit is stopped. The operation when ENX is L will be described.

  As described with reference to FIG. 25, at the start-up of the circuit, the node pgst is GND. As a result, a current flows through PM48, NB1 is generated by NM44, a potential is supplied to NB1 in FIG. 25, and a current flows through the operational amplifier. When the circuit reaches a steady state, the potential of pgst becomes Vdd, so PM48 is turned off. On the other hand, when the circuit of FIG. 25 reaches a steady state, the potential of the operational amplifier output 10 becomes a potential at which current flows in PM1 and PM2, so that current flows in PM47, NB1 is generated by NM44, and NB1 in FIG. A potential is supplied. The bias potential NB1 of the NMOS transistor can be generated with a simple circuit such as the circuit of FIG.

  As described above, in the circuits of FIGS. 24, 25, and 26, the input of the operational amplifier is set to the potentials of the nodes 30 and 31 in the conventional circuit of FIG. A low voltage operation is achieved by using a potential obtained by level shifting the potential of in the + direction, 50 and 51 as inputs of the operational amplifier, and the operational amplifier as an NMOS differential circuit.

  FIG. 27 shows another example of a circuit for generating the bias potential NB1 of the tail current source NM42 of the operational amplifier.

  In FIG. 27, R1 is a resistance, Vdd is a positive power supply, GND is a GND terminal, PM90, PM91 and PM4 are PMOS transistors, NM3 to NM6 are NMOS transistors, NB1 is a bias potential of the NMOS transistor, PB1 Denotes a bias potential of the PMOS transistor, and 34 and 35 denote internal nodes. Elements having the same functions as those of the conventional circuit of FIG. 3 and the corresponding nodes are given the same reference numerals. In order to simplify the drawing, elements for controlling the stop of the circuit are not shown.

  The circuit of FIG. 27 is the same circuit as the conventional circuit of FIG. The circuit of FIG. 3 can generate the bias potential NB1 of the NMOS transistor and the bias potential PB1 of the PMOS transistor. 27 can generate NB1 and supply a potential to NB1 of the circuit of FIG. It will be apparent that the circuit of FIG. 7 is not limited to that of FIG. 27 and that various modifications are possible.

  FIG. 28 is a diagram illustrating an example of a startup circuit having a configuration different from that in FIG.

  In FIG. 28, Q1 and Q2 are pnp bipolar transistors, R1, R30, R30 ′, R31, and R31 ′ are resistors, C10 is a capacitor, Vref is an output reference potential, Vdd is a positive power supply, and GND is GND. Terminals PM1, PM2, PM40 to PM46 are PMOS transistors, NM40, NM41, NM42, NM46 are NMOS transistors, 10 is an operational amplifier output, 30, 31, 32, 50, 51, 52, 54, 55, pgst Indicates an internal node, EN indicates a control signal, and NB1 indicates a bias potential of the NMOS transistor. The same reference numerals are given to elements having the same functions as those of the conventional circuit of FIG. 23, the circuits of FIGS. 24 and 25, and the corresponding nodes.

  Since the circuit of FIG. 28 is the same as the circuit of FIG. 25 except for the configuration of the startup circuit, the configuration of the startup circuit will be described below.

  The operation when the control signal EN is H will be described. NB1 of the circuit of FIG. 28 is supplied by the circuit of FIG.

  In FIG. 28, when no current flows through PM1 and PM2, no current flows through PM42, which has a common gate electrode 10. Since NB1 is added to NM46 and current flows through NM46, the potential of pgst becomes GND, and current flows through PM43. When a current flows through PM43, the potential of Vref increases and the potential of 50 also increases. Since the potential of 51 is increased to GND and the potential of 50 is increased, the potential of 10 starts to decrease and current starts to flow through PM1 and PM2. When current flows through PM1 and PM2, the operational amplifier functions, and the potentials of the nodes 50 and 51 become equal to each other, and the circuit is stabilized.

  When the circuit reaches the above stable state, a current flows through PM42, the potential of pgst becomes Vdd, and the startup circuit is disconnected. If the current flowing in PM42 is designed to be larger than the current flowing in NM46, the potential of pgst can be set to Vdd.

  As shown in FIG. 28, the start-up circuit can be variously modified without departing from the spirit of the present invention.

  FIG. 29 is an example showing characteristics of the power supply voltage Vdd and the reference voltage Vref of the circuit of the invention of FIG. FIG. 29 shows the cases where the temperatures are −40 ° C., 25 ° C., and 125 ° C. It can be seen that a constant reference voltage Vref can be obtained regardless of the power supply voltage Vdd and temperature.

  As described above, the potential of the node 50 varies depending on the temperature and decreases as the temperature increases. However, the dependence is smaller than the potentials of 30 and 31. As described above, in consideration of this temperature variation, the potentials of 50 and 51 are determined so that the operational amplifier operates within the operating temperature range. In the circuit of FIG. 28, since the value of the reference voltage Vref is about 1.2V, the power supply voltage requires about 1.2V, and the circuit operates from the power supply voltage of about 1.2V as shown in FIG. I understand that

  FIG. 30 is a circuit diagram showing another embodiment of the band gap circuit of the present invention using an operational amplifier.

  In FIG. 30, Q1 and Q2 are pnp bipolar transistors, R1, R30, R30 ′, R31 and R31 ′ are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, PM1 Denotes a PMOS transistor, 10 denotes a bias potential (op-amp output) of the PMOS transistor, 30, 31, 32, 50, and 51 denote internal nodes, and OP1 denotes an operational amplifier. Elements having the same functions as those in the circuit of FIG. 24 and corresponding nodes are given the same reference numerals.

  Differences between the circuit of FIG. 30 and the circuit of FIG. 24 will be described.

  In the circuit of FIG. 24, PM1 and PM2 are separately provided and currents are supplied to Vref and Vref ′. However, in the final stable state, ideally, the potentials of Vref and Vref ′ are the same potential. . Therefore, these two nodes may be one node. The circuit of the invention of FIG. 30 is a circuit example in which Vref and Vref ′ of FIG. 24 are the same node.

  FIG. 31 is a diagram showing an example of a more specific configuration of the circuit of FIG.

  In FIG. 31, Q1 and Q2 are pnp bipolar transistors, R1, R30, R30 ′, R31 and R31 ′ are resistors, C10 is a capacitor, Vref is an output reference potential, Vdd is a positive power supply, and GND is GND. PM1, PM2, PM40 to PM46 are PMOS transistors, NM40, NM41, NM42, NM46 are NMOS transistors, 10 is an operational amplifier output, 30, 31, 32, 50, 51, 52, 55, pgst is internal , EN is a control signal, and NB1 is a bias potential of the NMOS transistor. In FIG. 30, the same reference numerals are assigned to elements and corresponding nodes that function in the same manner as the circuit of FIG.

  As shown in FIGS. 30 and 31, the circuit of the invention of FIG. 24 can be modified and used.

  FIG. 32 is a circuit diagram showing another embodiment of the band gap circuit of the present invention using an operational amplifier.

  32, Q1 and Q2 are pnp bipolar transistors, R1, R2 and R2 ′ are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, PM1, PM2, PM42 and PM46. , PM49, PM50 are PMOS transistors, NM46 is an NMOS transistor, 10 is a bias potential (op-amp output) of the PMOS transistor, NB1 is a bias potential of the NMOS transistor, PB1 is a bias potential of the PMOS transistor, 31, 32, 50, pgst indicates an internal node, OP1 indicates an operational amplifier, and EN indicates a control signal. Note that elements having the same functions as the circuits of FIGS. 24 and 25 and the corresponding nodes are given the same reference numerals.

  Differences between the circuit of FIG. 32 and the circuit of FIG. 24 will be described.

  In the circuit of FIG. 24 described above, R30, R30 ′, R31, and R31 ′ are separately provided to generate a temperature-independent potential and lower potentials 50 and 51, and 50 and 51 are input to the operational amplifier. Here, since the operational amplifier is composed of an NMOS differential circuit, the input potential of the operational amplifier may be higher than that of the circuit of FIG. Therefore, in the circuit of FIG. 32, the input of the operational amplifier OP1 is set to Vref and the potential of the node 50. The resistance values of R2 and R2 ′ are adjusted so that the band gap voltage Vref can be generated (assuming that the resistance values of R2 and R2 ′ are equal).

  Also in the circuit of FIG. 32, since the currents flowing in PM1 and PM2 are equal, if feedback control is performed so that the potentials of Vref and 50 are equalized by OP1, the resistance values of R2 and R2 ′ are equal. The potentials of 31 are equal and function as a bandgap circuit as in the conventional circuit.

  FIG. 32 is a diagram showing another modification of the startup circuit.

  In FIG. 32, PM42, PM46, PM49, PM50, and NM46 constitute a startup circuit. The potentials of NB1 and PB1 are supplied from the circuit of FIG. When no current flows in PM1 and PM2, the potentials of Vref and 50 become GND, and the operational amplifier having the NMOS differential circuit as an input portion does not function. Therefore, when there is no startup circuit, the circuit does not start. In order to avoid this, a startup circuit is provided.

  When no current flows through PM1 and PM2, no current flows through PM42, which has a common gate electrode 10. Since NB1 is added to NM46 and a current flows through NM46, the potential of pgst becomes GND. Since the potential of pgst becomes GND, PM50 is turned ON and a current flows through PM49. When a current flows through PM49 and PM50, the potential of 50 increases. Since the potential of Vref is increased to GND and the potential of 50 is increased, the potential of 10 starts to decrease and current starts to flow through PM1 and PM2. When a current flows through PM1 and PM2, the operational amplifier functions, and the potentials of the nodes Vref and 50 become equal to each other and the circuit is stabilized.

  When the circuit reaches the above-described stable state, a current flows through PM42, the potential of pgst becomes Vdd, and the startup circuit is disconnected. If the current flowing in PM42 is designed to be larger than the current flowing in NM46, the potential of pgst can be set to Vdd.

  Further, the value of the startup current can be controlled by generating the bias potential PB1 of PM49 in the circuit of FIG. 27 and using this as the startup current. This makes it possible to start more stably. For example, if the startup current is too large, the potential of 50 becomes a value close to Vdd, and the potential of Vref correspondingly becomes a value close to Vdd. In this state, since PM1 and PM2 do not work as current sources, the feedback function may not work normally. If the startup current is accurately controlled by the bias potential PB1, such an abnormality at startup can be prevented.

  As described above, a modified circuit in which the input potential of the operational amplifier is higher than that of the circuit of FIG. 24 is possible as in the circuit of the invention of FIG.

  FIG. 33 is a circuit diagram showing another embodiment of the band gap circuit of the present invention using an operational amplifier.

  In FIG. 33, Q1, Q2 and Q3 are pnp bipolar transistors, R1, R31, R31 ′, R6 and R7 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, and PM1. , PM2, PM51, and PM52 are PMOS transistors, 10 is a bias potential (op-amp output) of the PMOS transistor, 30, 31, 32, 50, 51, and 60 are internal nodes, and OP1 is an operational amplifier. Note that elements having the same functions as the circuits of FIGS. 24 and 8 and the corresponding nodes are given the same reference numerals. Although elements related to control, start-up circuit, and phase compensation element are omitted, it will be apparent that the circuit can be similarly constructed from the above description.

  The circuit of FIG. 33 shows an example in which a circuit configuration for generating an arbitrary reference voltage is applied to the bandgap circuit of the present invention using an operational amplifier similarly to the circuit of the invention of FIG.

  Here, as in the circuit of FIG. 24, the operational amplifier OP1 has the inputs 50 and 51, which are obtained by shifting the potentials 30 and 31 in the positive direction by the resistors R31 ′ and R31 in the positive direction, and the NMOS differential circuit as an input portion. By combining, low voltage operation is achieved. At this time, a current proportional to the absolute temperature (PTAT current) flows through PM1 and PM2, and the circuit reaches a steady state.

  A specific circuit example of OP1 may be a general circuit as shown in FIG. In addition, the low voltage operation range can be expanded by a circuit configuration as shown in FIG.

  As described with reference to the circuit of FIG. 8, a current is passed through Q3 by PM51 to generate Vbe (Vbe: pn junction forward voltage) at 60, and this is divided by resistors R6 and R7. By adding a voltage having a positive temperature dependency to the divided potential by the PM 52, for example, a reference voltage of 0.9 V can be generated.

  FIG. 34 is a circuit diagram showing an embodiment of an operational amplifier according to the present invention.

  In FIG. 34, Vdd is a positive power supply, GND is a GND terminal, PM53 to PM57 are PMOS transistors, NM47 to NM55 are NMOS transistors, 10 is a bias potential (op-amp output) of the PMOS transistor, and NB1 is an NMOS transistor. PB1 is a bias potential of the PMOS transistor, 50, 51, 55, and 70 to 72 are internal nodes, and EN and ENX are control signals. Elements having the same functions as those of the circuits of FIGS. 33 and 40 and the corresponding nodes are given the same reference numerals.

  When EN is H and ENX is L, normal operation is performed.

  The features of the circuit of FIG. 34 will be described below. The potentials of NB1 and PB1 are supplied from the circuit of FIG.

  In the general operational amplifier circuit of FIG. 40, PM40 is diode-connected. When the threshold voltage of the PMOS transistor is small, there is no problem using the circuit of FIG. 40, but when the threshold voltage of the PMOS transistor is large, the following problem may occur.

  For example, let us consider a case where the potential of 50 and 51 is about 0.9 V and the power supply voltage Vdd is about 0.9 V. In the case of the circuit of FIG. 40, the potential of the node 55 is lower than the potentials of 50 and 51 by about the threshold voltage of the NMOS transistor. In order for a current to flow through PM 40, the gate potential of PM 40 is also lower than Vdd by about the threshold voltage of the PMOS transistor. Therefore, in a situation where the potentials 50 and 51 are close to the power supply voltage, the potential difference between the drain and source of the NM 40 in FIG. 40 is almost eliminated. In such a state, the gain of the operational amplifier circuit of FIG. 40 becomes small and a sufficient feedback action cannot be obtained.

  For example, in the circuit of FIG. 33, when the potentials of 50 and 51 are designed to be about 0.9 V and Vref is set to 0.9 V, the circuit of FIG. 33 ideally generates a stable reference voltage from about 0.9 V power supply voltage. It becomes possible to output. However, if the operational amplifier OP1 of FIG. 33 is in a state where the gain is small due to the above-mentioned problem of the operating point, the accuracy of the reference potential cannot be secured.

  In order to solve this problem, in the circuit of FIG. 34, PM53 and PM54 are used as constant current sources, and the circuit is configured so that the drain potentials of the differential circuits NM47 and NM48 are about Vdd. A constant current is supplied from PM 53 and PM 54 to nodes 70 and 71 (the currents of PM 53 and PM 54 have the same value), and a difference current from the drain current flowing in NM 47 and NM 48 flows in NM 50 and NM 51. In a general folded cascode circuit, a PMOS transistor is generally provided between nodes 70 and 71 and NM50 and NM51. However, when used in the circuit of FIG. 33, the potentials of 50 and 51 are known to be about 0.9V in advance. Therefore, even in the configuration of FIG. 34, the potentials of the nodes 70 and 71 are about the threshold voltage of the NMOS transistor, and the relationship between the drain potential and the gate potential of the NM47 and NM48 can be set in the saturation region.

  The difference current converted into a voltage by NM50 and NM51 is amplified by NM52, NM53, PM56, and PM57, and is set to 10. The signal polarity will be briefly described below. When 51 is at a high potential, the current flowing through the NM 50 decreases, so the potential at 70 decreases. Since the current flowing through the NM 51 increases, the potential of 71 increases. Since the potential of 70 is lowered, the current flowing through the NM 53 decreases. Since the potential of 71 increases, the current flowing through NM52 increases and the current flowing through PM56 and PM57 also increases. Since the current flowing through NM53 decreases and the current flowing through PM57 increases, 10 becomes H.

  FIG. 35 is an example showing characteristics of the power supply voltage Vdd and the reference voltage Vref of the circuit of FIG. 33 and the circuit of FIG. FIG. 35 shows the cases where the temperatures are −40 ° C., 25 ° C., and 125 ° C.

  As can be seen from FIG. 35, a constant reference voltage Vref can be obtained regardless of the power supply voltage Vdd and temperature. Further, the constant is designed so that the value of Vref is 0.9V. By using the circuit of the invention of FIGS. 33 and 34, when the value of the reference voltage Vref is 0.9 V, the circuit operates from about 0.9 V of the power supply voltage. The characteristic example of FIG. 35 also shows that the circuit operates from a power supply voltage of about 0.9V.

  In addition to the operational amplifier circuit of FIG. 34, an operational amplifier circuit as shown in FIG. 39 can be used in the circuit of FIG.

  In FIG. 39, Vdd is a positive power supply, GND is a GND terminal, PM53 to PM57, PM63 to PM66 are PMOS transistors, NM47 to NM56 are NMOS transistors, and 10 is a bias potential (operational amplifier output) of the PMOS transistor. NB1 is a bias potential of the NMOS transistor, PB1 is a bias potential of the PMOS transistor, 50, 51, 55, 72, 80 to 84 are internal nodes, and EN and ENX are control signals. Elements having the same functions as those in the circuits of FIGS. 40 and 34 and the corresponding nodes are given the same reference numerals.

  The circuit of FIG. 39 operates substantially the same as the circuit of FIG. 34, and therefore the difference from the circuit of FIG. 34 will be described. In the circuit of FIG. 34, the drain electrodes of NM50 and NM51 are directly connected to the drain electrodes of NM47 and NM48. This is because, in the circuit example of FIG. 33, it is known in advance that the potentials of 50 and 51 are about 0.9 V. However, the potentials of 50 and 51 are higher, and between the drain and source of NM47 and NM48. If voltage reduction becomes a problem, a circuit may be configured as shown in FIG.

  As shown in the figure, by providing PM63 and PM64 between the drains of NM50 and NM51 and the drains of NM47 and NM48, the potentials 82 and 83 can be different from the potentials 80 and 81. The potentials 82 and 83 are about the threshold voltage because the diodes NM50 and NM51 are diode-connected, but the potentials 80 and 81 are higher than the potential 84 and about the threshold voltage of the PMOS transistor.

  FIG. 39 shows an example in which a potential of 84 is generated by supplying a constant current to PM66 by PM65 and NM56. Since the potential of 84 is lower than Vdd by about the threshold voltage of the PMOS transistor, the potentials of 80 and 81 are close to Vdd. By providing PM63 and PM64, the potentials 80 and 81 can be close to Vdd. Therefore, even if the potentials 50 and 51 are high, NM47 and NM48 do not operate in the linear region, and the gain of the operational amplifier High input voltage range can be increased.

  As described above, when the potentials 50 and 51 are set to higher potentials, a bandgap circuit can be configured by using a circuit as shown in FIG. The advantages of the operational amplifier circuit of FIG. 39 have been described by taking the reference voltage circuit of FIG. 33 as an example, but it goes without saying that the circuit of FIG. 39 may be used for the circuit of the present invention using other operational amplifiers. is there.

  FIG. 36 is a circuit diagram showing another embodiment of the band gap circuit of the present invention using an operational amplifier.

  36, Q1, Q2, and Q3 are pnp bipolar transistors, R1, R31, R31 ′, and R2 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, PM1, PM2 PM58 is a PMOS transistor, 10 is a bias potential (operational amplifier output) of the PMOS transistor, 30, 31, 32, 50, 51 and 61 are internal nodes, and OP1 is an operational amplifier. The same reference numerals are assigned to elements and corresponding nodes that function in the same way as the circuits of FIGS. Although elements related to control, start-up circuit, and phase compensation element are omitted, it will be apparent that the circuit can be similarly constructed from the above description.

  In the circuit of FIG. 33, an example in which a circuit configuration for generating an arbitrary reference voltage is applied to the bandgap circuit of the present invention using an operational amplifier as in the circuit of FIG. 8, but a potential of 1.2 V is output. If this is the case, it is possible to configure a circuit as shown in FIG.

  When the circuit is configured as shown in FIG. 36, resistances R31 and R31 ′ for level shift for setting the potentials of 50 and 51 to about 0.9 V are necessary, but R30 and R30 ′ are not necessary. The band gap voltage is generated by adding the PTAT voltage to the emitter potential 61 of Q3 by R2. When R2 is smaller in size than R30 and R30 ′ in FIG. 24, there is an area advantage of configuring the circuit as shown in FIG.

  FIG. 37 is a circuit diagram showing another embodiment of the band gap circuit of the present invention using an operational amplifier.

  In FIG. 37, Q1 and Q2 are pnp bipolar transistors, R1, R31, R31 ′, R33 and R34 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, PM1, PM2 , PM59, PM60 and PM61 are PMOS transistors, 10 and 63 are bias potentials (op-amp outputs) of the PMOS transistors, 30, 31, 32, 50, 51 and 62 are internal nodes, and OP1 and OP2 are operational amplifiers. . Note that the same reference numerals are given to elements and corresponding nodes that function in the same manner as the circuits of FIGS. In order to simplify the figure, elements related to control, startup circuit, phase compensation element, etc. are omitted.

  In the description up to FIG. 36, as a method for generating the band gap voltage, an example in which the PTAT voltage is directly added to the voltage obtained by dividing Vbe or Vbe of the pnp bipolar transistor has been shown. However, in order to generate the band gap voltage, the PTAT voltage and the voltage that cancels the temperature dependence may be added, and thus the configuration shown in FIG. 37 is also possible.

  It can be easily understood from the above description that the gate potential 10 of PM1 and PM2 is controlled by OP1 so that the potentials of 50 and 51 are equal, and the PTAT current is generated in PM1, PM2, and PM59. . By the way, the potentials 50 and 51 have negative temperature dependence as shown in FIG. For example, it is possible to generate a current having a negative temperature dependency by using the 50 potential.

  If the gate potential 63 of PM61 is negatively feedback controlled by OP2 so that the potential of 50 and the potential of 62 coincide with each other, a current having a negative temperature dependency flows in PM61. When this current is appropriately scaled to cancel the positive temperature dependency of the PTAT current of PM59 and added by PM60, the temperature dependency of the total current can be eliminated. A reference voltage Vref independent of temperature can be generated by converting the total current of PM59 and PM60 into a voltage by the resistor R33.

  When the circuit is configured as shown in FIG. 37, a bias current having an arbitrary temperature dependency can be obtained simultaneously with the band gap voltage.

  FIG. 38 is a circuit diagram showing another embodiment of the band gap circuit of the present invention using an operational amplifier.

  In FIG. 38, Q1 and Q2 are pnp bipolar transistors, R1, R35, R35 ′, R36, R36 ′, and R37 are resistors, Vref is an output reference potential, Vdd is a positive power supply, GND is a GND terminal, PM1, PM2, and PM62 are PMOS transistors, 10 is a bias potential (operational amplifier output) of the PMOS transistor, 30, 31, 32, 50, and 51 are internal nodes, and OP1 is an operational amplifier. Elements having the same functions as those of the circuit of FIG. 36 and the like and corresponding nodes are given the same reference numerals. For simplification of illustration, elements relating to control, a startup circuit, a phase compensation element, and the like are omitted. R35 and R35 ′ have the same resistance value, and R36 and R36 ′ have the same resistance value.

R36 and R36 ′ function as level shift resistors for level-shifting the potential 31 corresponding to the emitter potential 30 of Q1 in the + direction (the same functions as the resistors R31 and R31 ′ up to FIG. 37).
The difference between the circuit of FIG. 36 and the circuit of FIG. 38 is in the resistors R35 and R35 ′.

  In the same way as the circuits up to FIGS. 36 and 37, the current flowing through Q1 and Q2 is proportional to the absolute temperature when the potentials of 30 and 31 are controlled to be equal. By the way, the potential Vbe of 30 has a negative temperature dependency that decreases as the temperature rises (equation (1)), and when this potential difference is divided by the resistor R35, a negative temperature that decreases as the temperature rises. A dependent current is obtained. When a current having a positive temperature dependency flowing in Q1 and Q2 and a current having a negative temperature dependency flowing in the resistors R35 and R35 ′ are appropriately added, the total current becomes a characteristic independent of temperature.

  That is, if the potentials 50 and 51 obtained by level-shifting the potential 31 corresponding to the emitter potential 30 of Q1 in the positive direction are matched, the potentials 30 and 31 become the same potential. Thus, when the potentials 30 and 31 are the same, the total current of the current flowing through Q1 and Q2 and the current flowing through the resistors R35 and R35 ′ has a characteristic that does not depend on temperature. A reference voltage independent of temperature can be obtained by converting the current independent of temperature into a voltage by R37.

  As described above, even with the circuit configuration as shown in FIG. 38, the effects of the present invention can be obtained, and a reference voltage independent of temperature can be obtained.

  FIG. 41 is a circuit diagram showing another embodiment of the band gap circuit of the present invention using an operational amplifier.

  41, Q1 and Q2 are pnp bipolar transistors, R1, R2, R2 ', R38 and R38' are resistors, Vref and Vref 'are output reference potentials, Vdd is a positive power supply, and GND is a GND terminal. PM1, PM2 are PMOS transistors, 10 is a bias potential (op-amp output) of the PMOS transistor, 30, 31, 32, 50 and 51 are internal nodes, and OP1 is an operational amplifier. Elements having the same functions as those in the circuit of FIG. 24 and the like and corresponding nodes are given the same reference numerals. In order to simplify the figure, elements related to control, startup circuit, phase compensation element, etc. are omitted. R2 and R2 ′ have the same resistance value, and R38 and R38 ′ have the same resistance value.

R38, R38 ′ and R2 and R2 ′ function as level shift resistors for level shifting the potential 31 corresponding to the emitter potential 30 of Q1 in the + direction (the same functions as the resistors R31 and R31 ′ up to FIG. 37). )
The difference between the circuit of FIG. 24 and the circuit of FIG. 41 is in the resistors R38 and R38 ′.

  In the circuit of FIG. 24, the operation has been described assuming that the threshold voltage of the NMOS transistor is about 0.8V. Even when the threshold voltage of the NMOS transistor is very large, the bandgap circuit can be configured based on the concept of the circuit of the invention of FIG. FIG. 41 shows an example in which the concept of the circuit of the present invention is applied when the threshold voltage of the NMOS transistor is 1.3V.

  Even when the threshold voltage of the NMOS transistor is 1.3 V, which is larger than the bandgap voltage, the potential of the potential 31 corresponding to the emitter potential 30 of Q1 is level-shifted in the positive direction by a resistor as in the circuit of FIG. Can be input. Since the threshold voltage of the NMOS transistor is 1.3 V, which is larger than the bandgap voltage, in addition to the resistors R2 and R2 ′ for generating the bandgap voltage, resistors R38 and R38 ′ for further level shifting the potential in the + direction. You can add more. By performing negative feedback control so that the potentials 50 and 51 that are 1.3 V or more are made to coincide with each other by R38 and R38 ′, the potentials of 30 and 31 become the same potential. As a result, the current flowing through PM1 and PM2 becomes a PTAT current, and a bandgap voltage can be generated.

  The feature of the invention of FIG. 41 is that the potential of the potential 31 corresponding to the emitter potential 30 of Q1 is further level shifted in the + direction even when the threshold voltage of the NMOS transistor is about 1.3 V, which is larger than the band gap voltage. Thus, the NMOS transistor differential input operational amplifier is operated to achieve low voltage operation as a whole.

  FIG. 42 is a circuit diagram showing another embodiment of the band gap circuit of the present invention using an operational amplifier.

  42, Q1 and Q2 are pnp bipolar transistors, R1, R30, R30 ′, R31 and R31 ′ are resistors, Vref and Vref ′ are output reference potentials, Vdd is a positive power supply, and GND is a GND terminal. , PM70 to PM77 are PMOS transistors, NM70 to NM76 are NMOS transistors, 100 is a bias potential (operational amplifier output) of the NMOS transistor, NB1 is a bias potential of the NMOS transistor, PB1 is a bias potential of the PMOS transistor, 30, Reference numerals 31, 32, 101 to 104 denote internal nodes, and OP3 denotes an operational amplifier. Elements having the same functions as those in the circuit of FIG. 24 and the like and corresponding nodes are given the same reference numerals. In order to simplify the drawing, elements relating to circuit stop control, phase compensation elements, and the like are omitted. NB1 and PB1 are supplied from the circuit of FIG.

  Up to FIG. 41, the example in which the operational amplifier controls the gate potential of the PMOS transistors (PM1, PM2) and the circuit is configured so that the current flowing through Q1, Q2 becomes the PTAT current has been described. However, the present invention is not limited to being applicable to a circuit that controls the gate potential of the PMOS transistors (PM1, PM2) with an operational amplifier. The circuit of FIG. 42 supplies a constant current to R1, R30, R30 ′, R31, R31 ′, Q1, and Q2 by PM70 and PM71, and controls the gate potential (100) of NM70 and NM71 to control 30, 31. In this example, PTAT currents are generated by matching the potentials of.

  The input of the operational amplifier OP3 is Vref and Vref ′. The fact that the potentials 30 and 31 coincide with each other due to the negative feedback action will be described. The sizes of NM70 and NM71 are designed to be equal. A constant current is supplied by PM70 and PM71 (assuming that the currents of PM70 and PM71 are equal), and an equal current flows through NM70 and NM71. Therefore, currents having the same difference are supplied to resistors R30, R30 ′, R31, and R31 ′. Flowing. It is assumed that the resistance values of R30 and R30 ′ are equal, and the resistance values of R31 and R31 ′ are also equal.

  When the potential of Vref ′ is higher than the potential of Vref, the potential of 100 increases, the current flowing through NM70 and NM71 increases, and the potential of Vref ′ decreases. Conversely, when the potential of Vref ′ is lower than the potential of Vref, the potential of 100 becomes lower, the current flowing through NM70 and NM71 becomes smaller, and the potential of Vref ′ increases. As a result, the potentials of Vref and Vref ′ are equal. Since the resistance values of R30 and R30 ′ and R31 and R31 ′ are equal, when the potentials of Vref and Vref ′ are equal, the potentials of 30, 31 are also equal. That is, the current flowing through Q1 and Q2 becomes a PTAT current proportional to the absolute temperature as described in the operation of the conventional circuit. As a result, it is possible to generate a band gap voltage that does not depend on temperature for Vref and Vref ′.

  42, PM72 to PM77 and NM72 to NM76 serve as start-up circuits. The operation of the startup circuit will be described below. The potential of the node 101 when the circuit is in a final steady state is about 0.9V.

  A bias potential PB1 is applied to PM76, and a bias potential NB1 is applied to NM76. As a result, a constant current flows through PM76, PM77, and NM76. If the drain potential of PM76 is a potential in the vicinity of Vdd, the potential of 104 is lower than Vdd by about the threshold voltage of the PMOS transistor.

  A bias potential PB1 is applied to PM72, and a bias potential NB1 is applied to NM73. At this time, the current of NM73 is made sufficiently larger than the current of PM72.

  It is assumed that the band gap circuit is not in a final steady state and no current flows through Q1 and Q2. At this time, the potentials of 101, Vref, and Vref ′ are GND. Since the potential of 101 is GND, the NM 72 is OFF, and the current supplied from the PM 72 does not flow to the NM 72. The current supplied from PM 72 flows to NM 74 through PM 73. When a current flows through NM74, the potential of 102 rises, and a current also flows through NM75 and PM74. When a current flows through PM74, a current flows through PM75, and the potential of Vref rises due to this current. Since the potential of Vref ′ is GND while the potential of Vref increases, the potential of 100 decreases and the currents of NM70 and NM71 decrease. Since the currents of NM70 and NM71 are decreased, the potential of Vref ′ is also increased by the currents of PM70 and PM71. When both the potentials of Vref and Vref ′ are increased, the operational amplifier OP3 operates, and the potentials of Vref and Vref ′ become equal to stabilize the circuit.

  When the potentials of Vref and Vref ′ are equal, the potential of the node 101 has increased to about 0.9 V, so that the current of PM72 also flows through NM72. Since the current of NM73 is set sufficiently larger than the current of PM72, all of the current of PM72 flows to NM73 through NM72. Since all the current of PM72 flows to NM73 through NM72, no current flows to PM73 and no current flows to NM74, NM75, and PM74. Since no current flows through PM74, no current flows through PM75, and the startup circuit is disconnected.

  FIG. 43 is a diagram illustrating an example of an operational amplifier circuit suitable for the circuit configuration of FIG.

  43, Vdd is a positive power supply, GND is a GND terminal, PM78 to PM81 are PMOS transistors, NM77 to NM81 are NMOS transistors, 100 is a bias potential (operational amplifier output) of the NMOS transistor, and NB1 is an NMOS transistor. , PB1 is the bias potential of the PMOS transistor, 105 to 108, Vref and Vref ′ are internal nodes. The elements having the same functions as those of the circuit of FIG. 42 and the corresponding nodes are given the same reference numerals. In order to simplify the drawing, elements relating to circuit stop control, phase compensation elements, and the like are omitted. NB1 and PB1 are supplied from the circuit of FIG. Assume that the gate potentials 104 of PM80 and PM81 are supplied from the circuit 104 of FIG.

  Since the circuit of FIG. 43 is a general folded cascode circuit, a detailed description of its operation is omitted, and only the signal polarity will be described below. When Vref ′ is a high potential, the current flowing through NM77 increases and the current flowing through NM80 decreases, so the potential of 106 decreases. Since the current flowing through NM78 decreases, the current flowing through PM81 increases. The potential at 106 decreases and the current at NM81 decreases. Since the current flowing through PM81 increases and the current of NM81 decreases, the potential of 100 increases. On the contrary, when Vref ′ is lower than Vref, it is clear that the potential of 100 becomes lower.

  The features of the circuit of the invention of FIGS. 42 and 43 will be described below.

  The circuit of FIG. 42 generates a band gap voltage by supplying a constant current from Vdd with a constant current source and controlling the gate potential of the NMOS transistor with an operational amplifier. By configuring the circuit in this way, the circuit of FIG. 24 is less affected by power supply noise.

  Assuming the most common mirror compensation, the effects of phase compensation capacitance and power supply noise will be described.

  When the gate potential of the PMOS transistor (PM1) is controlled by the operational amplifier as in the circuit of FIG. 25, the phase compensation capacitance is provided between the gate of the PMOS transistor and the output reference potential as shown by C10 in FIG. Will be.

  If a phase compensation capacitor is provided between the output reference potential at a constant potential from GND and the gate of the PMOS transistor, the gate potential 10 of the PMOS transistor tends to remain at a constant potential from GND when there is noise in the power supply Vdd. Therefore, the voltage between the gate and the source of PM1 fluctuates and causes the output reference potential to fluctuate (the gate potential 10 of the PMOS transistor is meaningful in the potential difference from Vdd).

  On the other hand, in the circuit of FIG. 42, since the gate potential 100 of the NMOS transistor NM71 is controlled by the operational amplifier, a general phase compensation capacitor for mirror compensation is provided between the node 100 and Vref. Since both the gate potential 100 and Vref of the NMOS transistor NM71 are signals having a significant potential difference from GND, even if there is noise in the power supply Vdd, it is not directly affected.

  In this way, the circuit of FIG. 42 supplies a constant current from Vdd by a constant current source, controls the gate potential of the NMOS transistor by an operational amplifier, and generates a band gap voltage, so that there is noise in the power supply Vdd. The impact can be mitigated.

  As described above, the low voltage operation, which is the effect of the present invention, can also be achieved by the circuits of the inventions of FIGS. 42, by supplying a constant current to R1, R30, R30 ′, R31, R31 ′, Q1, and Q2 by PM70 and PM71 and controlling the gate potential (100) of NM70 and NM71 as in the circuit of FIG. An example of generating a PTAT current by matching the potentials of 30 and 31 is shown, and even in a circuit in which an operational amplifier input is level-shifted in the + direction required by a resistor, various circuits can be used without departing from the spirit of the present invention. Needless to say, deformation is possible.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows an example of a structure of the conventional band gap circuit. It is a figure which shows another example of a structure of the conventional band gap circuit. It is a figure which shows an example of a structure of the conventional bias current generation circuit. It is a figure which shows another example of a structure of the conventional band gap circuit. 1 is a circuit diagram showing a first embodiment of a band gap circuit according to the present invention; FIG. FIG. 6 is a diagram illustrating an example of characteristics of a power supply voltage Vdd and a reference voltage Vref of the band gap circuit of FIG. 5. FIG. 6 is a circuit diagram showing an example when the circuit of FIG. 5 is used as a bias current generating circuit. It is a circuit diagram which shows the 2nd Example of the band gap circuit by this invention. It is a figure which shows an example of the characteristic of the power supply voltage of the circuit of FIG. 8, and a reference voltage. It is a circuit diagram which shows the 2nd Example of the bias current generation circuit by this invention. It is a figure which shows the other circuit example of the bias current generation circuit of this invention. It is a circuit diagram which shows the structure of another Example of the band gap circuit by this invention. It is a figure which shows an example of the characteristic of the power supply voltage and reference voltage of the circuit of FIG. It is a figure which shows an example of a structure of the low voltage detection circuit by this invention. It is a figure for demonstrating the operating characteristic of the circuit of FIG. It is a circuit diagram which shows another Example of the band gap circuit by this invention. It is a circuit diagram which shows another Example of the band gap circuit by this invention. It is a circuit diagram which shows another Example of the band gap circuit by this invention. It is a circuit diagram which shows another Example of the low voltage detection circuit by this invention. It is a circuit diagram which shows the other Example of the band gap circuit by this invention. It is a circuit diagram which shows a part of other Example of the low voltage detection circuit by this invention. It is a circuit diagram which shows a part of other Example of the low voltage detection circuit by this invention. It is a circuit diagram which shows a part of other Example of the low voltage detection circuit by this invention. It is a circuit diagram which shows the structure of the band gap circuit using the operational amplifier by this invention. FIG. 25 is a circuit diagram showing details of the circuit of FIG. 24. It is a figure which shows an example of the circuit which generate | occur | produces the bias electric potential of the tail current source of an operational amplifier. It is a figure which shows another example of the circuit which generate | occur | produces the bias electric potential of the tail current source of an operational amplifier. FIG. 26 is a diagram illustrating an example of a startup circuit having a configuration different from that of FIG. 25. It is a figure which shows the characteristic of the power supply voltage of the circuit of invention of FIG. 28, and a reference voltage. It is a circuit diagram which shows the other Example of the band gap circuit of this invention using an operational amplifier. FIG. 31 is a diagram illustrating an example of a specific configuration of the circuit of FIG. 30. It is a circuit diagram which shows the other Example of the band gap circuit of this invention using an operational amplifier. It is a circuit diagram which shows the other Example of the band gap circuit of this invention using an operational amplifier. It is a circuit diagram which shows the Example of the operational amplifier used by this invention. It is a figure which shows an example of the characteristic of the power supply voltage and reference voltage of the circuit of FIG. 33 and the circuit of FIG. It is a circuit diagram which shows the other Example of the band gap circuit of this invention using an operational amplifier. It is a circuit diagram which shows the other Example of the band gap circuit of this invention using an operational amplifier. It is a circuit diagram which shows the other Example of the band gap circuit of this invention using an operational amplifier. It is a circuit diagram which shows another example of the operational amplifier used by this invention. It is a circuit diagram which shows the most common structural example of the operational amplifier used by this invention. It is a circuit diagram which shows the other Example of the band gap circuit of this invention using an operational amplifier. It is a circuit diagram which shows the other Example of the band gap circuit of this invention using an operational amplifier. FIG. 43 is a diagram illustrating an example of an operational amplifier circuit suitable for the circuit configuration of FIG. 42.

Explanation of symbols

Q1, Q2, Q3 pnp bipolar transistors R1, R2, R5 Resistor Vref Output reference potential Vdd Positive power supply voltage GND Ground voltage NM1 to NM8 NMOS transistors PM1 to PM12 PMOS transistor 10 Bias potential 21 of PMOS transistor Bias potential 33 to NMOS transistor 35 Internal node EN, ENX control signal

Claims (3)

A current generating circuit for generating a first current substantially proportional to absolute temperature;
A voltage generation circuit for generating a reference voltage substantially independent of the absolute temperature based on the first current generated by the current generation circuit, the voltage generation circuit comprising:
A first element that generates a voltage that is substantially negatively proportional to the absolute temperature;
A resistive voltage divider connected in parallel to the first element;
A second element connected in parallel with the first element and the resistive voltage divider circuit for supplying a second current proportional to the first current;
A semiconductor integrated circuit comprising a third element connected to a node between resistors of the resistor voltage divider circuit and supplying a third current proportional to the first current. 2. The semiconductor integrated circuit according to claim 1, wherein the first element is a bipolar transistor or a diode. 2. The semiconductor integrated circuit according to claim 1, wherein the current generating circuit generates the first current by a size ratio of MOS transistors and a resistance.

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