JP2007243914A - Transmission apparatus including line test function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmission apparatus capable of checking a line state by establishing a line test, without terminating overhead information contained in a received signal. <P>SOLUTION: The transmission apparatus includes a test pattern signal generating means 4 for generating a test pattern signal, a test pattern signal detecting means 5 for detecting a test pattern signal generated by the test pattern signal generating means, and a line test setting means 6 for performing line test setting inside the apparatus by recognizing the reception of the test pattern signal. When a line test between transmission apparatuses is performed, a signal obtained by the test pattern signal generating means is transmitted to an opposed transmission apparatus and in the transmission apparatus which receives the test pattern signal; the test pattern signal detecting means is used to detect that the received signal is a test pattern signal, so that implementation of the line test between apparatuses is recognized and setting required for the line test within the transmission apparatus is automatically performed by the line test setting means. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a transmission apparatus having a line test function, and more particularly to a transmission apparatus capable of performing a line test without a signal termination function.

  Conventionally, a transmission apparatus having a line test function adds management information and maintenance information (hereinafter referred to as “overhead information”) when transmitting a signal, and instructs the start or end of a line test therein. Therefore, when a signal is received from the opposite device, it is necessary to terminate the overhead information and extract necessary information.

  For example, the frame transmission apparatus described in Patent Document 1 transmits a loop control request frame in which a code for requesting a loopback connection in a frame transmission section to be tested is assigned to a specific area of the MAC frame to the opposite transmission apparatus, and transmits the opposite transmission. A loop is formed by the device, and a loop control response frame is returned. After receiving the loop control response frame, the frame transmission device sends a test frame to the frame transmission interval, checks the returned test frame, and Test for quality.

The digital signal transmission apparatus described in Patent Document 2 includes a test start detection unit, a test end detection unit, a test start pattern generation unit, a test end pattern generation unit, a test signal generation unit, and a test start pattern detection. Unit, test end pattern detection unit, test signal detection, etc., and when executing a line test, if a test signal is inserted into the line from its own station device, a “branch execution command” is sent to the opposite station device. The program is executed without input from the outside, and an unnecessary alarm is not issued when branching is executed at the opposite station device.
JP 2005-203914 A JP-A-5-145603

  However, in the conventional transmission apparatus, when establishing a test operation, a control code for identifying the start or end of the test is inserted into the overhead information included in the transmitted signal, so that the overhead information is terminated after the signal is received. However, there is a problem that a process for extracting the control code is required, and the means for establishing the test operation is complicated.

  Accordingly, the present invention has been made in view of the problems in the conventional transmission apparatus and the like, and establishes a line test without terminating overhead information included in a received signal and checks the line state. It is an object of the present invention to provide a transmission device that can perform transmission.

  In order to achieve the above object, the present invention is a transmission apparatus having a line test function, which detects a test pattern signal generating means for generating a test pattern signal, and a test pattern signal generated by the test pattern signal generating means. Test pattern signal detecting means and line test setting means for recognizing reception of the test pattern signal and setting a line test in the apparatus.

  According to the present invention, when performing a line test between transmission apparatuses, the signal obtained by the test pattern signal generating means is transmitted to the opposite transmission apparatus, and the transmission apparatus receiving the test pattern signal receives the test pattern signal. By detecting that the received signal is a test pattern signal using the signal detection means, it recognizes the execution of the line test between the devices, and the line test setting means automatically sets the settings required for the line test inside the transmission device. Can be done automatically. As a result, it is possible to establish a line test without terminating the overhead information and to check the line state, thereby reducing processing inside the apparatus in the line test.

  Further, according to the present invention, the test pattern signal only needs to be uniquely determined and incorporated regardless of the signal speed and interface type, so the same test circuit configuration can be used regardless of the type of signal normally handled. The port can handle signals of different data types as needed.

  In the transmission apparatus having the line test function, the test pattern signal generation unit generates an arbitrary random pattern signal, outputs the random pattern signal as the test pattern signal, and the test pattern detection unit includes the random pattern signal. By detecting the signal, the test pattern signal can be detected.

  In the transmission apparatus having the line test function, the test pattern signal generation unit includes a fixed pattern generation unit that generates a predetermined fixed pattern signal and a random pattern generation unit that generates an arbitrary random pattern signal. The test pattern signal is generated by combining the pattern signal and the random pattern signal, and the test pattern signal detection means detects the fixed pattern signal, and the random pattern detection means detects the random pattern signal. The test pattern signal can be detected by detecting the fixed pattern signal and the random pattern signal.

  In the transmission apparatus having the line test function, the test pattern signal detecting means compares the input signal with a test pattern signal generated by an expected generation formula by taking an exclusive OR, and A test signal detection circuit that outputs a pulse signal indicating a match or mismatch in bit units, a counter that counts the number of pulses of the pulse signal output from the test signal detection circuit, and an error count value output from the counter Based on this, it is possible to provide a protection circuit that provides an arbitrary threshold value inside and issues or releases the test signal detection flag.

  In the transmission apparatus having the line test function, the line test setting means can be configured to include a selector having two output terminals.

  As described above, according to the present invention, it is possible to provide a transmission apparatus capable of establishing a line test and checking a line state without terminating overhead information included in a received signal.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an embodiment of a transmission apparatus (hereinafter abbreviated as “transmission apparatus”) having a line test function according to the present invention, and switches 1 to 3 include two input terminals and two output terminals. From either output terminal, it is possible to select and output one of the signals input from the two input terminals.

  The switch 1 individually selects and outputs the input signal 7 and one output signal of the switch 3 at each of the two output terminals according to the output logic of the switch control circuit 6. The switch 2 individually selects and outputs the input signal 9 and one output signal of the switch 1 at each of the two output terminals according to the output logic of the switch control circuit 6. The switch 3 individually selects and outputs one output signal of the switch 2 and the output of the pseudo random signal generator 4 at each of the two output terminals according to the output logic of the switch control circuit 6.

  The pseudo random signal generator (test pattern signal generating means) 4 always generates and outputs an arbitrary pseudo random pattern. The speed of the pseudo-random signal used as the test pattern signal is generated at a different speed so that it can be distinguished from the transmission signal handled during normal operation.

  When the pseudo-random signal detector (test pattern signal detecting means) 5 monitors one output signal of the switch 3 and receives a signal equivalent to the pseudo-random signal generated by the pseudo-random signal generator 4, In addition to outputting a detection flag signal, error information is output when the received signal is not an expected pattern, and the number of error bits is counted based on the error information.

  The switch control circuit (line test setting means) 6 selects either the line test control signal 11 from the outside or the detection flag signal output from the pseudo random signal detector 5 as the line test control signal. A switch control signal is output to the switches 1-3.

  Next, a detailed configuration of the switches 1 to 3 will be described with reference to FIG. These switches 1 to 3 can be realized, for example, by arranging two sets of selectors 20 and 21 having two input terminals.

  In the figure, the selector 20 selects and outputs either the input signal A or the input signal B according to the logic of the selection control signal 22. The selector 21 selects and outputs either the input signal A or the input signal B according to the logic of the selection control signal 23. As a result, the two input signals can be freely output from the two output terminals.

  Next, a detailed configuration of the switch control circuit 6 will be described with reference to FIG. The switch control circuit 6 can be realized by using, for example, a selector 30 having two input terminals.

  In the figure, the selector 30 can select a control signal with a high priority by selecting and outputting either the switch signal control A or the switch control signal B according to the logic of the selection signal. If the selector 30 is replaced with an OR gate, the switch control signal C that is output when any control signal becomes active (in this case, “1” logic) without giving priority. Can be made active.

  Next, a detailed configuration of the pseudo random signal detector 5 will be described with reference to FIG. The pseudo random signal detector 5 can be constituted by, for example, a clock extraction circuit 40, a test signal detection circuit 41, a counter 42, and a protection circuit 43.

  In the figure, a clock extraction circuit 40 extracts a clock component from an input signal and generates a clock signal used for subsequent data processing. Here, only a clock frequency component equivalent to the speed of the test pattern signal is generated. Use something that can be extracted. Thus, during normal operation, the clock extraction circuit 40 cannot generate a clock signal because the transmission signal speed is different from the test pattern signal speed, so that the test pattern signal is detected by the test signal detection circuit 41 at the subsequent stage. Therefore, erroneous detection of the test pattern signal can be prevented.

  The test signal detection circuit 41 compares, for example, an input signal and a test pattern signal generated by an expected generation formula by taking an exclusive OR, like a PN code detector. A pulse signal indicating a match or mismatch in bit units is output.

  The counter 42 accumulates the number of error bits by counting the number of pulses of the pulse signal. Based on the error count value output from the counter 42, the protection circuit 43 internally provides an arbitrary threshold value to issue or cancel the test signal detection flag.

  The configuration of the switches 1 to 3 and the like have been described in detail above. However, the configuration and operation of the pseudo random signal generator 4 in FIG.

  Next, the inter-device line test implementation and cancellation operation using the transmission device of FIG. 1 having the above configuration will be described with reference to FIGS.

  5 and 6 are configurations in an operating state when the transmission apparatuses shown in FIG. 1 are connected to face each other. In the figure, the solid line indicates the effective transmission of the signal, and the broken line indicates the signal treated as invalid. The arrows in the switches 1 to 3 indicate which signal is selected and output from the two input signals.

  First, the line test here will be briefly described. A line test is a transmission test in which an arbitrary test pattern signal is transmitted from one transmission device between connected transmission devices, and the received test pattern signal is folded inside the device in the opposite transmission device. It is returned to the device as it is. At this time, each transmission apparatus confirms the performance of the transmission path used for the connection line for each line by counting the reception state of the received test pattern signal and counting the number of error bits.

  First, in describing the line test method according to the present embodiment, the operation during normal operation of the transmission apparatus in FIG. 1 will be briefly described with reference to FIG.

  In the transmission device 50, a signal equivalent to the input signal 7 input to the transmission device 50 is output to the transmission device 51, and an equivalent signal of the signal received from the transmission device 51 is output as the output signal 10. Switches 1 to 3 are set. On the other hand, in the transmission device 51, the switches 1 to 1 output an equivalent signal of the input signal 9 to be input to the transmission device 50 and output an equivalent signal of the signal received from the transmission device 50 as the output signal 8. 3 is set. The switches 2 and 3 are set so that the signal input from the opposite transmission device is branched and output to the pseudo-random signal detector 5 in any of the transmission devices 50 and 51. In this state, the presence / absence of reception of the pseudo-random signal set to “1” is monitored. Here, the pseudo-random signal is a signal different from a signal handled between transmission apparatuses during normal operation.

  Next, the line test method according to the present embodiment will be described with reference to FIG.

  When the operator performs line test execution control via the device control terminal 52 from the normal operation state shown in FIG. 5, the start of the line test is notified to the switch control circuit 6 of the transmission device 50, and Line test settings are made for switches 1 to 3. At this time, the states of the switches 1 to 3 in the transmission device 50 are as follows.

  The switch 3 outputs the output of the pseudo random signal generator 4 to the switch 1 and outputs the other output from the transmission device 51 so that a pseudo random signal serving as a test pattern signal can be output to the transmission device 51. The setting is changed so that the received signal can be monitored by the pseudo random signal detector 5. Here, the pseudo-random signal is a signal obtained by a generation formula such as a PN code, for example, and is a signal that can be detected by using the same generation formula when received.

  The switch 1 changes from setting to output the input signal 7 to the transmission device 51 to setting to output a pseudo-random signal received from the switch 3. As a result, the test pattern signal is transmitted to the opposing transmission device 51. At this time, the switch 2 can monitor the signal received from the transmission device 51 in the pseudo random signal detector 5 without performing any change setting.

  The transmission device 51 that has received the test pattern signal outputs a detection flag from the pseudo random signal detector 5 to the switch control circuit 6 because the signal received from the transmission device 50 is a test pattern signal. The switch control circuit 6 receives the detection flag from the pseudo-random signal detector 5, recognizes the execution of the line test, autonomously returns the received test pattern signal to the switches 1 to 3 in the apparatus, and transmits the transmission apparatus. Set to return to 50.

  The switch 2 and the switch 3 are connected so that the received signal can always be monitored by the pseudo-random signal detector 5 without changing the setting. The switch 1 is changed from the setting for outputting the input signal 9 to the transmission device 50 to the setting for outputting the signal received from the switch 3 to the transmission device 50. As a result, the switch setting is made so that the signal received from the transmission apparatus 50 is turned back in the transmission apparatus 51 and returned to the transmission apparatus 50, and the construction of the test system for performing the line test between the transmission apparatus 50 and the transmission apparatus 51 is completed.

  In each transmission device 50, 51, the test pattern signal received from the opposite transmission device is monitored by each pseudo-random signal detector 5, and if the performance of the transmission path deteriorates and the reception state deteriorates, an error bit The number can be counted.

  As for the end of the line test, the input signal 7 is transmitted to the transmission device 51 by setting the line test to be completed from the device control terminal 52, that is, to return to the normal operation state (return to the state of FIG. 4). Become. The pseudo-random signal detector 5 of the transmission apparatus 51 that has received this signal recognizes that the line test has been completed when the reception of the test signal cannot be confirmed, and autonomously switches to the normal operation state of the switches 1 to 3 inside the apparatus. Control is performed by the switch control circuit 6 so as to return the setting, and a transition from the line test state to the normal operation state is performed.

  In the present invention, the execution of the line test is recognized by detecting the test pattern signal, and the line test should be started from a state in which an error occurs in the received signal due to the deterioration of the transmission path. However, it is conceivable that the test pattern signal cannot be detected and the circuit does not transit to the line test. This can be avoided by providing the pseudo-random signal detector 5 with the protection circuit 43.

  The pseudo-random signal is generally generated using a generation formula, and is generated by being processed in units of a bit width corresponding to the generation formula. Signal errors due to transmission path degradation often occur intermittently, and there are times when it looks normal, so in the received signal, the same number of continuous bit strings as the bit width that is the processing unit by the pseudo-random signal generation formula If no error is detected in 1 bit, the test signal reception flag is immediately notified by the test signal detection flag to make a transition to the line test. By setting an arbitrary threshold for the number of error bits included in a unit time and providing protection that is released only when the threshold is satisfied, the number of error bits on the transmission line that can be found during a line test can also be counted. it can. Even if a bit error exceeding this test cancellation threshold is seen and the test state is canceled, if the threshold is set so that it can be determined that the transmission path is defective (for example, disconnection or the like), transmission path deterioration or transmission path failure can be determined. This can be done and there is no hindrance as a circuit test.

  In the above embodiment, it is necessary to terminate the received signal because the line test is determined based on whether or not the test pattern signal is detected and the overhead information of the signal to be transmitted is not used as in the conventional transmission apparatus. Therefore, the line test setting process in the transmission apparatus can be simplified and automated.

  In the above embodiment, the test pattern signal only needs to be uniquely determined and incorporated regardless of the signal speed and interface type. Therefore, the same test circuit configuration can be used regardless of the type of signal normally handled. The port can handle signals of different data types as needed.

  Next, a second embodiment of the transmission apparatus according to the present invention will be described in detail with reference to the drawings.

  FIG. 7 is a block diagram showing a second embodiment of the transmission apparatus according to the present invention. In FIG. 7, the same components as those of the transmission apparatus shown in FIG.

  In the figure, the switch 1 selects an output signal 7 and one output signal of the switch 3 individually at each of the two output terminals according to a switch control signal output from the switch control circuit 6. Do. The switch 2 selects and outputs the input signal 9 and one output signal of the switch 1 individually at each of the two output terminals by the switch control signal output from the switch control circuit 6. The switch 3 individually selects one of the output signals of the switch 2 and the output of the test signal generator 60 at each of the two output terminals by the switch control signal output from the switch control circuit 6 and outputs the output. Do.

  The test signal generator 60 inserts a test recognition pattern signal for recognizing that it is a test signal into an arbitrary pseudo-random signal at a constant period, and outputs it as a test pattern signal.

  The test signal detector 61 monitors one output signal of the switch 3 and determines whether or not the test recognition pattern signal generated by the test signal generator 60 is included in the output signal. When the pattern signal is detected, the pseudo random signal detector 62 is notified that the output signal of the switch 3 is a test pattern signal.

  When the pseudo-random signal detector 62 receives a notification from the test signal detector 61 that the test pattern signal has been detected, the pseudo-random signal detector 62 starts monitoring the pseudo-random signal in the test pattern signal and detects the pseudo-random signal. In response to this, a detection flag signal is output. On the other hand, if the pseudo random signal in the test signal is not the expected pattern, error information is output and the number of error bits is counted based on the error information.

  The switch control circuit 6 selects either the line test control signal 11 from the outside or the detection flag signal output from the pseudo random signal detector 62 as the line test control signal, and performs switch control on the switches 1 to 3. Output a signal.

  Next, a detailed configuration of the test signal generator 60 will be described with reference to FIG. The test signal generator 60 can be composed of, for example, a counter 70, a pseudo random pattern generator 71, a test recognition pattern generator 72, and a selector 73.

  In the figure, a counter 70 is a free-run counter capable of counting an arbitrary number. The count value of the counter 70 is output to the pseudo-random pattern generator 71, the test recognition pattern generator 72, and the selector 73, respectively.

  The pseudo random pattern generator 71 generates and outputs a pseudo random signal such as a PN code. The pseudo random pattern generator 71 has a function of stopping output according to the count value of the counter 70.

  The test recognition pattern generator 72 generates a predetermined fixed pattern signal and outputs it as a test recognition pattern signal. The test recognition pattern generator 72 also has a function of stopping output in accordance with the count value of the counter 70, similarly to the pseudo random pattern generator 71.

  The selector 73 selectively outputs a pseudo random signal generated by the pseudo random pattern generator 71 and a test recognition pattern signal generated by the test recognition pattern generator 72 according to the count value output from the counter 70. And output as a test pattern signal. For example, as shown in FIG. 9, while the count value of the counter 70 is between 0 and 10, the test recognition pattern signal output from the test recognition pattern generator 72 is selected and output, and the count value of the counter 70 is Between 11 to 99, the pseudo random signal output from the pseudo random pattern generator 71 is selected and output. Thus, it is possible to generate a test pattern signal including a test recognition pattern signal and a pseudo random signal.

  Next, a detailed configuration of the test signal detector 61 will be described with reference to FIG. The test signal detector 61 can be composed of a comparison circuit 80 and a protection circuit 81, for example.

  In the figure, the comparison circuit 80 compares the output signal of the switch 3 that is an input signal with a signal having the same pattern as the fixed pattern signal set as the test recognition pattern signal by the bit length of the fixed pattern signal, and expects it. When the same pattern as the fixed pattern signal is detected, a detection flag is output.

  The protection circuit 81 holds the state of the detection flag for any time longer than the period in which the test recognition pattern signal is inserted in the test signal, outputs a test signal reception notification, and outputs the switch 3 The pseudo random signal detector 62 is notified that the test pattern signal is output from the terminal. On the other hand, if the detection flag is not input even after a longer time than the holding time, the state of the test signal reception notification is changed, and the test pattern signal is not output from the output terminal of the switch 3. Notice. As a result, when a test pattern signal is continuously input, a test signal reception notification indicating reception of the test pattern signal is output, and when the input of the test pattern signal is completed, the test pattern signal is not received. It is possible to output a test signal reception notification indicating.

  Next, a detailed configuration of the pseudo random signal detector 62 will be described with reference to FIG. The pseudo random signal detector 62 can be composed of, for example, a pseudo random signal detection circuit 90, a counter 91, and a protection circuit 92.

  The pseudo-random signal detection circuit 90 compares, for example, an input signal and a pseudo-random signal generated by an expected generation formula by taking an exclusive OR, like a PN code detector. A pulse signal representing whether or not matches in bit units is output. The pseudo random signal detection circuit 90 operates according to the detection enable signal, and can stop the detection operation of the pseudo random signal by activating the detection enable signal.

  The counter 91 accumulates the number of error bits by counting the number of pulses of the pulse signal output from the pseudo random signal detection circuit 90. Based on the error count value output from the counter 91, the protection circuit 92 internally sets an arbitrary threshold value and issues or cancels the test signal detection flag.

  Next, the implementation and cancellation operation of the inter-device line test using the transmission apparatus of FIG. 7 having the above configuration will be described with reference to FIGS.

  12 and 13 show a configuration in an operating state when the transmission apparatuses shown in FIG. 7 are connected to face each other. As in FIGS. 5 and 6, the solid lines in the drawings indicate effective transmission of signals, and the broken lines indicate signals treated as invalid. The arrows in the switches 1 to 3 indicate which signal is selected and output from the two input signals.

  First, in describing the line test method according to the present embodiment, the operation during normal operation of the transmission apparatus shown in FIG. 7 will be briefly described with reference to FIG.

  During normal operation, the switches 1 to 3 of the transmission apparatuses 100 and 101 are set so that a signal transmitted from the opposite transmission apparatus is output as an output signal, as in FIG. The switches 2 and 3 are set so that the signal input from the opposite transmission device is branched and output to the test signal detector 61 and the pseudo random signal detector 62 in either of the transmission devices 100 and 101. The devices 100 and 101 are in a state of monitoring whether or not a test signal is received.

  Next, the line test method according to the present embodiment will be described with reference to FIG.

  When the operator performs line test execution control via the apparatus control terminal 52 from the normal operation state shown in FIG. 12, the start of the line test is notified to the switch control circuit 6 of the transmission apparatus 100, and Line test settings are made for switches 1 to 3. At this time, the state of each switch in the transmission apparatus 100 is as follows.

  The switch 3 outputs the output of the test signal generator 60 to the switch 1 so that the test pattern signal can be output to the transmission apparatus 101, and detects the signal received from the transmission apparatus 101 to the other output. The setting is changed so that the monitor 61 and the pseudo random signal detector 62 can monitor.

  The switch 1 changes from the setting for outputting the input signal 7 to the transmission apparatus 101 to the setting for outputting the test pattern signal received from the switch 3. As a result, the test pattern signal is transmitted to the opposite transmission apparatus 101. At this time, the switch 2 is set to output a signal received from the transmission apparatus 101 to the test signal detector 61 and the pseudo-random signal detector 62 without any change setting. Settings are maintained.

  The transmission apparatus 101 that has received the test pattern signal detects the test recognition pattern signal included in the test pattern signal by the test signal detector 61. Accordingly, the reception of the test pattern signal is recognized, and the pseudo random signal detector 62 is notified of the reception of the test pattern signal. Upon receiving this notification, the pseudo-random signal detector 62 starts monitoring the pseudo-random signal and, when detecting the expected pseudo-random signal from the signal pattern of the test pattern signal, sets the test signal detection flag to the switch control circuit 6. Output.

  The switch control circuit 6 recognizes the execution of the line test by receiving the test signal detection flag from the pseudo-random signal detector 5, and autonomously returns the received test signal to the switches 1 to 3 in the apparatus, Settings are made so as to return to the transmission apparatus 100.

  The switch 2 and the switch 3 are not changed in setting, and the connection is such that the received signal can always be monitored by the test signal detector 61 and the pseudo random signal detector 62. For the switch 1, the setting for outputting the input signal 9 to the transmission apparatus 100 is changed to the setting for outputting the signal received from the switch 3 to the transmission apparatus 100. As a result, a switch setting is made so that a signal received from the transmission apparatus 100 is looped back in the transmission apparatus 101 and returned to the transmission apparatus 100, and the construction of a test system for performing a line test between the transmission apparatus 100 and the transmission apparatus 101 is completed.

  After the construction of the test system is completed, the test pattern signals received from the opposing transmission devices are transmitted to the respective test signal detectors 61 and pseudo-random signal detectors, as in the embodiment shown in FIGS. When the performance of the transmission line deteriorates and the reception state deteriorates, the number of error bits is counted.

  Also in the above embodiment, as in the embodiment shown in FIGS. 1 to 6, it is determined whether or not the line test is performed based on whether or not the test pattern signal is detected, and the overhead of the signal to be transmitted as in the conventional transmission apparatus Since no information is used, it is not necessary to terminate the received signal, and the line test setting process in the transmission apparatus can be simplified and automated.

  In the above embodiment, the test signal detector 61 and the pseudo random signal detector 62 confirm the reception of the test signal by the double test signal confirmation means, and then transition to the line test state. Even in situations where it is difficult to recognize the test signal, such as when the signal is at the same speed as the test pattern signal or when a highly random signal is input, the test signal is prevented from being falsely detected, and transitions to unintended line conditions Can be avoided.

  Next, a third embodiment of the transmission apparatus according to the present invention will be described in detail with reference to the drawings.

  The basic configuration is as shown in FIG. 1, but in this embodiment, as shown in FIG. 14, a clock extraction circuit that extracts a clock from received signal data as shown in FIG. 120 is added. In this case, a clock component is extracted by the clock extraction circuit 120 and used as a clock signal inside the transmission apparatus. However, by using a clock extraction circuit 120 having a wide extractable clock frequency range, It is possible to handle signals of various speeds by using them.

  In this case, there may be a speed difference between the test pattern signal used in the line test and the signal handled during normal operation. However, the pseudo random signal generator 4 for generating the test pattern signal and the test pattern signal are Data that can be handled by the same reception port of the transmission apparatus without changing the test pattern signal speed or coding method by uniquely determining the type of test pattern signal to be handled in the pseudo random signal detector 5 to be detected. The speed can be diversified.

  As shown in FIG. 15, a clock extraction circuit 120 that extracts a clock from the received signal data can be added to the configuration of FIG. In this case as well, the test signal generator 60, the test signal detector 61, and the pseudo random signal detector 62 determine the type of the test pattern signal to be handled, thereby changing the test pattern signal speed and the coding method. Without this, it is possible to diversify the data rate that can be handled by the same receiving port of the transmission apparatus.

  14 and 15, as shown in FIGS. 16 and 17, an input signal is output to the input / output interface of the transmission apparatus after photoelectric conversion to the inside of the apparatus. It is good also as a structure provided with the optical module 160 which outputs an electrical signal to the exterior of an apparatus after an electrical-optical conversion.

1 is a block diagram showing a first embodiment of a transmission apparatus according to the present invention. It is a block diagram which shows the switch of the transmission apparatus of FIG. It is a block diagram which shows the switch control circuit of the transmission apparatus of FIG. It is a block diagram which shows the pseudo random signal detector of the transmission apparatus of FIG. It is a block diagram for demonstrating operation | movement of the transmission apparatus of FIG. It is a block diagram for demonstrating operation | movement of the transmission apparatus of FIG. It is a block diagram which shows 2nd Embodiment of the transmission apparatus concerning this invention. It is a block diagram which shows the test signal generator of FIG. It is a schematic diagram which shows an example of a test pattern signal. It is a block diagram which shows the test signal detector of FIG. It is a block diagram which shows the pseudo random signal detector of FIG. It is a block diagram for demonstrating operation | movement of the transmission apparatus of FIG. It is a block diagram for demonstrating operation | movement of the transmission apparatus of FIG. It is a block diagram which shows 3rd Embodiment of the transmission apparatus concerning this invention. It is a block diagram which shows 4th Embodiment of the transmission apparatus concerning this invention. It is a block diagram which shows 5th Embodiment of the transmission apparatus concerning this invention. It is a block diagram which shows 6th Embodiment of the transmission apparatus concerning this invention.

Explanation of symbols

1 to 3 switch 4 pseudo random signal generator 5 pseudo random signal detector 6 switch control circuit 7 input signal 8 output signal 9 input signal 10 output signal 11 line test control signal 20 selector 21 selector 22 selection control signal 23 selection control signal 30 Selector 40 Clock extraction circuit 41 Test signal detection circuit 42 Counter 43 Protection circuit 50 Transmission device 51 Transmission device 52 Device control terminal 60 Test signal generator 61 Test signal detector 62 Pseudo random signal detector 70 Counter 71 Pseudo random pattern generator 72 Test recognition pattern generator 73 Selector 80 Comparison circuit 81 Protection circuit 90 Pseudorandom signal detection circuit 91 Counter 92 Protection circuit 100 Transmission device 101 Transmission device 110 Transmission device 111 Transmission device 120 Clock extraction circuit 130 Transmission device 131 Transmission device 140 Transmission device 141 Transmission device 150 Transmission device 151 Transmission device 160 Optical module

Claims (5)

A test pattern signal generating means for generating a test pattern signal;
Test pattern signal detecting means for detecting the test pattern signal generated by the test pattern signal generating means;
A transmission apparatus having a line test function, comprising: line test setting means for recognizing reception of the test pattern signal and performing line test setting inside the apparatus. The test pattern signal generation means generates an arbitrary random pattern signal, outputs the random pattern signal as the test pattern signal,
2. The transmission apparatus having a line test function according to claim 1, wherein the test pattern detection means detects the test pattern signal by detecting the random pattern signal. The test pattern signal generating means includes a fixed pattern generating means for generating a predetermined fixed pattern signal and a random pattern generating means for generating an arbitrary random pattern signal, and combining the fixed pattern signal and the random pattern signal. Generating the test pattern signal;
The test pattern signal detection means includes a fixed pattern detection means for detecting the fixed pattern signal and a random pattern detection means for detecting the random pattern signal, and detects the fixed pattern signal and the random pattern signal. 2. The transmission apparatus having a line test function according to claim 1, wherein the test pattern signal is detected. The test pattern signal detection means includes:
A test signal detection circuit that compares an input signal with the test pattern signal by taking an exclusive OR, and outputs a pulse signal indicating that the input signal matches or does not match in bit units;
A counter for counting the number of pulses of the pulse signal output from the test signal detection circuit;
A protection circuit that issues or cancels a test signal detection flag by providing an arbitrary threshold value based on an error count value output from the counter. Transmission equipment with line test function.   5. The transmission apparatus having a line test function according to claim 1, wherein the line test setting means includes a selector having two output terminals.

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