JP2007243370A - Likelihood calculation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To constitute a circuit which detects and holds two kinds of Euclidean minimum values without prolonging a detection time for detecting the two kinds of Euclidean minimum values corresponding to bits of each digit, with a minimum circuit scale while preventing the overlapping of the circuits regarding a likelihood calculation device. <P>SOLUTION: Euclidean distance minimum values common in all bits are successively detected with a one-time processing cycle of inputting all bit-value patterns of a transmission signal by a Euclidean distance minimum value detector 1-1 provided in common to each bit. An Euclidean distance minimum value of a bit value different from a bit value giving the Euclidean distance minimum value common in all bits is detected by a minimum value detection/transition enable generator 1-3 and an Euclidean distance minimum value detector/transition part 1-4, on the basis of the update information of the Euclidean distance minimum value common in all bits outputted during the detection of the Euclidean distance minimum value common in all bits, a bit value giving the minimum value outputted from a bit value holder 1-2 provided so as to correspond to each bit, and the change information of the bit value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a likelihood arithmetic apparatus, and more particularly, in a decoding process in an MLD (Maximum Likelihood Decoding) method, which is one of demodulation methods, in a digital modulation / demodulation communication system using multilevel modulation. The present invention relates to a likelihood calculation device that performs a likelihood calculation of a received signal that is necessary for the above.

  The multi-level modulation method is a digital modulation method in which a signal of a plurality of bits is transmitted at a time by switching phases and amplitudes. QPSK (Quadrature Phase Shift Keying; multi-value number = 4, bit number = 2) and 8PSK (8 Phase Shift Keying; multi-value number = 8, bit number = 3) for forming a multi-value signal by changing the phase, There are 16QAM (16 Quadrature Amplitude Modulation; multi-value number = 16, bit number = 4), 64QAM (multi-value number = 64, bit number = 6), etc., which form a multi-value signal by changing the amplitude.

  These modulation methods are widely used regardless of wired transmission / wireless transmission. Especially, the combination with OFDM (Orthogonal Frequency Division Multiplex) is excellent in terms of frequency utilization efficiency. It has also been put into practical use.

  In the demodulation method using MLD, a replica point is generated in advance from a constellation of a transmission signal corresponding to the number of multi-level modulation signals and a channel estimation value, and a result of a distance calculation between an actual reception signal point of the transmitted signal and a replica point The information of each bit is to be restored with high accuracy by obtaining the likelihood of the received signal from.

  FIG. 8 shows a basic configuration of an MLD receiver. As shown in (a) of the figure, the transmission signal that has passed through the propagation path is input to the reception signal termination unit 8-1, and the channel estimation unit 8-2 calculates the channel estimation value based on the reception signal, The replica calculation unit 8-3 calculates the replica point of the received signal from the channel estimation value and the constellation of the transmission signal, and the Euclidean distance between the replica point and the actual reception signal point is calculated by the Euclidean calculation unit 8-4. Then, the likelihood of the received signal is calculated by the likelihood calculating unit 8-5 based on the Euclidean distance. Then, the turbo decoding unit 8-6 restores information of each bit of the transmission signal using the likelihood information, and the data processing unit 8-7 performs various processes using the restored bit information.

  (B1) in FIG. 8 shows a constellation of each transmission signal transmitted by multilevel modulation of QPSK (multilevel number = 4, bit number = 2), and FIG. 8 (b2) shows channel estimation of the propagation path. The replica point of the signal calculated based on the value is shown, and (b3) in the figure shows the Euclidean distance between the actual received signal point and each replica point.

The likelihood calculation in the likelihood calculation unit 8-5 is calculated by performing the following [Equation 1] for each bit of the bit string representing each transmission signal point of multilevel modulation.
Likelihood of target bit = √ (Minimum Euclidean distance when target bit is “1”) − √ (Minimum Euclidean distance when target bit is “0”) [Equation 1]

  FIG. 9 shows a configuration of a conventional likelihood calculation circuit. As shown in the figure, the minimum value of the Euclidean distance when the bit value is “0” is held for each of N bits (bit 0 to bit (N−1)) representing the transmission signal point. 1 minimum value holding circuit 9-1, second minimum value circuit 9-2 holding the minimum value of the Euclidean distance when the bit value is “1”, and first and second minimum value holding circuits 9. And subtracting circuit 9-3 for calculating the difference between the minimum values held in -1 and 9-2, respectively.

A bit value pattern of all transmission signals ( ^2N ) is sequentially input to a circuit corresponding to each bit (bit0 to bit (N-1)), and first and second minimum values corresponding to each bit. In the holding circuits 9-1 and 9-2, every time a different bit value pattern is input in sequence, the Euclidean distance between the replica point corresponding to the bit value pattern and the received signal point, and the Euclidean input previously input When the Euclidean distance input this time is smaller than the minimum value of the distance, the Euclidean distance is determined as the minimum value and held. By repeating this operation until input of all bit value patterns is completed, the final minimum value is held in the first and second minimum value holding circuits 9-1 and 9-2.

  As an example, the likelihood calculation in the case of 16QAM (multi-level number = 16, bit number = 4) will be described with reference to FIGS. FIG. 10 shows the configuration of a 16QAM conventional likelihood arithmetic circuit. As shown in the figure, the first value that holds the minimum value of the Euclidean distance when the bit value is “0” corresponding to each of the four bits (bit 0 to bit 3) representing the 16 transmission signal points. The minimum value holding circuit 10-1, the second minimum value circuit 10-2 that holds the minimum value of the Euclidean distance when the bit value is “1”, and the first and second minimum value holding circuits 10-1. And 10-2, a subtracting circuit 10-3 for calculating a difference between the minimum values respectively held in 10-2.

As shown in FIG. 11, 16 (= 2 ⁴ ) bit value patterns ('0000' to '1111') are sequentially input to the circuit corresponding to each bit (bit0 to bit3), and each bit corresponds. In each of the first and second minimum value holding circuits 10-1 and 10-2, each time a bit value pattern is input, the Euclidean distance of the bit value pattern and the minimum value of the Euclidean distance input in the past The minimum value of the Euclidean distance is held while being updated, and the final Euclidean minimum value is changed to the first and second minimum value holding circuits 10-1 and 10 by the completion of input of all bit value patterns. -2.

FIG. 11 shows an example of the Euclidean distance (EucLen) of each bit value pattern. In this example,
(1) The minimum value of Euclidean distance when the value of bit0 is “0” is “2”,
(2) The minimum value of Euclidean distance when the value of bit0 is “1” is “5”,
(3) The minimum value of Euclidean distance when the value of bit1 is “0” is “3”,
(4) The minimum value of Euclidean distance when the value of bit1 is “1” is “2”,
(5) The Euclidean distance minimum value with a bit2 value of “0” is “5”,
(6) The minimum value of Euclidean distance when the value of bit2 is “1” is “2”,
(7) The minimum value of Euclidean distance when the value of bit3 is “0” is “2”,
(8) The minimum value of Euclidean distance when the value of bit3 is “1” is “4”,
It becomes.

  Therefore, the likelihood of bit0 is √5-√2, the likelihood of bit1 is √2-√3, the likelihood of bit2 is √2-√5, and the likelihood of bit3 is √4-√2.

  Further, instead of the likelihood calculation circuit shown in FIG. 10, as shown in FIG. 12, after the minimum value is detected and determined in advance from the Euclidean distance of all bit value patterns, the bit having the minimum value is obtained. A configuration in which the minimum value of the Euclidean distance is detected for each bit corresponding to the bit value opposite to each bit value of the value pattern may be employed.

  The operation of FIG. 12 will be described in detail. In the case of the Euclidean distance similar to the example of FIG. 11, in the first processing cycle, from the bit value pattern of “0000” to the bit value pattern of “1111” in that order. The minimum value “2” is obtained by examining the distance, and the bit value pattern “0110” giving the minimum value “2” is determined.

  As a result of the end of the first processing cycle, (1) Euclidean distance minimum value '2' when bit0 value is '0', (4) Euclidean distance minimum value when bit1 value is '1'. “2”, (6) Euclidean distance minimum value “2” when the value of bit 2 is “1”, (7) Minimum Euclidean distance value “2” when the value of bit 3 is “0”.

  Next, in the second processing cycle, for the bit value opposite to the bit value pattern '0110' specified in the first processing cycle, from the bit value pattern of '0000' to the bit value pattern of '1111', In turn, the minimum value of the Euclidean distance is detected and determined for each bit.

That is,
Determine the minimum Euclidean distance 5 from '1' for bit 0 (2)
determine the minimum Euclidean distance 3 from '0' for bit 1 (3)
determine the minimum Euclidean distance 5 from bit 0 for '0' (5)
The minimum Euclidean distance 4 from the bit “1” is determined for bit 3 (8).

  As a prior art document related to the present invention, Patent Document 1 below is a parallel estimator that simultaneously performs transmission path estimation and maximum likelihood sequence estimation, and measures likelihood based on transmission path estimation information ( Regarding an MLSE Maximum Likelihood Sequence Estimation) type equalizer, when an estimated value (replica) of a received signal corresponding to a candidate sequence of each transmission signal is obtained and a transmission signal is estimated from a difference between the received signal and a replica of each sequence, A technique for reducing multiplication required for replica generation is described.

Patent Document 2 listed below relates to a soft decision decoding apparatus that decodes a convolutional code to which a polyphase phase modulation method is applied, so that bit likelihood can be easily calculated and reproduction with good bit error rate characteristics is performed. A soft decision decoding apparatus and a soft decision decoding method for obtaining a signal are described. The present invention is based on the premise that the Euclidean distance is used for the likelihood calculation, and is different from that described in Patent Document 2 in which the phase information is used for the calculation.
JP-A-10-126321 JP 2002-314436 A

  As described above, in the conventional likelihood calculation circuit shown in FIG. 9 or FIG. 10, a likelihood calculation circuit corresponding to each bit of the bit string representing the transmission signal point is prepared in parallel, and the bit value is set in each likelihood calculation circuit. The calculation for obtaining the Euclidean minimum value in the case of “0” and “1” is performed, and the calculation of [Expression 1] is performed for each bit.

  At this time, in the calculation for obtaining the two types of Euclidean distance minimum values of “0” and “1” corresponding to each bit, one of the two types of Euclidean distance minimum values is always the other digit. The bit value in the bit overlaps with the Euclidean distance minimum value of either “0” or “1”.

  That is, in the example of FIG. 11, the Euclidean distance minimum value '2' when the bit0 value is '0', the Euclidean distance minimum value '2' when the bit1 value is '1', and the bit2 value are The minimum Euclidean distance value “2” when “1” and the minimum Euclidean distance value “2” when bit3 is “0” overlap. This means that the minimum value holding circuit 10-1 or 10-2 that detects and holds the minimum value provided for bit correspondence of each digit holds the same value in an overlapping manner.

  Also, as shown in FIG. 12, after detecting and determining the minimum value from the Euclidean distance of all the bit value patterns in advance, about the bit value opposite to each bit value of the bit value pattern that has become the minimum value, The configuration for detecting the minimum value of the Euclidean distance corresponding to each bit can avoid duplication of the two types of minimum value detection holding circuits provided for the bit correspondence of each digit, but the two types of Euclidean minimum values corresponding to each bit. As a processing time for detecting, two processing cycles are required, and the processing time is doubled.

  The present invention detects two types of Euclidean minimum values corresponding to each bit in one processing cycle without extending the detection time for detecting two types of Euclidean minimum values corresponding to the bits of each digit, and each digit. Configures a circuit that detects and holds two types of Euclidean minimum values with the smallest circuit scale without duplicating the circuit that detects and holds the two types of Euclidean minimum values corresponding to two bits, thereby reducing the circuit scale of the likelihood arithmetic unit The purpose is to do.

  The likelihood calculation device of the present invention will be described with reference to FIGS. 1 to 3. (1) The minimum Euclidean distance between each replica point generated from the constellation of each transmission signal and the channel estimation value and the reception signal point For each bit of the bit string representing each transmission signal, and in a likelihood calculation device that calculates the likelihood of the reception signal based on the Euclidean distance, each transmission signal point is provided in common for each bit. In accordance with the order in which all bit value patterns of the bit string representing are input, the minimum Euclidean distance is detected from the Euclidean distance for each bit value pattern, and the Euclidean distance is held as the Euclidean distance minimum value common to all bits. The all-bit common Euclidean distance minimum value (c) and the minimum value update information (d) indicating that there was an update at the time of the update are output. The bit distance of the bit when the minimum value update information (d) is output from the Euclidean distance minimum value detection unit 1-1 is provided for each bit corresponding to the minimum Clid distance detection unit 1-1. And a bit value holding unit 1-2 for outputting the bit value (e) and bit value update information (ki) indicating that the bit value has been updated, and the Euclidean distance provided for each bit. When the minimum value update information is output from the minimum value detector 1-1 and the bit value update information (g) of the bit is simultaneously output from the bit value holding unit 1-2, the Euclidean distance minimum value is detected. The bit of the bit string representing the respective transmission signal points, which transitions from the unit 1-1 to the all-bit common Euclidean distance minimum value (c) immediately before the update, holds as the Euclidean distance minimum value (f) for each bit. The minimum Euclidean distance is detected from the Euclidean distance (A) of the bit value pattern having a bit value opposite to the bit value output from the bit value holding unit 1-2 in the order in which the patterns are input. A Euclidean distance minimum value detection / transition unit 1-4 that holds the Euclidean distance as a bit-wise Euclidean distance minimum value (K), and the bit-wise Euclidean distance minimum value (K) and the Euclidean distance common to all bits The likelihood of the received signal is calculated for each bit based on the minimum value (c).

  (2) The Euclidean distance minimum value detecting unit 1-1 is held by the holding unit 1-12 that writes and holds the value of the Euclidean distance for each bit value pattern that is sequentially input, and the holding unit 1-12. And a comparator 1-11 that compares the value of the newly input Euclidean distance with the value of the Euclidean distance, and the comparator 1-11 inputs a new value from the value held by the holding unit 1-12. When the value of the Euclidean distance is smaller, the writing of the holding unit is validated.

  (3) The bit value holding unit 1-2 writes and holds sequentially inputted bit values, and newly inputs the value (e) held in the holding unit 1-23. A discrepancy detector 1-21 for detecting a discrepancy with the measured bit value, and a logical product of the detection result of the discrepancy detector 1-21 and the minimum value update information from the Euclidean distance minimum value detector 1-1. A logical product operation unit 1-22 that performs an operation, and outputs the logical output of the logical product operation unit 1-22 as the bit value update information (ki). The writing of the holding unit 1-23 is validated.

  Further, (4) performing a logical product operation of the minimum value update information (d) from the Euclidean distance minimum value detection unit 1-1 and the bit value update information (ki) from the bit value holding unit 1-2, Based on the result of the logical product operation, the Euclidean distance minimum value detection / transition unit 1-4 transitions from the Euclidean distance minimum value detection unit 1-1 to the all-bit common Euclidean distance minimum value (c) immediately before the update. A transition enable signal (K) that activates the processing to be performed, and when a mismatch between the bit value (e) output from the bit value holding unit 1-2 and the input bit value is detected, A minimum value detection / transition enable signal that outputs a minimum value detection enable signal (Q) for enabling processing for detecting the minimum Euclidean distance (A) to the Euclidean distance minimum value detection / transition unit 1-4. Characterized by comprising a Le generator 1-3.

  (5) The Euclidean distance minimum value detection / transition unit 1-4 includes all bits common Euclidean distance minimum value (c) from the Euclidean distance minimum value detection unit 1-1 and each bit sequentially input. A selection unit 1-41 that selects and outputs any one of the Euclidean distances (a) for each value pattern, a holding unit 1-45 that writes and holds a value output from the selection unit 1-41, and a new And a comparator 1-42 for outputting logical information indicating that the Euclidean distance (a) for each bit value pattern input to is smaller than the value held in the holding unit 1-45, and the transition enable signal described above Is input, the selection unit 1-41 selects and outputs the all-bit common Euclidean distance minimum value (C), and the transition enable signal (K) is ORed. -4 To the holding unit 1-45 to validate the writing of the holding unit 1-45, and when the transition enable signal (K) is not input, the minimum value detection enable signal (K) and The logical output of the logical product operation with the logical information from the comparator 1-42 is given to the holding unit 1-45 via the logical sum calculating unit 1-44, and the holding of the Euclidean distance (A) is performed. The writing to the unit 1-45 is validated.

  According to the present invention, the Euclidean distance minimum value detection unit provided in common for each bit can minimize the Euclidean distance common to all bits in one processing cycle in which all of the bit value patterns of the transmission signal are input in a single cycle. The value is detected sequentially, and based on the update information of the Euclidean distance minimum value common to all bits, the bit value at that time, and the change information, a bit value different from the bit value that gives the minimum Euclidean distance common to all bits is corresponding to each bit. By detecting the Euclidean minimum value, two types of Euclidean minimum values corresponding to each bit can be detected in one processing cycle without extending the detection time, and two types corresponding to each digit bit. The Euclidean minimum value of the Euclidean minimum value is not duplicated, and the two Euclidean minimum values are detected and held with the simplest circuit. A circuit can be formed, it is possible to reduce the circuit scale of the likelihood calculation unit.

  FIG. 1 shows an example of the configuration of the likelihood calculation apparatus of the present invention. The likelihood calculation apparatus of the present invention includes a Euclidean distance minimum value detection unit 1-1 that is commonly used for each bit, and the Euclidean distance minimum value detection unit 1-1 performs the calculation on all bit value patterns to be calculated. The minimum value of the Euclidean distance is detected and held in the order in which each bit value pattern is input, the minimum value of the Euclidean distance (c) and the minimum value update information (d) indicating that there was an update at the time of the update. Is output. The Euclidean distance minimum value (c) finally detected by the Euclidean distance minimum value detector 1-1 is used as the Euclidean distance minimum value common to all bits.

  For each bit, a bit value holding unit 1-2, a minimum value detection / transition enable generation unit 1-3, a Euclidean distance minimum value detection / transition unit 1-4, and a subtraction unit 1-5 are provided. The bit value holding unit 1-2 is enabled by the minimum value update information (D) output from the Euclidean distance minimum value detecting unit 1-1, holds the bit value input at that time, and is an Euclidean distance common to all bits. The bit value (e) when the minimum value is updated and the bit value update information (g) indicating that the bit value is updated are output when the bit value is updated.

  The minimum value detection / transition enable generation unit 1-3 has an input bit value (A) delayed by one clock, a minimum value update information (E) common to all bits common Euclidean distance, and a bit value of a common Euclidean distance minimum value common to all bits. (E) and bit value update information (g) are monitored, and a minimum value detection enable signal (g) and a minimum value transition enable signal (g) are generated according to the information.

  The minimum value detection enable signal (Q) is a minimum Euclidean distance (hereinafter referred to as a bit) in a bit value pattern having a bit value opposite to the value of each bit of the bit value pattern that gives the Euclidean distance minimum value common to all bits. This is an enable signal for detecting another Euclidean distance minimum value).

  Also, the minimum value transition enable signal (K) indicates that the all-bit common Euclidean distance minimum value is updated at the same time when the all-bit common Euclidean distance minimum value is updated and the bit value is updated at the same time. Therefore, the Euclidean distance minimum value common to all bits immediately before the update is moved from the Euclidean distance minimum value detection unit 1-1 to the Euclidean distance minimum value detection / transition unit 1-4 ( Enable signal for transition).

  The Euclidean distance minimum value detection / transition unit 1-4 transitions the Euclidean distance common to all bits from the Euclidean distance minimum value detection unit 1-1 when the above-described minimum value transition enable signal (K) is valid, and sets the Euclidean distance by bit. When the minimum value detection enable signal (c) described above is valid, it is stored as the minimum distance value, and the past Euclidean distance minimum value for each bit held by itself is compared with the Euclidean distance (a) that is sequentially input. Then, the smaller value is updated as the bit-by-bit Euclidean distance minimum value, and the finally held value is output as the bit-by-bit Euclidean distance minimum value.

  After the input of the Euclidean distance of all the bit value patterns to be calculated is completed, the subtracting unit 1-5, when the bit value (e) that gives the minimum value of the Euclidean distance common to all bits is “1”, is the Euclidean common to all bits. The Euclidean distance minimum value for each bit is subtracted from the minimum distance value, and the bit value (e) that gives the Euclidean distance minimum value common to all bits is “0”. Subtract the minimum value. The subtraction result is output as the likelihood of the bit. In addition, the value which carried out the square root calculation as needed is used for the Euclidean distance minimum value common to all bits and the Euclidean distance minimum value for each bit.

  FIG. 2A shows the configuration of the aforementioned Euclidean distance minimum value detector 1-1. The Euclidean distance minimum value detection unit 1-1 holds the Euclidean distance input according to the order of each bit value pattern in the flip-flop circuit (FF) 1-12, and the stored Euclidean distance is newly input. The Euclidean distance is compared in magnitude by the comparator 1-11, and the smaller value is held in the flip-flop circuit (FF) 1-12, whereby the Euclidean distance minimum value is detected, and the Euclidean distance minimum value ( C) and minimum value update information (d) indicating that there was an update at the time of the update.

  FIG. 2B shows the configuration of the bit value holding unit 1-2 described above. When the above-described minimum value update information (d) is valid, that is, when the minimum value of the Euclidean distance is updated, the bit value holding unit 1-2 converts the input bit value into a flip-flop circuit (FF) 1-23. And the bit value (e) is output, and when the input bit value is different from the previously held bit value, this bit indicates that the bit value of the minimum value of the Euclidean distance has been updated. Outputs value update information (ki). In order to perform these processes, as shown in the figure, a mismatch detection circuit 1-21, an AND circuit 1-22, and a flip-flop circuit (FF) 1-23 are provided.

  FIG. 2C shows a configuration of the minimum value detection / transition enable generation unit 1-3. The minimum value detection / transition enable generation unit 1-3 compares the input bit value (A) with the bit value (E) of the Euclidean distance minimum value common to all bits by the comparator 1-31, and determines that the values are different. The minimum value detection enable signal (Q) shown is output. Also, the minimum value update information (D) and the bit value update information (G) of the Euclidean distance common to all bits are input to the AND circuit 1-32, and the logical product is generated as a minimum value transition enable signal (K).

  FIG. 3A shows the configuration of the Euclidean distance minimum value detection / transition unit 1-4. The Euclidean distance minimum value detection / transition unit 1-4 detects the Euclidean distance minimum value for each bit, and sequentially inputs the Euclidean distance (A) and the Euclidean distance minimum value together with the sequentially input bit value pattern. The all-bit common Euclidean distance minimum value (c) output from the detector 1-1 is input to the selector 1-41, and the minimum value transition enable signal (ke) is input as a selection control signal of the selector 1-41. When the minimum value transition enable signal (K) is valid ('1'), the Euclidean distance minimum value (U) common to all bits is selected and output, and the minimum value transition enable signal (K) is invalid ('0'). In the case of '), the Euclidean distance (A) that is sequentially input is selected and output.

  Further, the minimum value transition enable signal (K) is added to the flip-flop (FF) circuit 1-45 through the OR circuit 1-44, and when the minimum value transition enable signal (K) is valid ('1'), there is no signal. The minimum Euclidean distance value (U) common to all bits is held in the flip-flop (FF) circuit 1-45 as a condition, and the value is output as the Euclidean minimum value (K) for each bit.

  On the other hand, the Euclidean distance (A) sequentially input and the value held in the flip-flop (FF) circuit 1-45 are compared by the comparator 1-42, and the Euclidean distance (A) input this time is compared. ) Is smaller than the value held in the flip-flop (FF) circuit 1-45, and the AND circuit 1-43 detects that the minimum value detection enable signal (Q) is valid ('1'). The logical value of the detection result is added as a write control signal to the flip-flop (FF) circuit 1-45 through the OR circuit 1-44, and the Euclidean distance (A) input this time is added to the flip-flop (FF) circuit 1-45. And the value of the Euclidean minimum value (f) for each bit is updated.

  FIG. 3B shows the configuration of the subtraction unit 1-5. The subtracting unit 1-5 includes the all-bit common Euclidean distance minimum value (c) output from the Euclidean distance minimum value detection unit 1-1 and the bit-based Euclidean output from the Euclidean distance minimum value detection / transition unit 1-4. The minimum value (f) is input to the first selector 1-51 and the second selector 1-52, and is selected from the bit value holding unit 1-2 as a selection control signal for the selectors 1-51 and 1-52. Input the output bit value (e).

  If the bit value (e) giving the minimum Euclidean distance common to all bits is “1”, the first selector 1-51 selects the minimum Euclidean distance common to all bits (c), and the second selector In 1-52, the Euclidean minimum value (f) for each bit is selected. On the other hand, when the bit value (e) that gives the all-bit common Euclidean distance minimum value is '0', the second selector 1-52 selects the all-bit common Euclidean distance minimum value (c), The first selector 1-51 selects the Euclidean minimum value (f) for each bit.

  All-bit common Euclidean distance minimum value (c) or bit-specific Euclidean minimum value (c) output from the first and second selectors 1-51 and 1-52 is respectively converted into a square root calculator 1 as necessary. Is input to the subtracter 1-55 through -53, 1-54, and the subtracter 1-55 performs the subtraction to determine whether the bit value (e) giving the minimum Euclidean distance common to all bits is “1”. Depending on whether it is '0', the value obtained by subtracting the Euclidean distance minimum value for each bit from the Euclidean distance minimum value for all bits, or the value obtained by subtracting the Euclidean distance minimum value for all bits from the Euclidean distance minimum value for each bit Is output as the likelihood of.

  4 to 7 show specific examples of the operation of the likelihood calculating apparatus according to the present invention. Here, it is assumed that the Euclidean distance of each transmission signal is the Euclidean distance shown in FIG. FIG. 4 is a time chart of the bit 0 likelihood calculation, FIG. 5 is a bit 1 likelihood calculation, FIG. 6 is a bit 2 likelihood calculation, and FIG. 7 is a bit 3 likelihood calculation.

  4 to 7, in order from the top, the Euclidean distance that is the input signal, the bit information that is also the input signal, the minimum value update information (D) output from the Euclidean distance minimum value detector 1-1, and the Euclidean. All-bit common Euclidean distance minimum value (c) output from the minimum distance detection unit 1-1, bit value update information (g) output from the bit value holding unit 1-2, and similarly the bit value holding unit 1-2 The bit value (e) output from the signal, the inverted value (e ') of the bit value (e), the delay information (a) of the bit information which is the input signal, the minimum value detection enable signal (g), the minimum Value transition enable signal (K), input signal Euclidean distance delay information (A) for one clock, and Eucli for each bit output from Euclidean distance minimum value detection / transition unit 1-4 Shows de minimum distance value (f).

  In the bit 0 likelihood calculation shown in FIG. 4, when the minimum Euclidean distance common to all bits (c) changes from “13” to “6”, the bit information of the input signal changes from “0” to “1”. As a result, the bit value update information (ki) becomes “1”, whereby the Euclidean distance changes from “13” to the bit-specific Euclidean distance minimum value (Swap).

  After that, when the bit information is “0” and “12” is input whose Euclidean distance is smaller than “13”, the minimum value detection enable signal (Q) by the minimum value detection (MinSearch) processing becomes “1”. Thus, the Euclidean distance minimum value for each bit is updated from “13” to “12”.

  Next, when the Euclidean distance minimum value (c) common to all bits changes from “6” to “5”, the bit information of the input signal is both “1” and does not change, so the bit value update information (g) Becomes “0”, so that the transition of the Euclidean distance minimum value (c) common to all bits is not performed.

  Next, when the Euclidean distance minimum value (c) common to all bits changes from “5” to “3”, the bit information of the input signal changes from “1” to “0”, thereby the bit value update information ( G) becomes “1”, whereby the Euclidean distance “5” is changed to the Euclidean distance minimum value for each bit (Swap).

  Thereafter, when the all-bit common Euclidean distance minimum value (C) changes from “3” to “2”, the bit information of the input signal is both “0” and does not change, so the common Euclidean distance minimum value (C) No transition is performed. Further, since a value smaller than “5” is not input as the Euclidean distance when the input bit information is “1”, the bit-specific Euclidean distance minimum value (K) is not updated, and the bit-specific Euclidean distance minimum value ( As a result, “5” is finally output. As a result, the likelihood of bit 0 is calculated as √5−√2 obtained by subtracting the Euclidean distance minimum value (U) common to all bits from the Euclidean distance minimum value (K) for each bit.

  In the likelihood calculation of bit 1 shown in FIG. 5, when the minimum Euclidean distance common to all bits (c) changes from “13” to “6”, the bit information of the input signal remains “0” and does not change. For this reason, the bit value update information (K) is “0”, and the transition of the Euclidean distance minimum value (C) common to all bits is not performed.

  After that, when the bit information is '1' and '12' is smaller than '13' and the Euclidean distance is input, the minimum value detection enable signal (Q) by the minimum value detection (MinSearch) processing becomes '1'. Then, an operation to update the bit-by-bit Euclidean distance minimum value from “13” to “12” is performed, but at the same time, the Euclidean distance minimum value (c) common to all bits is changed from “6” to “5”. When the bit information changes, the bit information of the input signal changes from “0” to “1”, so that the bit value update information (K) becomes “1”, which is the Euclidean distance minimum value (U) common to all bits. The transition “Swap” of “6” is performed in preference to the above-described minimum value detection (MinSearch) process.

  Next, when the Euclidean distance minimum value (c) common to all bits changes from “5” to “3”, the bit information of the input signal changes from “1” to “0”, thereby the bit value update information ( G) becomes “1”, whereby the Euclidean distance “5” is changed (Swap) to the Euclidean distance minimum value (f) for each bit.

  Next, when the Euclidean distance minimum value common to all bits (c) changes from “3” to “2”, the bit information of the input signal changes from “0” to “1”. ) Becomes “1”, whereby the Euclidean distance “3” is changed (Swap) to the Euclidean distance minimum value (f) for each bit.

  Thereafter, there is no update of the Euclidean distance minimum value (c) common to all bits, and thereafter, since a value smaller than “3” is not input as the Euclidean distance of which the input bit information is “0”, the bit-specific Euclidean distance The minimum value (f) is not updated, and finally “3” is output as the bit-wise Euclidean distance minimum value (f). Thus, the likelihood of bit 1 is calculated as √2−√3 obtained by subtracting the bit-specific Euclidean distance minimum value (K) from the all-bit common Euclidean distance minimum value (C).

  In the likelihood calculation of bit 2 shown in FIG. 6, when the all-bit common Euclidean distance minimum value (C) changes from “13” to “6”, the bit information of the input signal remains “0” and does not change. For this reason, the bit value update information (K) is “0”, and the transition of the Euclidean distance minimum value (C) common to all bits is not performed.

  Even when the Euclidean distance minimum value (c) common to all bits changes from “6” to “5”, the bit information of the input signal remains “0” and does not change. ) Becomes “0”, and the transition of the Euclidean distance minimum value (c) common to all bits is not performed. Further, during this period, bit information of the value “1” opposite to the bit information “0” of the Euclidean distance minimum value (c) common to all bits is not input, and therefore the minimum value detection (MinSearch) process is not performed.

  Thereafter, when the Euclidean distance minimum value (c) common to all bits changes from “5” to “3”, the bit information of the input signal changes from “0” to “1”. Becomes “1”, and thereby, “5”, which is the Euclidean distance minimum value (c) common to all bits, is changed (Swap) to the Euclidean distance minimum value (f) for each bit.

  Thereafter, when the minimum Euclidean distance (c) common to all bits changes from “3” to “2”, the bit information of the input signal remains “1” and does not change. Therefore, the bit value update information (g) Becomes “0”, so that the transition of the Euclidean distance minimum value (c) common to all bits is not performed.

  Thereafter, there is no update of the Euclidean distance minimum value (c) common to all bits, and since a value smaller than “5” is not input as the Euclidean distance after which the input bit information is “0”, the minimum value detection ( The bit-by-bit Euclidean distance minimum value (K) is not updated by the MinSearch process, and “5” is finally output as the bit-by-bit Euclidean distance minimum value (K). As a result, the likelihood of bit 2 is calculated as √2−√5 obtained by subtracting the bit-specific Euclidean distance minimum value (K) from the all-bit common Euclidean distance minimum value (C).

  In the bit 3 likelihood calculation shown in FIG. 7, when the all-bit common Euclidean distance minimum value (c) sequentially changes from “13” to “6”, “5”, “3”, “2”, The bit information remains “0” and does not change. Therefore, the bit value update information (K) becomes “0”, and the transition of the all-bit common Euclidean distance minimum value (C) is not performed.

  Further, before “2” is output as the all-bit common Euclidean distance minimum value (c), the bit information of the value “1” opposite to the bit information “0” of the all-bit common Euclidean distance minimum value (c) is Since it is not input, the minimum value detection (MinSearch) process is not performed.

  Thereafter, a minimum value detection (MinSearch) process is started for bit information having a value “1” opposite to the bit information “0” of the Euclidean distance minimum value (c) common to all bits, and sequentially input Euclidean distances ( (A) is detected, and “15”, “10”, and “4” are sequentially detected as the Euclidean distance minimum value (f) for each bit, and finally “4” is output. As a result, the likelihood of bit3 is calculated as √4−√2 obtained by subtracting the Euclidean distance minimum value (U) common to all bits from the Euclidean distance minimum value (K) for each bit.

  As mentioned above, although the structural example and the operation example of the likelihood calculating apparatus of this invention were demonstrated with reference to FIGS. 1-7, this invention is not limited to this structural example, In likelihood calculation, Euclidean distance is Any configuration that is input along the time axis is applicable regardless of the number of multi-level modulation signals.

  In addition, when the signal to be calculated is input with a long interval on the time axis, the detection result of the Euclidean distance minimum value and the holding of each bit value are held using a RAM (Random Access Memory). Can be realized. Further, by using a DSP (Digital Signal Processor) or the like and describing the circuit function of the present invention in a program language, the function equivalent to the present invention can be realized.

  As an advantage of the likelihood calculation using the Euclidean distance as in the present invention, the maximum likelihood estimation in the receiving apparatus of the MIMO (Multiple-Input-Multiple-Output) multiplexing communication system composed of a plurality of transmitting antennas It is easy to apply to decoding (MLD), and a table used for calculating phase information and trigonometric function calculation are unnecessary.

It is a figure which shows the structural example of the likelihood calculating apparatus of this invention. It is a figure which shows the Euclidean distance minimum value detection part, bit value holding | maintenance part, minimum value detection / transition enable generation part of this invention. It is a figure which shows the Euclidean distance minimum value detection / transition part of this invention, and a subtraction part. It is a figure which shows the specific example of likelihood calculation operation | movement of bit0 of this invention. It is a figure which shows the specific example of likelihood calculation operation | movement of bit1 of this invention. It is a figure which shows the specific example of likelihood calculation operation | movement of bit2 of this invention. It is a figure which shows the specific example of likelihood calculation operation | movement of bit3 of this invention. It is a figure which shows the basic composition of the receiver of a MLD system. It is a figure which shows the structure of the conventional likelihood calculating circuit. It is a figure which shows the structure of the conventional likelihood calculating circuit of 16QAM. It is a figure which shows the example of the Euclidean distance of each bit value pattern. It is a time chart of the operation | movement which detects the minimum value of the Euclidean distance of a reverse bit value after detecting and determining the minimum value of the Euclidean distance.

Explanation of symbols

1-1 Euclidean Distance Minimum Value Detection Unit 1-2 Bit Value Holding Unit 1-3 Minimum Value Detection / Transition Enable Generation Unit 1-4 Euclidean Distance Minimum Value Detection / Transition Unit 1-5 Subtraction Unit

Claims (5)

The minimum Euclidean distance between each replica point generated from the constellation of each transmitted signal and the channel estimation value and the received signal point is obtained for each bit of the bit string representing each transmitted signal, and the received signal is based on the Euclidean distance. In a likelihood calculation device for calculating likelihood,
The minimum Euclidean distance is detected from the Euclidean distance for each bit value pattern according to the order in which all the bit value patterns of the bit string representing each transmission signal point are input in common for each bit, Euclidean distance minimum value detection unit that holds the Euclidean distance as an all-bit common Euclidean distance minimum value and outputs minimum value update information indicating that there is an update at the time of updating the common Euclidean distance minimum value of all bits;
It is provided for each bit, holds the bit value of the bit when the minimum value update information is output from the Euclidean distance minimum value detection unit, and indicates that the bit value and the bit value have been updated A bit value holding unit for outputting bit value update information;
When the minimum value update information is output from the Euclidean distance minimum value detection unit and the bit value update information is output from the bit value holding unit of the bit at the same time, the Euclidean distance minimum value is prepared for each bit. According to the order in which the bit value pattern of the bit string representing each transmission signal point is input, the Euclidean distance minimum value common to all bits immediately before the update is transitioned from the detection unit and held as the bit-specific Euclidean distance minimum value. The Euclidean distance that detects the minimum Euclidean distance from the Euclidean distance of the bit value pattern having the bit value opposite to the bit value output from the value holding unit, and holds the Euclidean distance as the Euclidean distance minimum value for each bit. A minimum value detection / transition part;
And a likelihood calculation device for calculating a likelihood of a received signal for each bit based on the bit-wise Euclidean distance minimum value and the all-bit common Euclidean distance minimum value. The Euclidean distance minimum value detection unit writes and holds the value of the Euclidean distance for each bit value pattern that is sequentially input, and the value held in the holding unit and the newly input Euclidean distance value And a comparator for comparing the size,
The comparator according to claim 1, wherein when the value of the Euclidean distance newly input is smaller than the value held in the holding unit, the comparator validates writing in the holding unit. Likelihood calculation device. The bit value holding unit writes and holds sequentially inputted bit values, a mismatch detector that detects a mismatch between a value held in the holding unit and a newly input bit value, and the mismatch A logical product operation unit that performs a logical product operation between the detection result of the detector and the minimum value update information from the Euclidean distance minimum value detection unit,
The likelihood calculation device according to claim 1, wherein the logical output of the logical product operation unit is output as the bit value update information, and the writing of the holding unit is validated by the bit value update information. . A logical product operation is performed between the minimum value update information from the Euclidean distance minimum value detection unit and the bit value update information from the bit value holding unit, and based on the result of the logical product operation, the Euclidean distance minimum value detection / transition unit On the other hand, while outputting a transition enable signal that activates the process of transitioning the all-bit common Euclidean distance minimum immediately before the update from the Euclidean distance minimum value detection unit,
Enables the Euclidean distance minimum value detection / transition unit to detect the minimum Euclidean distance when a mismatch between the bit value output from the bit value holding unit and the input bit value is detected. The likelihood calculation device according to claim 1, further comprising a minimum value detection / transition enable generation unit that outputs a minimum value detection enable signal. The Euclidean distance minimum value detection / transition unit selects either the Euclidean distance minimum value common to all bits from the Euclidean distance minimum value detection unit or the Euclidean distance for each bit value pattern that is sequentially input. A selection unit that outputs the data, a holding unit that writes and holds the value output from the selection unit, and a logic that indicates that the Euclidean distance for each newly input bit value pattern is smaller than the value held in the holding unit A comparator that outputs information,
When the transition enable signal according to claim 4 is input, the selection unit selects and outputs a minimum value common to all bits of Euclidean distance, and the transition enable signal is output via the OR operation unit. Give to the holding unit to enable writing of the holding unit,
When the transition enable signal is not input, a logical output of a logical product operation of the minimum value detection enable signal according to claim 4 and the logical information from the comparator is sent via the logical sum operation unit. The likelihood calculation apparatus according to claim 1, wherein the likelihood calculation device is provided to the holding unit and validates writing of the Euclidean distance to the holding unit.

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