JP2007243065A - Circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost circuit board with high reliability by reducing the effect of stress generated by variation in ambient temperature. <P>SOLUTION: The circuit board has a single or a plurality of insulating layers 4 formed on a surface of a base 1 and has a via hole 6 for inter-layer connection with a wiring pattern in the respective layers 4. As the circuit board, a circuit board is used which satisfies a relation of K1>K2<K3 among the coefficient K1 of thermal expansion of a semiconductor element mounted on the circuit board and the coefficients K2 and K3 of thermal expansion of the base 1 and insulating layers 4 and uses a material obtained by impregnating optically transparent reinforcing fiber 2 with photosensitive resin 3 for the insulating layers 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a circuit board for mounting a semiconductor element, and more particularly to a circuit board in which stress generated between the semiconductor element and the semiconductor element due to a change in ambient temperature is reduced.

  A circuit board for mounting a semiconductor element is formed by repeatedly forming a wiring layer and an insulating layer as many times as necessary on a support, and the mounting of the semiconductor element on the circuit board is connected to an internal circuit of the semiconductor element. This is done by soldering the electrode to the electrode formed on the wiring layer on the outermost surface of the circuit board.

  In manufacturing a circuit board, an insulating substrate mainly made of an epoxy resin or a polyimide resin is usually used as a support, and a wiring pattern is formed on the support using a photolithography technique to form a wiring layer. In recent years, a high conductivity metal such as copper is used as a wiring layer material. When the wiring layer is multilayered, the above wiring layer is used as the first wiring layer, and an insulating layer is stacked thereon. As the insulating layer material, a resin material such as an epoxy resin or a polyimide resin, which is the same as the support material, is usually used from the viewpoint of ease of processing and manufacturing cost. Next, a wiring pattern to be a second wiring layer is formed on the insulating layer using the same photolithography technique, and a via hole is formed at a predetermined position of the insulating layer, and the inside is filled with a conductive material, thereby The first and second wiring layers are electrically connected. For the formation of the via hole, a dry etching method using a plasma process or a so-called laser drilling method in which a laser beam is irradiated to make a hole in an insulating layer is generally used. By repeating the steps as described above, the wiring layer is multi-layered.

  Usually, in an electronic device, a semiconductor element is used in a state of being mounted on a circuit board. For this reason, with the progress of miniaturization and high density of electronic devices, there is a demand for high density and high precision for circuit boards. The via holes connecting the wiring layers are also required to have a smaller diameter and high dimensional processing accuracy.

  However, when the dry etching method is used for forming the via hole, it is difficult to ensure sufficient dimensional processing accuracy due to the influence of side etching. On the other hand, the laser drilling method can ensure dimensional processing accuracy, but the circuit board. When the wiring pattern density is increased and the number of via holes is increased, processing takes time and the manufacturing cost increases.

  In addition, the thermal expansion coefficient of silicon, which is the main material of the semiconductor element, is about 3 ppm, whereas the thermal expansion coefficient of epoxy resin and polyimide resin generally used as a material for the support and insulating layer constituting the circuit board. Reaches a size of about 12 to 15 ppm. Therefore, when a semiconductor element is mounted on a circuit board, when the ambient temperature changes greatly due to a change in the usage environment of the electronic device or heat generated from the operating semiconductor element, the circuit board is caused by a difference in thermal expansion coefficient. A positional shift occurs in the semiconductor element mounted thereon, and a large stress is applied to the semiconductor element accordingly, which causes a decrease in the reliability of the circuit board on which the semiconductor element is mounted. In particular, the influence of the stress applied to the semiconductor element from the support that occupies most of the circuit board volume is large.

  Therefore, an attempt has been made to suppress as much stress as possible when the semiconductor element is mounted on the circuit board by using a material having a smaller coefficient of thermal expansion than that of the semiconductor element as a support for the circuit board. Examples of such a support material include carbon fiber reinforced plastic and Invar alloy whose surface has been subjected to insulation treatment. These materials have a coefficient of thermal expansion of about 1 to 2 ppm, and by using this, it is possible to reduce the above-mentioned positional deviation of the semiconductor element and to reduce the stress applied from the support to the semiconductor element. . However, when using the same epoxy resin or polyimide resin as the insulating layer material formed on the support made of such a material having a small coefficient of thermal expansion, cracks are generated in the vicinity of the opening of the via hole when the via hole is formed. There is a problem that it becomes easy.

  When an insulating layer having a thermal expansion coefficient of about 12 to 15 ppm is laminated on a support having a thermal expansion coefficient of about 1 to 2 ppm, a large new stress is applied to the insulating layer at the joint between the support and the insulating layer. . The stress on the insulating layer is widely dispersed throughout the insulating layer as long as the insulating layer is uniformly formed on the support with a thickness of about several tens of μm, and does not significantly affect the semiconductor element or the circuit board. The stress uniformly distributed throughout the insulating layer is concentrated in the vicinity of the opening of the via hole due to the local non-uniformity generated in the insulating layer film thickness due to the impact applied to the insulating layer during laser drilling or the formation of the via hole. . And it is thought that a crack generate | occur | produces in an insulating layer by using this as a trigger. In order to avoid such a situation, it is necessary to use a material having a thermal expansion coefficient comparable to that of the support as the insulating layer material. However, in terms of the ease of processing and the manufacturing cost described above, epoxy resin, polyimide resin, etc. The use of resin materials is unavoidable at present.

  Therefore, a method of forming a via hole by a photo process using a photosensitive resin as a material of an insulating layer has been proposed (Patent Document 1). In this method, it is possible to divert the manufacturing technique such as an exposure / development apparatus usually used for manufacturing a circuit board and a photolithography technique using the same without preparing processing equipment such as a laser drilling apparatus. The manufacturing cost can be reduced, and a fine and highly accurate via hole can be formed without impact during processing by laser drilling.

  However, this method has a problem that the photosensitive resin applied to the support is easily peeled off from the support under the influence of heat treatment or the like in a later step, and there is a problem with the strength of the photosensitive resin itself. Therefore, there is a problem that the reliability of the circuit board decreases. In addition, there still remains a risk that stress that has been uniformly dispersed throughout the insulating layer due to the formation of the via hole is concentrated in the vicinity of the opening of the via hole.

On the other hand, in the prior art (Patent Document 2) in which glass fibers are mixed in a photosensitive resin for the purpose of increasing the strength of the photosensitive resin and this is used as an insulating layer of a circuit board, a photo without using a method such as laser drilling. Via holes can be formed by the process, and furthermore, the stress applied from the support to the insulating layer can be made uniform through the glass fibers.
JP-A-9-64538 JP-A-53-123871

  The method of mixing glass fiber in a photosensitive resin and using this as an insulating layer of a circuit board can reduce the manufacturing cost because a via hole can be formed by a photo process without using a method such as laser drilling. In addition, the stress applied to the insulating layer can be made uniform through the glass fiber. However, since the purpose of mixing glass fibers was to increase the hardness of the insulating layer in the past, the structure of the glass fibers mixed in the photosensitive resin was not optimized, so problems remained in the dimension processing accuracy of via holes, It did not necessarily contribute to improving the reliability of the circuit board.

  Accordingly, an object of the present invention is to provide a circuit board having a low cost and high reliability by reducing the influence of stress caused by a change in ambient temperature.

A solution to the above problem is that a single or multiple insulating layers are formed on the surface of the support, and each insulating layer is provided with a wiring pattern and via holes for interlayer connection. The thermal expansion coefficient K1 of the semiconductor element to be satisfied and the thermal expansion coefficients K2 and K3 of the support and the insulating layer satisfy the relationship of K1> K2 <K3, and an optically transparent reinforcing fiber is photosensitive as the insulating layer material. A circuit board characterized by using a resin impregnated with a conductive resin,
Alternatively, in the circuit board, the reinforcing fiber is a glass fiber,
Alternatively, in the above circuit board, the support is formed by a circuit board formed of a composite using carbon fiber as a reinforcing material.

  In the circuit board according to the present invention, the thermal expansion coefficient of the entire circuit board is increased by laminating an insulating layer having a thermal expansion coefficient larger than that of the support on the support having a smaller thermal expansion coefficient than the semiconductor element to be mounted. As a result, the stress applied to the semiconductor element is reduced. In addition, by using an optically transparent reinforcing fiber impregnated with a photosensitive resin as an insulating layer material, via holes can be formed on the insulating layer using ordinary photolithography technology, and dry etching is performed. As compared with the case where the method or the laser drilling method is used, it is possible to reduce the manufacturing cost and to form the via hole with high accuracy without giving a local impact to the insulating layer. In addition, even if the insulating layer thickness becomes non-uniform due to the formation of via holes, the stress applied to the insulating layer is uniformly borne by the reinforcing fiber, so cracks are avoided by avoiding stress concentration on the via hole opening. Can be prevented.

  In addition, by making the gap between fibers in the reinforcing fiber smaller than the thickness of the fiber, the transmittance of exposure light in the photolithography process can be made more uniform, and deterioration of dimensional processing accuracy with respect to the wiring pattern and via hole diameter can be prevented. it can.

  In producing the circuit board according to the present invention, first, an insulating layer made of an optically transparent reinforcing fiber impregnated with a photosensitive resin is laminated on the surface of the support. A silicon LSI is used as a semiconductor element mounted on a circuit board, and a composite made of carbon fiber as a reinforcing material is used for a support as a material having a thermal expansion coefficient smaller than that of silicon. This material is easy to handle because it has properties similar to those of conventionally used epoxy resins, and its thermal expansion coefficient is as low as 1-2 ppm, compared to about 12 ppm for epoxy resins. It is suitable for a support because it has a strength reaching 5 times as high as 100 GPa. In addition to the composite, a material obtained by insulating the surface of the Invar alloy can also be used. A cloth in which glass fibers are woven vertically and horizontally is used as an optically transparent reinforcing fiber, and photosensitive polyimide is used as a photosensitive resin.

  For the insulating layer laminated on the support, a via hole having a predetermined diameter is formed at a predetermined position by a normal photolithography technique. The cloth woven with glass fiber is transparent to the exposure light irradiated in the photolithography process, so it does not interfere with the formation of the via hole pattern. It causes a decrease. In order to prevent this, the so-called flattening treatment is applied to the glass fiber in order to make the surface distribution of the glass fiber amount in the thickness direction of the insulating layer more uniform so that the gap between the glass fibers is smaller than the thickness of the glass fiber itself. It is effective to carry out against this.

  After the via hole is formed in the insulating layer on the support as described above, the inside of the via hole is used for connection between the buried wiring layers with a conductive material such as copper by plating. Then, a wiring pattern is formed thereon. By repeating the above steps, a circuit board having a multilayered wiring layer can be obtained.

  FIGS. 1A to 1D are process sectional views for explaining an embodiment of the present invention. The support 1 is made of a composite using carbon fiber as a reinforcing material, and its coefficient of thermal expansion is about 1 ppm. The reinforcing fiber 2 is made of cloth made of glass fibers having a diameter of about 7 μm bundled and woven vertically and horizontally. The reinforcing fiber 2 impregnated with the photosensitive resin 3 is used as the insulating layer 4 of the circuit board. The cloth woven with glass fibers is flattened so that the transmittance of light irradiated in the subsequent exposure process is made as uniform as possible to increase the dimensional processing accuracy. Photosensitive polyimide can be used as the photosensitive resin 3.

  First, as shown in FIG. 1A, the reinforcing fiber 2 is impregnated with an unphotosensitized and uncured photosensitive resin 3 and laminated on the surface of the support 1 in a heating environment at a temperature of 180 ° C. to a thickness of 40 μm. The insulating layer 4 is formed.

  Next, as shown in FIG. 1B, exposure is performed through a chrome mask 5 from above the insulating layer 4 laminated according to a normal photolithography technique.

  Next, as shown in FIG. 1C, the via-hole 6 is formed by developing the selectively exposed photosensitive polyimide 3. When the thickness of the insulating layer 4 was 40 μm, the via hole 6 with an opening diameter of 80 μm could be formed with high accuracy by setting the exposure amount of irradiation light in the photolithography process using a mercury lamp as a light source to 600 mJ.

  After the via hole 6 was formed, the photosensitive polyimide 3 was cured by heat treatment at 400 ° C. for 1 hour. As a result, the insulating layer 4 is formed with the reinforcing fibers 2 penetrating the via holes 6.

  Next, copper is deposited on the entire surface including the bottom surface of the via hole 6 by electroless copper plating. Subsequently, by performing electrolytic copper plating, the inside of the via hole 6 is filled with copper and the surface is polished by the CMP method, so that an interlayer connection material 7 made of copper can be formed as shown in FIG.

By repeating the above steps, a circuit board having five wiring layers could be formed without causing cracks in the insulating layer.
(Supplementary note 1) A circuit board in which a single layer or a plurality of layers of insulating layers are formed on the surface of a support, and a wiring pattern and via holes for interlayer connection are formed in each insulating layer. Photosensitive resin is used for the optically transparent reinforcing fiber as the insulating layer material, in which the thermal expansion coefficient K1 of the semiconductor element and the thermal expansion coefficients K2 and K3 of the support and the insulating layer satisfy the relationship of K1> K2 <K3. What is impregnated with a circuit board is used.
(Additional remark 2) The said reinforcing fiber is the said circuit board characterized by the clearance gap between fibers being smaller than the thickness of a fiber.
(Additional remark 3) The said reinforcing fiber is a glass fiber, The said circuit board characterized by the above-mentioned.
(Additional remark 4) The said support body is formed with the composite which uses carbon fiber as a reinforcing material, The said circuit board characterized by the above-mentioned.

  The present invention is effective in improving the reliability of a circuit board by reducing the stress of the circuit board caused by a change in the ambient temperature of the circuit board or a temperature change caused by heat generated by a semiconductor element to be mounted.

Process sectional drawing which shows the manufacturing method of the circuit board based on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support body 2 Reinforcing fiber 3 Photosensitive resin 4 Insulating layer 5 Chrome mask 6 Via hole 7 Interlayer connection material

Claims (3)

In a circuit board in which a single layer or a plurality of insulating layers are formed on the surface of the support, and a wiring pattern and a via hole for interlayer connection are formed in each insulating layer,
The thermal expansion coefficient K1 of the semiconductor element mounted on the circuit board and the thermal expansion coefficients K2 and K3 of the support and the insulating layer satisfy the relationship of K1> K2 <K3, and are optically transparent as the insulating layer material What is claimed is: 1. A circuit board using a reinforced fiber impregnated with a photosensitive resin.   The circuit board according to claim 1, wherein the reinforcing fiber is a glass fiber. The circuit board according to claim 1, wherein the support is formed of a composite having carbon fiber as a reinforcing material.

Images