JP2007242907A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which plans to reduce a switching loss by efficiently drawing out minority carriers remaining in a reduced surface field region at the time of turnoff. <P>SOLUTION: On a front surface of a semiconductor substrate 100, a reduced surface field region 101 and a base region 102 are formed to be mutually adjacent. A gate electrode 106 is formed on the base region 102. An emitter region 104 is formed in the base region 102. While a collector region 107 being formed in the reduced surface field region 101, a summit semiconductor layer 110 electrically connected with the base region 102 is formed so as to be isolated from the collector region 107. A second gate electrode 113 is formed on the reduced surface field region 101. Moreover, there are provided a collector electrode 109 electrically connected with the collector region 107; and an emitter electrode 115 electrically connected with the base region 102, the emitter region 104, and the second gate electrode 113. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a high breakdown voltage lateral insulated gate bipolar transistor.

  As a high-voltage semiconductor device using a Si substrate, for example, a power MOSFET has been developed mainly for use as a power control element, but in recent years, it has both high-voltage and large-current processing capability and consumes less power. Insulated gate bipolar transistors (hereinafter referred to as “IGBTs”) have attracted attention, and IGBTs having various structures have been proposed.

  Hereinafter, as a semiconductor device according to a first conventional example, a typical high breakdown voltage lateral IGBT having a RESURF structure will be described with reference to FIG. FIG. 8 is a cross-sectional view showing the structure of the semiconductor device according to the first conventional example.

As shown in FIG. 8, an N-type RESURF region 401 and a P-type base region 402 are formed on the surface of the P ⁻ -type semiconductor substrate 400.

A P ⁺ -type contact region 403 and an N ⁺ -type emitter region 404 are formed in the base region 402. Further, a gate insulating film 405 is formed on the emitter region 404 so as to extend over the base region 402 to the RESURF region 401, and a gate electrode 406 is formed on the gate insulating film 405. .

On the other hand, a P ⁺ -type collector region 407 is formed in the RESURF region 401 so as to be separated from the base region 402. A P-type semiconductor layer 410 electrically connected to the base region 402 is formed on the surface layer portion in the RESURF region 401 so as to be separated from the collector region 407. Further, an interlayer film 414 is formed on the semiconductor substrate 400 via a field insulating film 412 formed on the surface of the RESURF region 401.

  Further, a collector electrode 409 that is electrically connected to the collector region 407 is formed on the semiconductor substrate 400, while it is electrically connected to both the contact region 403 and the emitter region 404 on the semiconductor substrate 400. An emitter electrode 415 is formed.

  In the semiconductor device according to the first conventional example, when a positive voltage is applied to the gate electrode 406, a channel is formed in the base region 402, and the emitter region 404 and the RESURF region 401 are conducted. A positive bias is applied between the emitter electrode 415 and the collector electrode 409, the potential of the collector region 407 becomes larger than the potential of the resurf region 401, and the potential difference between the potential of the collector region 407 and the potential of the resurf region 401 is about 0.6V. Then, holes are injected from the collector region 407 into the RESURF region 401, and a collector current flows from the collector electrode 409 to the emitter electrode 415.

  At this time, in the semiconductor device according to the first conventional example, since the minority carriers are injected into the RESURF region 401, conductivity modulation occurs as in the case of a general bipolar transistor. Therefore, compared with a unipolar MOSFET. Thus, the conduction resistance during the IGBT operation can be lowered.

  For this reason, since the conduction loss at the time of high output can be reduced, the power consumption can be reduced as compared with a MOSFET having a chip size equivalent to the chip size of the IGBT.

  Further, as a semiconductor device according to a second conventional example, a lateral IGBT having both a MOSFET operation and an IGBT operation will be described with reference to FIGS. 9 to 11 (see, for example, Patent Document 1). FIG. 9 is a plan view showing the structure of the semiconductor device according to the second conventional example. FIG. 10 is a cross-sectional view showing the structure of the semiconductor device according to the second conventional example, specifically, a cross-sectional view taken along line XX shown in FIG. On the other hand, FIG. 11 is a cross-sectional view showing the structure of the semiconductor device according to the second conventional example, specifically, a cross-sectional view taken along the line XI-XI shown in FIG.

As shown in FIGS. 10 and 11, an N-type RESURF region 501 and a P-type base region 502 are formed on the surface of the P ⁻ -type semiconductor substrate 500.

A P ⁺ -type contact region 503 and an N ⁺ -type emitter region 504 are formed in the base region 502. A gate insulating film 505 is formed on the emitter region 504 so as to extend over the base region 502 to the RESURF region 501, and a gate electrode 506 is formed on the gate insulating film 505. .

On the other hand, a P ⁺ -type collector region 507 (particularly, see FIG. 10) is formed in the RESURF region 501 so as to be separated from the base region 502, while the RESURF region 501 is electrically connected to the collector region 507. An N ⁺ -type drain region 508 to be connected (particularly, see FIG. 11) is formed so as to be separated from the base region 502. Here, the collector region 507 and the drain region 508 are formed so as to be alternately arranged in a direction perpendicular to the direction from the collector region 507 to the emitter region 504, as shown in FIG. A P-type semiconductor layer 510 that is electrically connected to the base region 502 is formed on the surface layer portion in the RESURF region 501 so as to be separated from the collector region 507. An interlayer film 514 is formed on the semiconductor substrate 500 via a field insulating film 512 formed on the surface of the RESURF region 501.

  A collector / drain electrode 509 that is electrically connected to both the collector region 507 and the drain region 508 is formed on the semiconductor substrate 500, while the contact region 503 and the emitter region 504 are formed on the semiconductor substrate 500. An emitter / source electrode 515 that is electrically connected to both is formed.

  Thus, in the semiconductor device according to the second conventional example, the drain region 508 is formed in the RESURF region 501, whereas in the semiconductor device according to the first conventional example, as shown in FIG. Does not have an area.

  In the semiconductor device according to the second conventional example, when a positive bias is applied between the collector / drain electrode 509 and the emitter / source electrode 515 and a positive voltage is applied to the gate electrode 506, the emitter / source electrode 515 is discharged from the drain region 508. An electronic current flows through the MOSFET to perform MOSFET operation.

  On the other hand, when the electron current flowing through the emitter / source electrode 515 increases to some extent, and the potential difference between the potential of the collector region 507 and the potential of the portion surrounding the collector region 507 in the RESURF region 501 reaches about 0.6V, Holes are injected from the collector region 507 into the RESURF region 501, and the MOSFET operation is shifted to the IGBT operation.

Thus, in the semiconductor device according to the second conventional example, the MOSFET operation is performed when the collector current flowing through the element is relatively small, while the IGBT operation is performed when the collector current flowing through the element is increased to some extent. That is, a semiconductor device that performs a MOSFET operation or an IGBT operation according to the amount of collector current flowing through the element can be realized.
Japanese Patent Application No. 2005-305335

  However, the IGBT cited as the semiconductor device according to the first and second conventional examples has the following problems.

  As described above, since conductivity modulation occurs in the IGBT, the conduction loss can be reduced during the IGBT operation (that is, at the time of high voltage), so that the MOSFET has a chip size equivalent to the chip size of the IGBT. Compared with the power consumption can be reduced. Further, an IGBT capable of operating as a MOSFET at a low voltage has been proposed.

  However, since the IGBT uses minority carriers, it takes time to pull out the minority carriers remaining in the RESURF region at the turn-off time when the conductive state is switched to the cut-off state. Therefore, the switching speed of the IGBT is slower than the switching speed of the MOSFET, and the IGBT has a problem that the switching loss is large and the switching characteristics are deteriorated.

  In order to cope with this problem, for example, a lifetime killing technique is applied as a method for improving the switching characteristics, but it is not the best solution because it involves a cost increase and deterioration of characteristics. .

  In view of the above, the first object of the present invention is to reduce the switching loss by efficiently extracting minority carriers remaining in the RESURF region at the turn-off time in the IGBT. Therefore, a second object is to reduce conduction loss during MOSFET operation.

  In order to achieve the first object, a first semiconductor device according to the present invention includes a second conductivity type resurf region formed on a surface of a first conductivity type semiconductor substrate, and a RESURF on the surface of the semiconductor substrate. A first conductivity type base region formed adjacent to the region, a second conductivity type emitter region formed in the base region, and extending from the emitter region to the RESURF region on the base region A first gate insulating film formed; a first gate electrode formed on the first gate insulating film; a collector region of a first conductivity type formed in the RESURF region so as to be separated from the base region; A collector electrode formed on the semiconductor substrate and electrically connected to the collector region; a first conductive type electrically connected to the base region and formed on the surface layer portion in the RESURF region so as to be separated from the collector region; the top A conductor layer; a second gate insulating film formed on the RESURF region so as to extend from the collector region to the top semiconductor layer; a second gate electrode formed on the second gate insulating film; and a semiconductor substrate And a base region, an emitter region, and an emitter electrode electrically connected to the second gate electrode.

  According to the first semiconductor device of the present invention, in the IGBT, minority carriers remaining in the resurf region can be extracted from the top semiconductor layer formed in the surface layer portion in the resurf region at the time of turn-off in the IGBT operation. In addition, minority carriers can also be extracted from the collector region through the MOSFET having the first conductivity type channel formed by utilizing a part of the collector region. Therefore, the fall time (tf) can be shortened, and the switching loss can be reduced, so that the switching characteristics can be improved.

  The first semiconductor device of the present invention may further include a buried semiconductor layer of a first conductivity type formed in the RESURF region so as to be in contact with the top semiconductor layer and electrically connected to the base region. preferable.

  In this case, since the buried semiconductor layer is further formed in the RESURF region, minority carriers remaining in the RESURF region are efficiently removed from the buried semiconductor layer in addition to the top semiconductor layer at the turn-off in the IGBT operation. Can be pulled out well. In addition, as described above, minority carriers can also be extracted from the collector region through the MOSFET having the first conductivity type channel formed using a part of the collector region.

  Further, in this way, the embedded semiconductor layer is formed in the RESURF region at a position deeper than the formation position of the top semiconductor layer. Therefore, a depletion layer easily spreads in the RESURF region during reverse bias, so that the impurity concentration contained in the RESURF region can be increased while maintaining a high breakdown voltage. It is possible to shorten the lifetime.

  As described above, the embedded semiconductor layer formed so as to be electrically connected to the base region and in contact with the top semiconductor layer is further provided in the RESURF region, thereby further reducing the fall time (tf). Therefore, the switching loss can be further reduced, so that the switching characteristics can be further improved.

  In order to achieve the first and second objects, a second semiconductor device of the present invention includes a second conductivity type resurf region formed on a surface of a first conductivity type semiconductor substrate, and a surface of the semiconductor substrate. A first conductivity type base region formed adjacent to the RESURF region, a second conductivity type emitter region formed in the base region, and extending from the emitter region to the RESURF region on the base region A first gate insulating film formed in such a manner; a first gate electrode formed on the first gate insulating film; and a collector of a first conductivity type formed in the RESURF region so as to be separated from the base region. A drain region of a second conductivity type formed in the RESURF region so as to be separated from the base region, and a collector / drain electrode formed on the semiconductor substrate and electrically connected to the collector region and the drain region A top conductive semiconductor layer of a first conductivity type formed on the surface layer portion in the RESURF region so as to be separated from the collector region and electrically connected to the base region; on the RESURF region, on the top semiconductor layer from the collector region; A second gate insulating film formed to extend to the second gate electrode, a second gate electrode formed on the second gate insulating film, a base region, an emitter region, and a second gate electrode formed on the semiconductor substrate And an emitter / source electrode electrically connected to each other.

According to the second semiconductor device of the present invention, even in an IGBT capable of MOSFET operation,
Similar to the first semiconductor device of the present invention described above, minority carriers can also be extracted from the collector region through the MOSFET having the first conductivity type channel formed using a part of the collector region. Therefore, the fall time (tf) can be shortened, and the switching loss can be reduced, so that the switching characteristics can be improved.

  Furthermore, according to the second semiconductor device of the present invention, since the top semiconductor layer is formed in the resurf region in the IGBT capable of operating as a MOSFET, the depletion layer easily expands in the resurf region at the time of reverse bias. . As a result, the impurity concentration contained in the RESURF region can be increased while maintaining a high breakdown voltage, so that the conduction resistance during MOSFET operation can be lowered. For this reason, since the conduction loss can be reduced during MOSFET operation, the amount of collector (drain) current that flows during MOSFET operation can be increased.

  Further, according to the second semiconductor device of the present invention, in the IGBT capable of operating the MOSFET, the electron is operated during the MOSFET operation through the MOSFET having the first conductivity type channel formed using a part of the collector region. Since both current and hole current flow, the current capability can be increased. For this reason, it is possible to further increase the amount of collector (drain) current that flows during MOSFET operation.

  In the second semiconductor device of the present invention, the plurality of collector regions and the plurality of drain regions are arranged so that the collector regions and the drain regions are alternately arranged in a direction perpendicular to the direction from the collector region to the emitter region. It is preferable that a region is formed.

  In this case, the collector region and the drain region are formed in the RESURF region so as to be alternately arranged in a direction perpendicular to the direction from the collector region to the emitter region. The length in the direction (that is, the direction in which the collector region and the drain region are arranged) can be shortened. Therefore, the collector voltage when switching from the MOSFET operation to the IGBT operation (that is, when the potential difference between the potential of the collector region and the potential of the portion surrounding the collector region in the RESURF region reaches about 0.6 V due to the voltage drop) The collector voltage (for example, about 1 V) can be easily increased. For this reason, the range of the collector voltage in which MOSFET operation with high-speed switching performance is possible is expanded (that is, the MOSFET operation with high-speed switching performance is designed to reach a collector voltage larger than about 1 V, for example), etc. Since a more practical design is possible around the voltage at which the MOSFET operation is switched to the IGBT operation, for example, the balance between the MOSFET operation having excellent switching characteristics and the IGBT operation having a low conduction resistance can be freely designed. It is possible.

  In the second semiconductor device of the present invention, the RESURF region further includes a first conductivity type embedded semiconductor layer formed in contact with the top semiconductor layer and electrically connected to the base region. Is preferred.

  In this manner, the buried semiconductor layer formed so as to be electrically connected to the base region and to be in contact with the top semiconductor layer also in the IGBT capable of operating as a MOSFET, as in the first semiconductor device of the present invention described above. Is further provided in the RESURF region, so that the fall time (tf) can be further shortened, so that the switching loss can be further reduced, and the switching characteristics can be further improved. Can do.

  Further, in this way, in the IGBT capable of operating as a MOSFET, the buried semiconductor layer is formed in the RESURF region at a position deeper than the formation position of the top semiconductor layer. Therefore, the depletion layer is more easily spread in the resurf region at the time of reverse bias, so that the impurity concentration contained in the resurf region can be further increased while maintaining a high breakdown voltage. The conduction resistance can be further reduced. For this reason, since the conduction loss can be further reduced during the MOSFET operation, the amount of collector (drain) current flowing during the MOSFET operation can be further increased.

  In the second semiconductor device of the present invention, it is preferable that a plurality of embedded semiconductor layers are formed so that each is arranged in a direction perpendicular to the direction from the collector region to the emitter region.

  In the second semiconductor device of the present invention, a plurality of top semiconductor layers are formed so that each is adjacent to the collector region in a direction perpendicular to the direction from the collector region to the emitter region. Is preferred.

  In this case, since each of the plurality of top semiconductor layers is formed in the RESURF region so as to correspond to each of the plurality of collector regions, the first semiconductor layer formed using a part of the collector region is formed. Since the path of the drain-source current is secured in the surface layer portion in the RESURF region without reducing the current capability of the MOSFET having the conductivity type channel, the conduction resistance during the MOSFET operation can be further reduced.

  In the first or second semiconductor device of the present invention, a second collector region is further formed at the peripheral portion of the collector region so as to be in contact with the collector region, and the first conductivity included in the second collector region. The type impurity concentration is lower than the concentration of the first conductivity type impurity contained in the collector region, and the second gate insulating film is formed from the second collector region to the top semiconductor layer. Is preferred.

  In this way, the electric field applied to the second gate electrode can be relaxed, so that the second gate insulating film can be thinned. Therefore, the threshold voltage of the MOSFET having the first conductivity type channel formed using a part of the collector region can be lowered, so that the MOSFET having the first conductivity type channel can be conducted with a smaller collector voltage. Can do.

  In the first or second semiconductor device of the present invention, the second gate electrode is preferably made of a polycrystalline P-type semiconductor.

  In this case, since the work function difference between the work function of the second gate electrode and the work function of the RESURF region can be reduced, the first conductivity type channel formed using a part of the collector region is provided. Since the threshold voltage of the MOSFET can be lowered, the MOSFET having the first conductivity type channel with a smaller collector voltage compared to the case where an N-type semiconductor polycrystal is used as the material constituting the second gate electrode. Can be conducted.

  According to the semiconductor device of the present invention, since the minority carriers remaining in the RESURF region can be efficiently extracted at the time of turn-off, the switching characteristics can be improved.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention, specifically, a cross-sectional view taken along the line II-II shown in FIG. On the other hand, FIG. 3 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. Specifically, FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. In FIG. 1, illustration of some components is omitted.

As shown in FIGS. 2 and 3, for example, on the surface of the P ⁻ type semiconductor substrate 100 having a concentration of 1 × 10 ¹⁴ / cm ³ , for example, the concentration is 1 × 10 ¹⁶ / cm ³ and the depth is 7 μm. An N-type RESURF region 101 is formed. Further, on the surface of the semiconductor substrate 100, for example, a P-type base region 102 having a concentration of 1 × 10 ¹⁷ / cm ³ is formed adjacent to the RESURF region 101.

The base region 102, for example, concentration and P ⁺ -type contact region 103 of 1 × 10 ¹⁹ / cm ^3, for example, concentration and the N ⁺ -type emitter region 104 of 1 × 10 ²⁰ / cm ³ is formed. A gate insulating film 105 is formed on the emitter region 104 so as to extend over the base region 102 to the RESURF region 101, and a gate electrode 106 is formed on the gate insulating film 105.

On the other hand, in the RESURF region 101, for example, a P ⁺ -type collector region 107 (see FIG. 2 in particular) having a concentration of 1 × 10 ¹⁹ / cm ³ is formed so as to be separated from the base region 102, while the RESURF region An N ⁺ -type drain region 108 (see FIG. 3 in particular) having a concentration of 1 × 10 ²⁰ / cm ³ , for example, is formed so as to be separated from the base region 102. Has been. Here, as shown in FIG. 1, the collector region 107 and the drain region 108 are formed so as to be alternately arranged in a direction perpendicular to the direction from the collector region 107 to the emitter region 104.

As shown in FIGS. 2 and 3, the surface layer portion in the RESURF region 101 is electrically connected to the base region 102. For example, a P-type top semiconductor layer 110 having a concentration of 1 × 10 ¹⁶ / cm ³ is connected to the collector. It is formed so as to be separated from the region 107. A field insulating film (second gate insulating film) 112 is formed on the RESURF region 101 so as to extend from the collector region 107 to the top semiconductor layer 110. On the field insulating film 112, P ⁺ A second gate electrode 113 made of a polycrystal of a type semiconductor is formed. An interlayer film 114 is formed on the semiconductor substrate 100 via a field insulating film 112 formed on the surface of the RESURF region 101.

  A collector / drain electrode 109 electrically connected to both the collector region 107 and the drain region 108 is formed on the semiconductor substrate 100 via the interlayer film 114, while the interlayer film is formed on the semiconductor substrate 100. An emitter / source electrode 115 that is electrically connected to all of the contact region 103, the emitter region 104, and the second gate electrode 113 is formed via 114.

  Thus, in the semiconductor device according to the present embodiment, the field insulating film 112 is formed so as to extend from the collector region 107 to the top semiconductor layer 110, and further, on the field insulating film 112, A two-gate electrode 113 is formed. On the other hand, the semiconductor device according to the first and second conventional examples does not include the second gate electrode formed on the field insulating films 412 and 512 as shown in FIGS.

  In the semiconductor device of the present invention, when a positive bias is applied between the collector / drain electrode 109 and the emitter / source electrode 115 and a positive voltage is applied to the gate electrode 106, an electron current is generated from the drain region 108 to the emitter / source electrode 115. Flow, perform MOSFET operation.

  On the other hand, when the current flowing through the emitter / source electrode 115 increases to some extent and the potential difference between the potential of the collector region 107 and the potential of the portion surrounding the collector region 107 in the RESURF region 101 reaches about 0.6 V, Holes are injected into the RESURF region 101, and the MOSFET operation is shifted to the IGBT operation.

  According to the semiconductor device according to the present embodiment, the P-channel MOSFET formed using a part of the collector region 107 becomes conductive during the operation of the semiconductor device. As a result, using the path from the collector / drain electrode 109 to the collector region 107, the P channel, the top semiconductor layer 110, the base region 102, and the contact region 103, at the turn-off in the IGBT operation, the collector region 107 to the RESURF region 101. The holes remaining in can be extracted. In addition, holes remaining in the RESURF region 101 can also be extracted from the top semiconductor layer 110. For this reason, since the fall time (tf) can be shortened and the switching loss can be reduced, the switching characteristics can be improved.

  Further, according to the semiconductor device according to the present embodiment, the depletion layer expands in the top semiconductor layer 110 after extracting the holes remaining in the RESURF region 101 by increasing the collector potential at the turn-off time, Since the hole current flowing from the collector / drain electrode 109 through the P-channel MOSFET to the path can be blocked, the switching characteristics can be further improved.

  Furthermore, according to the semiconductor device according to the present embodiment, the top semiconductor layer 110 that is electrically connected to the base region 102 is formed in the resurf region 101, so that a depletion layer is formed in the resurf region 101 during reverse bias. Becomes easier to spread. Therefore, the impurity concentration contained in the RESURF region 101 can be increased while maintaining a high withstand voltage, so that the conduction resistance during the MOSFET operation can be lowered. For this reason, since the conduction loss can be reduced during MOSFET operation, the amount of collector (drain) current that flows during MOSFET operation can be increased.

  Further, according to the semiconductor device according to the present embodiment, when the semiconductor device operates, the P-channel MOSFET formed by using a part of the collector region 107 becomes conductive, so that the MOSFET is operated using the above path. In addition, since both the electron current and the hole current flow, the current capability can be increased. For this reason, it is possible to further increase the amount of collector (drain) current that flows during MOSFET operation.

  Further, according to the semiconductor device of this embodiment, as shown in FIG. 1, the collector regions 107 and the drain regions 108 are alternately arranged in a direction perpendicular to the direction from the collector region 107 to the emitter region 104. In addition, since it is formed in the RESURF region 101, the length of the collector region 107 in the vertical direction (that is, the direction in which the collector region 107 and the drain region 108 are arranged) can be shortened. Therefore, the collector voltage when switching from the MOSFET operation to the IGBT operation (that is, when the potential difference between the potential of the collector region and the potential of the portion surrounding the collector region in the RESURF region reaches about 0.6 V due to the voltage drop) The collector voltage (for example, about 1 V) can be easily increased. For this reason, the range of the collector voltage in which MOSFET operation with high-speed switching performance is possible is expanded (that is, the MOSFET operation with high-speed switching performance is designed to reach a collector voltage larger than about 1 V, for example), etc. Since a more practical design is possible around the voltage at which the MOSFET operation is switched to the IGBT operation, for example, the balance between the MOSFET operation having excellent switching characteristics and the IGBT operation having a low conduction resistance can be freely designed. It is possible.

Further, according to the semiconductor device of the present embodiment, a P ⁺ -type semiconductor polycrystal is used as the material constituting the second gate electrode 113. In this way, since the work function difference between the work function of the second gate electrode 113 and the work function of the RESURF region 101 can be reduced, the P-channel MOSFET formed using a part of the collector region 107 can be reduced. Since the threshold voltage can be lowered, the P-channel MOSFET can be made to conduct with a smaller collector voltage than in the case where an N ⁺ type semiconductor polycrystal is used as the material constituting the second gate electrode 113. it can.

  In the first embodiment, the case where the top semiconductor layer 110 is formed in the RESURF region 101 has been described as a specific example, but the present invention is not limited to this. For example, in the case where a plurality of semiconductor layers are formed at a position deeper than the formation position of the top semiconductor layer 110 in the RESURF region 101 in addition to the top semiconductor layer 110, the same effect as the present invention can be obtained. Can do. For example, even when each of the plurality of top semiconductor layers is formed in the RESURF region 101 so as to be alternately arranged in a direction perpendicular to the direction from the collector region 107 to the emitter region 104, The same effect as the invention can be obtained.

  In the first embodiment, as shown in FIG. 1, the collector region 107 and the drain region 108 are alternately arranged in a direction perpendicular to the direction from the collector region 107 to the emitter region 104. Although the case where it was formed in the RESURF region 101 has been described as a specific example, the present invention is not limited to this. For example, even when each of a plurality of drain regions (or collector regions) is formed on the surface of a collector region (or drain region) formed in the RESURF region 101 so as to be embedded with a space therebetween, The same effect as the present invention can be obtained.

  As described above, the formation region of the top semiconductor layer 110, the collector region 107, and the drain region 108 formed in the RESURF region 101 is a P-channel MOSFET that uses a part of the collector region 107 during operation of the semiconductor device. Must be positioned so that they are conducting.

  Further, the structure of the semiconductor device according to the present invention is not limited to FIGS. 1 to 3 shown in the first embodiment. The structure of the semiconductor device according to the modification will be described below with reference to FIG. FIG. 4 is a cross-sectional view illustrating the structure of a semiconductor device according to a modification. In FIG. 4, the same components as those of the semiconductor device according to the first embodiment of the present invention are denoted by the same reference numerals.

<Modification>
In the following, the difference between the semiconductor device according to the modification and the semiconductor device according to the first embodiment will be specifically described.

  In the semiconductor device according to the modification, as shown in FIG. 4, the P-type second collector region 207 a having an impurity concentration lower than the impurity concentration contained in the collector region 107 is formed so as to be in contact with the peripheral portion of the collector region 107. Has been.

  In this way, the electric field applied to the second gate electrode 113 can be relaxed, so that the field insulating film 212 is made thinner than the field insulating film (see FIG. 1: 112). can do. Therefore, the threshold voltage of the P-channel MOSFET formed using a part of the collector region 107 can be lowered, so that the P-channel MOSFET formed using a part of the collector region 107 with a smaller collector voltage. Can be conducted.

(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. FIG. 5 is a plan view showing the structure of the semiconductor device according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention, specifically, a cross-sectional view taken along the line VI-VI shown in FIG. On the other hand, FIG. 7 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention, specifically, a cross-sectional view taken along the line VII-VII shown in FIG. In FIG. 5, illustration of some components is omitted. 5 to 7, the same reference numerals are given to the same components as those of the semiconductor device according to the first embodiment of the present invention described above. Therefore, in this embodiment, the same description as the semiconductor device according to the second embodiment of the present invention is not repeated.

  Hereinafter, the semiconductor device according to the present embodiment will be specifically described on differences from the semiconductor device according to the first embodiment described above.

In the first embodiment described above, the RESURF region 101 (see FIGS. 2 and 3 described above) having the P-type top semiconductor layer 110 having a concentration of, for example, 1 × 10 ¹⁶ / cm ³ is formed inside. On the other hand, in the present embodiment, as shown in FIGS. 6 and 7, the P-type top semiconductor layer 310 having a concentration of 1 × 10 ¹⁶ / cm ³ , for example, and the top semiconductor layer 310 are formed inside. The RESURF region 301 having the embedded semiconductor layer 311 is provided.

  Here, as shown in FIG. 6, the embedded semiconductor layer 311 is formed at a position deeper than the formation position of the top semiconductor layer 310, and is electrically connected to the base region 102 at a location not shown. . Further, the top semiconductor layer 310 is electrically connected to the base region 102 through a buried semiconductor layer 311 formed so as to be in contact with the top semiconductor layer 310.

  Further, as shown in FIG. 5, each of the plurality of top semiconductor layers 310 is arranged in the RESURF region 301 so as to be arranged at a desired interval in a direction perpendicular to the direction from the collector region 107 to the emitter region 104. The embedded semiconductor layer 311 is formed in contact with each of the plurality of top semiconductor layers 310. Here, each of the plurality of top semiconductor layers 310 is formed so as to correspond to each of the plurality of collector regions 107, and more specifically, the interval at which each of the plurality of top semiconductor layers 310 is arranged is a drain region. It is formed to be equal to the width W of 108.

  In the semiconductor device according to the present embodiment, since the embedded semiconductor layer 311 is formed in the resurf region 301, minority carriers remaining in the resurf region 301 are removed from the top semiconductor layer 310 at the time of turn-off in the IGBT operation. It can be pulled out efficiently. Furthermore, as in the first embodiment described above, not only can the minority carriers remaining in the RESURF region 301 be extracted from the top semiconductor layer 310, but in addition, a part of the collector region 107 is used. Minority carriers can also be extracted from the collector region 107 through the P-channel MOSFET formed in this manner.

  Furthermore, according to the semiconductor device of this embodiment, the buried semiconductor layer 311 is formed in the RESURF region 301 at a position deeper than the formation position of the top semiconductor layer 310. Therefore, compared to the first embodiment described above, a depletion layer is more easily expanded in the resurf region 301 at the time of reverse bias, and therefore included in the resurf region (see FIGS. 2 and 3: 101 described above). Since the RESURF region 301 having an impurity concentration higher than the impurity concentration can be realized, the lifetime of holes in the RESURF region 301 can be shortened.

  As described above, the buried semiconductor layer 311 formed so as to be electrically connected to the base region 102 and to be in contact with the top semiconductor layer 310 is further provided in the RESURF region 301, thereby reducing the fall time (tf). Since the switching loss can be further reduced, the switching loss can be further reduced, so that the switching characteristics can be further improved.

  In addition, according to the semiconductor device of this embodiment, at the time of turn-off, after the holes remaining in the RESURF region 301 are extracted, the depletion layer expands in the top semiconductor layer 310 or the embedded semiconductor layer 311, thereby collecting the collector The hole current flowing from the / drain electrode 109 to the collector region 107, the P channel, the top semiconductor layer 310, the buried semiconductor layer 311, the base region 102, and the contact region 103 can be blocked, so that the switching characteristics are improved. Can be achieved. Furthermore, when the hole current is blocked, the time until the hole current is blocked can be easily set according to the size of the top semiconductor layer 310.

  Furthermore, according to the semiconductor device of this embodiment, the buried semiconductor layer 311 is formed in the RESURF region 301 at a position deeper than the formation position of the top semiconductor layer 310. Therefore, as described above, a depletion layer is more likely to expand in the resurf region 301 at the time of reverse bias, so that the concentration of impurities contained in the resurf region 301 can be further increased while maintaining a high breakdown voltage. Therefore, the conduction resistance during MOSFET operation can be further reduced. For this reason, since the conduction loss can be further reduced during the MOSFET operation, the amount of collector (drain) current flowing during the MOSFET operation can be further increased.

  Further, according to the semiconductor device according to the present embodiment, as shown in FIG. 5, each of the plurality of top semiconductor layers 310 is in a direction perpendicular to the direction from the collector region 107 toward the emitter region 104 and a plurality of top semiconductor layers 310. In order to correspond to each of the collector regions 107, it is formed so as to be arranged at a desired interval (see W in FIG. 5). Therefore, the drain-source current path is ensured in the surface layer portion in the resurf region 301 without degrading the current capability of the P-channel MOSFET formed by using a part of the collector region 107, so that the MOSFET operation The conduction resistance at the time can be further reduced.

  In the second embodiment, as shown in FIGS. 6 and 7, the case where one buried semiconductor layer 311 is formed in the RESURF region 301 has been described as a specific example. However, the present invention is not limited to this. It is not limited. For example, when a buried semiconductor layer in which a plurality of semiconductor layers are stacked is formed in the RESURF region 301, or each of the plurality of buried semiconductor layers is directed toward the emitter region 104 from the collector region 107. Even in the case of being formed in the RESURF region 301 so as to be alternately arranged in the vertical direction, the same effect as the present invention can be obtained.

  As described above, the top semiconductor layer 310, the buried semiconductor layer 311, the collector region 107, and the drain region 108 formed in the RESURF region 301 use a part of the collector region 107 during the operation of the semiconductor device. Thus, the P-channel MOSFET is positioned to be conductive.

  As described above, in the first and second embodiments, in the semiconductor device according to the present invention, the modification of the semiconductor layer formed in the RESURF regions 101 and 301 has been introduced. It goes without saying that modifications within the scope of the gist are included.

  In the first and second embodiments, the case where the drain region 108 is formed in the RESURF regions 101 and 301 has been described in order to achieve the first and second objects of the present invention. In order to achieve the first object of the present invention, the drain region 108 does not need to be formed in the RESURF regions 101 and 301. By including a field insulating film 112 formed so as to extend from the collector region 107 to the top semiconductor layer 110, and a second gate electrode 113 formed on the field insulating film 112, the first object of the present invention It goes without saying that can be achieved.

  In the present invention, since minority carriers remaining in the RESURF region can be efficiently extracted at the time of turn-off, the switching characteristics can be improved, so that the semiconductor device such as a high breakdown voltage lateral insulated gate bipolar transistor can be used. Useful.

1 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing shown about the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing shown about the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing shown about the structure of the semiconductor device which concerns on the modification of this invention. It is a top view shown about the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing shown about the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing shown about the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing shown about the structure of the semiconductor device which concerns on a 1st prior art example. It is a top view shown about the structure of the semiconductor device which concerns on a 2nd prior art example. It is sectional drawing shown about the structure of the semiconductor device which concerns on a 2nd prior art example. It is sectional drawing shown about the structure of the semiconductor device which concerns on a 2nd prior art example.

Explanation of symbols

100 P ⁻ type semiconductor substrate 101 N type RESURF region 102 P type base region 103 P ⁺ type contact region 104 N ⁺ type emitter region 105 first gate insulating film 106 first gate electrode 107 P ⁺ type collector region 108 N ⁺ type drain Region 109 Collector / drain electrode 110 P-type top semiconductor layer 112 Field insulating film (second gate insulating film)
113 Second gate electrode 114 Interlayer film 115 Emitter / source electrode 207a P-type second collector region 212 Field insulating film 301 N-type RESURF region 310 P-type top semiconductor layer 311 P-type buried semiconductor layer 400 P ^- type semiconductor substrate 401 N-type RESURF region 402 P type base region 403 P ⁺ type contact region 404 N ⁺ type emitter region 405 Gate insulating film 406 Gate electrode 407 P ⁺ type collector region 409 Collector electrode 410 P type semiconductor layer 412 Field insulating film 414 Interlayer film 415 Emitter electrode 500 P ⁻ type semiconductor substrate 501 N type RESURF region 502 P type base region 503 P ⁺ type contact region 504 N ⁺ type emitter region 505 gate insulating film 506 gate electrode 507 P ⁺ type collector region 508 N ⁺ type drain region 509 Collector / drain electrode 510 P-type semiconductor layer 512 Field insulating film 514 Interlayer film 515 Emitter / source electrode

Claims (9)

A second conductivity type RESURF region formed on the surface of the first conductivity type semiconductor substrate;
A base region of a first conductivity type formed on the surface of the semiconductor substrate so as to be adjacent to the RESURF region;
An emitter region of a second conductivity type formed in the base region;
A first gate insulating film formed on the base region so as to extend from the emitter region to the RESURF region;
A first gate electrode formed on the first gate insulating film;
A collector region of a first conductivity type formed in the RESURF region so as to be separated from the base region;
A collector electrode formed on the semiconductor substrate and electrically connected to the collector region;
A first conductive type top semiconductor layer formed in a surface layer portion in the RESURF region so as to be separated from the collector region and electrically connected to the base region;
A second gate insulating film formed on the RESURF region so as to extend from the collector region to the top semiconductor layer;
A second gate electrode formed on the second gate insulating film;
A semiconductor device comprising: an emitter electrode formed on the semiconductor substrate and electrically connected to the base region, the emitter region, and the second gate electrode.   2. The semiconductor device according to claim 1, further comprising a buried semiconductor layer of a first conductivity type formed in the RESURF region so as to be in contact with the top semiconductor layer and electrically connected to the base region. Semiconductor device. A second conductivity type RESURF region formed on the surface of the first conductivity type semiconductor substrate;
A base region of a first conductivity type formed on the surface of the semiconductor substrate so as to be adjacent to the RESURF region;
An emitter region of a second conductivity type formed in the base region;
A first gate insulating film formed on the base region so as to extend from the emitter region to the RESURF region;
A first gate electrode formed on the first gate insulating film;
A collector region of a first conductivity type formed in the RESURF region so as to be separated from the base region;
A drain region of a second conductivity type formed in the RESURF region so as to be separated from the base region;
A collector / drain electrode formed on the semiconductor substrate and electrically connected to the collector region and the drain region;
A top conductive semiconductor layer of a first conductivity type formed in a surface layer portion in the RESURF region so as to be separated from the collector region and electrically connected to the base region;
A second gate insulating film formed on the RESURF region so as to extend from the collector region to the top semiconductor layer;
A second gate electrode formed on the second gate insulating film;
A semiconductor device comprising: an emitter / source electrode formed on the semiconductor substrate and electrically connected to the base region, the emitter region, and the second gate electrode.   A plurality of collector regions and a plurality of drain regions are formed such that the collector regions and the drain regions are alternately arranged in a direction perpendicular to the direction from the collector region to the emitter region. The semiconductor device according to claim 3.   5. The semiconductor device according to claim 3, further comprising a buried semiconductor layer of a first conductivity type formed in the RESURF region so as to be in contact with the top semiconductor layer and electrically connected to the base region. A semiconductor device according to 1.   6. The semiconductor device according to claim 5, wherein a plurality of the embedded semiconductor layers are formed so that each of them is arranged in a direction perpendicular to a direction from the collector region to the emitter region.   The plurality of top semiconductor layers are formed so as to be adjacent to the collector region in a direction perpendicular to the direction from the collector region to the emitter region, respectively. The semiconductor device according to any one of the above. A second collector region is further formed on the periphery of the collector region so as to be in contact with the collector region,
A concentration of the first conductivity type impurity contained in the second collector region is lower than a concentration of the first conductivity type impurity contained in the collector region;
The semiconductor device according to claim 1, wherein the second gate insulating film is formed from the second collector region to the top semiconductor layer.   The semiconductor device according to claim 1, wherein the second gate electrode is made of a polycrystal of a P-type semiconductor.

Images