JP2007242093A - Semiconductor integrated circuit and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of speedily returning from a power down mode while attaining low power consumption. <P>SOLUTION: The semiconductor integrated circuit comprises: a boosting power supply circuit 25 which supplies at least either a first predetermined voltage generated by boosting a predetermined voltage or a second predetermined voltage lower than the first predetermined voltage; two or more circuit blocks; and a voltage boosting control circuit which controls the boosting power supply circuit so as to supply the first predetermined voltage to the two or more circuit blocks in a first operation mode, supplying the second predetermined voltage to a predetermined circuit block among the two or more circuit blocks in a second operation mode, and controlling the boosting power supply circuit 25 not to supply voltage to the other circuit blocks. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generally relates to semiconductor integrated circuits and electronic devices, and particularly relates to semiconductor integrated circuits and electronic devices having a power-down mode (low power consumption mode).

  Conventionally, an SRAM is used as a work memory in a portable device such as a cellular phone. However, as the memory capacity required for portable devices increases, recently, a DRAM having dynamic memory cells or a pseudo SRAM that provides an interface equivalent to an SRAM while being a DRAM has been adopted as a work memory. Since the DRAM memory cell is smaller than the SRAM memory cell, the storage capacity of the work memory can be increased at the same cost.

  A memory mounted on a portable device is required to have low power consumption in order to increase the battery usage time. In order to reduce power consumption, when the portable device is not operating, the operation mode of the DRAM and pseudo SRAM is shifted to a power-down mode that does not require holding of written data. In power-down mode, operating current and leakage current are reduced to reduce current consumption by various methods such as stopping refresh and shutting off the internal power supply from the external power supply, or stopping the internally generated power supply circuit. .

  FIG. 1 is a diagram showing a conventional example of a semiconductor memory device. The configuration of FIG. 1 includes a boost power supply circuit 10 and a memory core 11.

  In a semiconductor memory device, it is necessary to supply a boosted potential higher than HIGH to a word line in order to store HIGH in a memory cell quickly and reliably. In order to realize this, the power supply voltage is boosted from the external power supply voltage by the boost power supply circuit 10 to generate a power supply having a higher potential.

  A boost power supply circuit used in a semiconductor memory device is generally a charge pump circuit, which couples a signal output oscillated by an oscillation circuit to one end (first end) of a capacitor, and connects the other end (second end) of the capacitor to a diode. It is configured by connecting to the anode side of an NMOS diode or the like. With the voltage at the first end of the capacitor corresponding to the first state of the oscillation signal lowered, the capacitor is charged from the second end side, and the potential at the second end of the capacitor is set to V. Next, the voltage at the first end of the capacitor is increased in response to the second state of the oscillation signal, thereby boosting the voltage at the second end of the capacitor to V or higher. Due to the voltage rise at the second end due to this pumping operation, the charge of the capacitor is supplied to the output side via the diode.

  If such a pair of capacitor and diode is a single-stage circuit, a plurality of stages are prepared, and the output of the previous stage (cathode side of the diode) is connected to the input of the subsequent stage (second end of the capacitor). A step-up booster power circuit can be configured. Further, if the number of stages to be driven is variable, the output voltage of the boost power supply circuit can be set to a voltage corresponding to the number of driving stages.

  In the configuration example shown in FIG. 1, the boosting power supply circuit 10 is, for example, a two-stage boosting circuit. In the normal operation state, the boost power supply circuit 10 generates a boosted voltage corresponding to the number of two driving stages and supplies the boosted voltage to the memory core 11. When the semiconductor memory device is not used, a transition is made to a power down mode, which is a low power consumption state, in order to reduce power consumption. The boost power supply circuit 10 receives the “0” state operation mode signal indicating the power down mode, and stops the boost voltage supply.

  In such a configuration, in the power down mode, the boosted voltage is lowered to substantially the ground voltage due to the leakage current of the memory core 11. Since the boosted voltage drops to substantially the ground voltage, there is a problem that it takes time until the boosted voltage is restored by the above pump operation when returning from the power-down mode later.

Patent Document 1 discloses a technique for creating a specific area of an SDRAM in advance as an area that is not in the power down mode. Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique in which an internal power supply circuit provided corresponding to a certain memory bank is turned on and an internal power supply circuit provided corresponding to another bank is turned off. Patent Document 3 shows a conventional example of a power down mode.
Japanese Patent Laid-Open No. 08-63391 Japanese Patent Laid-Open No. 11-297071 Japanese Patent Laid-Open No. 2002-124082

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit and an electronic device that can realize low power consumption and can return from a power-down mode at high speed.

  A semiconductor integrated circuit includes: a boost power supply circuit that supplies at least one of a first predetermined voltage generated by boosting a predetermined power supply and a second predetermined voltage lower than the first predetermined voltage; And the step-up power supply circuit is controlled to supply the first predetermined voltage to the plurality of circuit blocks in the first operation mode, and the plurality of circuit blocks in the second operation mode. And a step-up control circuit for controlling the step-up power supply circuit so that the second predetermined voltage is supplied to the predetermined circuit block and no voltage is supplied to the other circuit blocks.

  An electronic device includes: a CPU; a boost power supply circuit that supplies at least one of a first predetermined voltage generated by boosting a predetermined power supply and a second predetermined voltage lower than the first predetermined voltage; A plurality of circuit blocks, and the booster power supply circuit is controlled to supply the first predetermined voltage to the plurality of circuit blocks in the first operation mode, and the plurality of circuits in the second operation mode. A step-up control circuit that controls the step-up power supply circuit so that the second predetermined voltage is supplied to a predetermined circuit block of the block and no voltage is supplied to the other circuit blocks; A circuit block is designated.

  According to at least one embodiment of the present invention, when there is a circuit block that is desired to be restored quickly, the second predetermined value that is lower than the first prescribed voltage (boosted voltage) is determined for the circuit block that is desired to be restored quickly. Is supplied from the boosting power supply circuit. Since the second predetermined voltage is set lower than the first predetermined voltage, the leakage current in the circuit block is small. In addition, since the second predetermined voltage is applied to the circuit block, the return to the first predetermined voltage is quicker than the case where the voltage is increased from the ground voltage to the first predetermined voltage.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a diagram showing an example of the configuration of the semiconductor memory device according to the present invention. In the following description, a case where the present invention is applied to a semiconductor memory device will be described as a preferred example. However, any circuit that has a power-down mode in a configuration in which a boost voltage is supplied to a plurality of blocks using a boost power source. The present invention can be applied and is not necessarily limited to a semiconductor memory device.

  The semiconductor memory device 20 of FIG. 2 includes a command control circuit 21, an operation control circuit 22, a mode register 23, a boost control circuit 24, a boost power supply circuit 25, an address input circuit 26, an address decoder 27, a data input / output circuit 28, and a memory. A core circuit 29 is included. The memory core circuit 29 is divided for each bank and includes a plurality (four in this example) of memory cores 29-1 to 29-4. The memory core circuit 29 need not be divided for each bank. For example, the memory core circuit 29 may be divided for each row block or a plurality of row blocks.

  The command control circuit 21 receives a chip enable signal / CE, an output enable signal / OE, a write enable signal / WE, and the like as external commands. The command control circuit 21 decodes the received external command and outputs the decoded external command to the operation control circuit 22 as an internal command signal. Commands indicated by the internal command signal include a mode register setting command in addition to a read command and a write command. The command control circuit 21 has a function of rewriting the mode register 23 when the instructed command is a mode register setting command.

  The operation control circuit 22 generates various timing signals for executing the read operation, the write operation, and the refresh operation according to the internal command signal (read command and write command) and the refresh command supplied from the command control circuit 21. To do. These timing signals are supplied to the memory core circuit 29, the data input / output circuit 28, and the like. The generation timing of the timing signal is changed according to the operation specification set in the mode register 23. The operation control circuit 22 has an arbiter (not shown) that determines the priority order of commands when a read command or a write command conflicts with a refresh command generated inside the semiconductor memory device. The refresh command is periodically generated by a refresh timer (not shown).

  The mode register 23 is supplied with a setting signal from the command control circuit 21 when the external command signal to the command control circuit 21 is a mode register setting command. In accordance with this setting signal, a value corresponding to the address signal supplied from the outside via the address input circuit 26 is set in the internal register of the mode register 23. In the mode register 23, for example, a plurality of types of operation specifications for operating the semiconductor memory device 20 are set. In the mode register 23, a memory core that the semiconductor memory device 20 is to be restored at high speed is registered.

  In response to the signal supplied from the operation control circuit 22, the boost control circuit 24 controls the boost power supply circuit 25 so as to generate a boost voltage suitable for the operation mode at that time. In the normal operation mode (when the command control circuit 21 does not output a power-down mode signal), the boost control circuit 24 causes the boost power supply circuit 25 to generate the first predetermined voltage (boost voltage), and the memory core 29- A first predetermined voltage is supplied to all of 1 to 29-4. In the power down mode (when the command control circuit 21 outputs a power down mode signal), the boost control circuit 24 causes the boost power supply circuit 25 to generate a second predetermined voltage lower than the first predetermined voltage, Among the memory cores 29-1 to 29-4, the second predetermined voltage is supplied to the memory core that needs to be restored quickly, and the supply of voltage is stopped to the other memory cores. At this time, the boost control circuit 24 specifies the memory core that is desired to be restored at high speed based on the signal supplied from the mode register 23.

  The address input circuit 26 receives an external address signal via the address terminal, and outputs the received address to the address decoder 27, the mode register 23, and the like. Address decoder 27 decodes the external address signal and outputs the decoded signal to memory core circuit 29.

  The data input / output circuit 28 outputs read data transferred from the memory core circuit 29 via the common data bus to the external data terminal during a read operation. During the write operation, the data input / output circuit 28 receives write data via the external data terminal and transfers the received data signal to the memory core circuit 29 via the common data bus.

  The memory cores 29-1 to 29-4 of the memory core circuit 29 have a memory cell array, a word decoder WD, a sense amplifier SA, and a column decoder CD. The memory cell array includes a plurality of memory cells (dynamic memory cells) including a transfer transistor and a capacitor, a word line connected to the gate of the transfer transistor of each memory cell, and a bit line connected to the data input / output node of the transfer transistor. Have.

  The word decoder WD selects one of the word lines according to the row decode signal among the decode signals from the address decoder 27. For example, the sense amplifier SA amplifies the signal amount of data read from the memory cell via the bit line during a read operation.

  The memory cores 29-1 to 29-4 transmit read data read to the bit line and amplified by the sense amplifier SA to the common data bus, and transmit write data supplied from the common data bus to the bit line. It has a column switch. The column decoder CD outputs a control signal for controlling the column switch according to the column decode signal among the decode signals from the address decoder 27.

  FIG. 3 is a diagram showing the configuration of the first embodiment of the power supply circuit to the memory core. For convenience of explanation, FIG. 3 shows memory cores 29-1 to 29-4 together with the boost power supply circuit 25.

  In FIG. 3, the boosting power supply circuit 25 includes a boosting circuit 31 and switches 32-1 to 32-4. The booster circuit 31 is a two-stage booster power supply circuit and is configured such that the number of stages to be driven is variable. The booster circuit 31 generates a boosted voltage corresponding to the number of drive stages. That is, the boosted voltage at the time of two-stage driving is higher than the boosted voltage at the time of one-stage driving.

  A boosting stage number signal is supplied from the boosting control circuit 24 to the boosting circuit 31. The boosting stage number signal is a 2-bit signal. When “00”, the boosted power supply is stopped, when “01”, one-stage boosting is indicated, and when “10” or “11”, two-stage boosting is indicated. Boosting power supply signals # 0 to # 3 are supplied from the boosting control circuit 24 to the switches 32-1 to 32-4. The switches 32-1 to 32-4 block the boosted voltage if the corresponding boosted power supply signals # 0 to # 3 are in the “0” state indicating supply stop. The boosted voltage output from the boost power supply circuit 25 via the switches 32-1 to 32-4 is supplied to the memory cores 29-1 to 29-4.

  During normal operation, the booster circuit 31 receives a boosting stage number signal of “10” or “11” and operates with two-stage boosting. The switches 32-1 to 32-4 receive the boosted power supply signal in the “1” state, and supply the boosted voltage of the two-stage boost from the booster circuit 31 to the memory cores 29-1 to 29-4.

  At the time of power-down where there is a memory core to be restored at high speed, the booster circuit 31 receives a booster stage number signal of “01” and operates at a single booster. Further, the switch 32-1 corresponding to the memory core 29-1 to be restored at high speed receives the boosted power supply signal in the “1” state, and supplies the boosted voltage of one step booster from the booster circuit 31 to the memory core 29-1. Since the boost voltage of this one-stage boost is set lower than that during the two-stage boost, the leak current in the memory core is small. In addition, since the one-step boosted voltage is applied to the memory core, the return to the two-stage boosted voltage is faster than the case where the ground voltage is boosted to the two-stage boosted voltage and returned.

  Further, the switches 32-2 to 32-4 corresponding to the low power consumption memory cores 29-2 to 29-4 receive the boosted power supply signal in the “0” state, and block the boosted voltage to the memory core. This reduces the leakage current in the memory core and realizes low power consumption.

  At the time of power-down where it is desired to reduce the power consumption of all the memory cores, the booster circuit 31 receives a booster stage number signal of “00” and stops its operation. The switches 32-1 to 32-4 may receive the boosted power supply signal in the “0” state and cut off the supply of the boosted voltage to all the memory cores. However, in this case, since the booster circuit 31 does not supply the boosted voltage, the state of the boosted power supply signal may be “0” or “1”.

  FIG. 4 is a diagram showing the configuration of the second embodiment of the power supply circuit to the memory core. 4, the same components as those in FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.

  In FIG. 4, the boosting power supply circuit 25 includes a boosting circuit 31 and switches 42-1 to 42-3. Unlike the configuration of the first embodiment shown in FIG. 3, the switches 42-1 to 42-3 are connected in series with respect to the boosted voltage. Except for the series connection, the operations of the switches 42-1 to 42-3 are the same as the operations of the switches 32-1 to 32-4.

  In the second embodiment, the fast recovery memory core can be selected only from the side closer to the boost power supply. When the memory core 29-1 is the only memory core that is desired to be restored at high speed, none of the switches 42-1 to 42-3 is in a conductive state.

  As in the case of the first embodiment, a boosted voltage of one step boost is supplied to the memory core that is to be restored quickly. Since the boost voltage of this one-stage boost is set lower than that during the two-stage boost, the leak current in the memory core is small. In addition, since the one-step boosted voltage is applied to the memory core, the return to the two-stage boosted voltage is faster than the case where the ground voltage is boosted to the two-stage boosted voltage and returned. For the low power consumption memory core, the supply of the boosted voltage is cut off. This reduces the leakage current in the memory core and realizes low power consumption.

  FIG. 5 is a diagram showing the configuration of the third embodiment of the power supply circuit to the memory core. In FIG. 5, the boosting power supply circuit 25 includes boosting circuits 31-1 to 31-4. Unlike the configurations of the first and second embodiments, a plurality of booster circuits are provided corresponding to a plurality of memory cores on a one-to-one basis, and no switches are provided. Each of the booster circuits 31-1 to 31-4 operates in the same manner as the booster circuit 31.

  During normal operation, each of the booster circuits 31-1 to 31-4 receives a booster stage number signal of “10” or “11” and operates with a two-stage booster. As a result, the boosted voltage of the two-stage boost is supplied from the booster circuits 31-1 to 31-4 to the memory cores 29-1 to 29-4.

  At the time of power down when there is a memory core to be returned to high speed, the booster circuit 31-1 corresponding to the memory core 29-1 to be returned at high speed receives a boosting stage number signal of “01” and operates at a single boost. As a result, a boosted voltage of one step boost is supplied from the booster circuit 31-1 to the memory core 29-1. Since the boost voltage of this one-stage boost is set lower than that during the two-stage boost, the leak current in the memory core is small. In addition, since the one-step boosted voltage is applied to the memory core, the return to the two-stage boosted voltage is faster than the case where the ground voltage is boosted to the two-stage boosted voltage and returned.

  The booster circuits 31-2 to 32-4 corresponding to the low power consumption memory cores 29-2 to 29-4 receive the boosting stage number signal of “00” and stop the boosted voltage supply operation. This reduces the leakage current in the memory core and realizes low power consumption.

  At power-down when it is desired to reduce the power consumption of all the memory cores, all the booster circuits 31-1 to 32-4 receive the booster stage number signal of “00” and stop operating. Reduces power consumption by reducing leakage current in all memory cores.

  FIG. 6 is a diagram showing the configuration of the fourth embodiment of the power supply circuit to the memory core. 6, the boosting power supply circuit 25 includes a boosting circuit 51 and switches 52-1, 52-2,. For convenience of illustration, portions corresponding to the memory core 29-3 and subsequent portions are omitted.

  In the first to third embodiments, the booster circuit is a two-stage booster power supply circuit, and is configured such that the number of stages to be driven is variable. In normal operation, a two-stage boosted voltage is supplied to each memory core, and in a power-down mode, a single boosted voltage is supplied to the fast recovery memory core. On the other hand, in the fourth embodiment, the booster circuit 51 is, for example, a two-stage fixed booster circuit and can only switch whether or not to supply a two-stage boosted voltage. Instead, a boosted voltage and an external voltage are supplied to the switches 52-1, 52-2,..., And the external voltage can be selected as necessary. Specifically, the switches 52-1, 52-2,... Receive the corresponding boost power supply clamp signals # 0, # 1,. If so, connect the switch output to an external voltage. By this clamping to the external power supply, the external power supply voltage is supplied to the fast recovery memory core as a second predetermined voltage.

  During normal operation, the booster circuit 51 receives an “1” state operation mode signal from the booster control circuit 24 and outputs a boosted voltage. The switches 52-1, 52-2,... Receive the boosted power supply signal in the “1” state and the boosted power supply clamp signal in the “0” state from the boost control circuit 24, and store the boosted voltage from the booster circuit 51 in the memory. Supply to the core.

  At the time of power-down where there is a memory core to be restored at high speed, the booster circuit 51 receives an operation mode signal of “0” from the booster control circuit 24 and stops operating. Further, the switch 52-1 corresponding to the memory core to be restored at high speed receives the "0" state boost power supply signal and the "1" state boost power supply clamp signal from the boost control circuit 24, and clamps the switch output to the external power source. To do. Since this external power supply voltage is lower than the boosted voltage during normal operation, the leakage current in the memory core is reduced accordingly. In addition, since the external power supply voltage is applied to the memory core, the return to the boosted voltage is faster than the case of returning from the ground voltage to the boosted voltage.

  The switch 52-2 corresponding to the low power consumption memory core receives the boosted power supply signal in the “0” state and the boosted power supply clamp signal in the “0” state from the boost control circuit 24, and cuts off the boosted voltage to the memory core. At the same time, the external power supply is not clamped. This reduces the leakage current in the memory core and realizes low power consumption.

  At power down when it is desired to reduce the power consumption of all the memory cores, the booster circuit 51 receives an operation mode signal of “0” from the booster control circuit 24 and stops operating. The switches 52-1, 52-2,... Receive boosted power supply signals in the “0” state and boosted power supply clamp signals in the “0” state from the boost control circuit 24 and boost all memory cores. The voltage is cut off and the external power supply is not clamped. However, in this case, since the booster circuit 51 does not supply the boosted voltage, the state of the boosted power supply signal may be “0” or “1”.

  FIG. 7 is a diagram showing the configuration of the fifth embodiment of the power supply circuit to the memory core. In FIG. 7, the same elements as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted.

  7, the booster power supply circuit 25 includes a booster circuit 51, a booster power supply clamp circuit 61, and switches 62-1, 62-2,. Unlike the configuration of the fourth embodiment shown in FIG. 6, the switches 62-1, 62-2,... Receive boosted power supply signals # 1, # 2,. If the supply signal is in a “0” state indicating supply stop, the boosted voltage is cut off. Unlike the fourth embodiment, the switches 62-1, 62-2,... Are connected in series, so that fast recovery can only be selected from the side closer to the boost power supply. The boosting power supply clamp circuit 61 receives the boosting power supply clamp signal from the boosting control circuit 24, and clamps the boosted voltage output from the boosting circuit 51 to the external power supply if the boosting power supply clamp signal is in the “1” state indicating the external power supply clamp. To do.

  During normal operation, the booster circuit 51 receives an operation mode signal in the “1” state and supplies a boosted voltage. The switches 62-1, 62-2,... Receive the boosted power supply signal in the “1” state and supply the boosted voltage from the booster circuit 51 to the memory core. As for the memory core 29-1, the output of the booster circuit 51 is supplied as it is without passing through a switch. At this time, the boost power supply clamp signal is in the “0” state.

  At the time of power-down where there is a memory core to be restored at high speed, the booster circuit 51 receives the operation mode signal in the “0” state and stops operating. The boost power supply clamp circuit 61 receives the boost power supply clamp signal in the “1” state, and connects the boost voltage to the external power supply voltage. As a result, the external power supply voltage is supplied to the memory core 29-1 that is desired to be returned to high speed. Since this external power supply voltage is lower than the boosted voltage during normal operation, the leakage current in the memory core is reduced accordingly. In addition, since the external power supply voltage is applied to the memory core, the return to the boosted voltage is faster than the case of returning from the ground voltage to the boosted voltage. As for the low power consumption memory core, the switches 62-1, 62-2,... Receive the boosted power supply signal in the “0” state, and cut off the boosted power to the memory core. This reduces the leakage current in the memory core and realizes low power consumption.

  At the time of power-down where it is desired to reduce the power consumption of all the memory cores, the booster circuit 51 receives an operation mode signal of “0” and stops operating. The boost power supply clamp circuit 61 receives the boost power supply clamp signal in the “0” state and stops operating. Further, the switches 62-1, 62-2,... Receive the boosted power supply signal in the “0” state, and block the supply of the boosted voltage to all the memory cores. However, in this case, since the booster circuit 51 does not supply the boosted voltage and the clamp by the booster power supply clamp circuit 61 is not performed, the state of the booster power supply signal is “0” or “1”. It doesn't matter.

  FIG. 8 is a diagram showing the configuration of the sixth embodiment of the power supply circuit to the memory core. 8 includes booster circuits 51-1, 51-2,... And booster power clamp circuits 61-1, 61-2,. A plurality of booster circuits are provided corresponding to a plurality of memory cores on a one-to-one basis, and no switches are provided. Each of the booster circuits 51-1, 51-2,... Operates in the same manner as the booster circuit 51 of FIG. Further, each of the boost power supply clamp circuits 61-1, 61-2,... Operates in the same manner as the boost power supply clamp circuit 61 in FIG.

  During normal operation, each of the booster circuits 51-1, 51-2,... Receives an operation mode signal of “1” and outputs a boosted voltage. Thus, a predetermined boosted voltage is supplied from the booster circuits 51-1, 51-2,... To the memory cores 29-1, 29-2,. At this time, all the boost power supply clamp signals # 0, # 1,... Are in the “0” state, and the boost power supply clamp circuits 61-1, 61-2,.

  At the time of power down when there is a memory core that is to be restored to high speed, the booster circuit 51-1 corresponding to the memory core 29-1 that is to be restored to high speed receives the operation mode signal of “0” and stops the boosting operation. Further, the boosted power supply clamp signal # 0 is set to “1”, and the boosted power supply clamp circuit 61-1 clamps the boosted voltage to the external power supply voltage. As a result, the external power supply voltage is supplied to the memory core 29-1. Since this external power supply voltage is lower than the boosted voltage during normal operation, the leakage current in the memory core is reduced accordingly. In addition, since the external power supply voltage is applied to the memory core, the return to the boosted voltage is faster than the case of returning from the ground voltage to the boosted voltage. For the low power consumption memory core 29-2, the corresponding booster circuit 51-2 receives the "0" operation mode signal and stops the boosting operation. However, by setting the boost power supply clamp signal # 1 to the “0” state, the clamp operation by the boost power supply clamp circuit 61-2 is not executed. This reduces the leakage current in the memory core and realizes low power consumption.

  At the time of power-down where all the memory cores are desired to have low power consumption, all the booster circuits 51-1, 51-2,... Receive the operation mode signal of “0” and stop the operation, and all the booster power clamp circuits The boosting power source clamp signal with 61-1, 61-2,... "0" is received, and the clamping operation is not executed. This reduces leakage current in all memory cores and achieves low power consumption.

  FIG. 9 is a diagram showing the configuration of the seventh embodiment of the power supply circuit to the memory core. 9, the same components as those in FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. The boosting power supply circuit 25 of FIG. 9 includes boosting circuits 31-1 to 31-4. A plurality of booster circuits are provided corresponding to a plurality of memory cores on a one-to-one basis, and no switches are provided.

  During normal operation, each of the booster circuits 31-1 to 31-4 receives a booster stage number signal of “10” or “11” and operates with a two-stage booster. As a result, the boosted voltage of the two-stage boost is supplied from the booster circuits 31-1 to 31-4 to the memory cores 29-1 to 29-4.

  In the embodiment of FIG. 9, it is assumed that there is a memory core in which data is to be held in the power down mode. In other words, even in the power-down mode, a specified number of memory cores are scheduled to perform a refresh operation to hold data. In the example of FIG. 9, the memory core 29-1 is a memory core that performs the next refresh, and the memory core 29-2 is a memory core that is waiting for refresh (the next time the refresh is not yet performed). The booster circuit 31-1 corresponding to the memory core 29-1 that executes the next refresh selects the two-stage boosting by the boosting stage number signals # 0 and # 1 of “10” or “11”, and the boosting voltage of the two-stage boosting Supply.

  The booster circuit 31-2 corresponding to the memory core 29-2 waiting for refreshing receives a booster stage number signal of “01” and operates at a single booster. As a result, a boosted voltage of one step boost is supplied from the booster circuit 31-2 to the memory core 29-2. Further, the booster circuit 31-3 corresponding to the memory core 29-3 to be restored at high speed receives the "01" booster stage number signal and operates at a single booster. As a result, a boosted voltage of one step boost is supplied from the booster circuit 31-3 to the memory core 29-3. Since the boost voltage of this one-stage boost is set lower than that during the two-stage boost, the leak current in the memory core is small. In addition, since the one-step boosted voltage is applied to the memory core, the return to the two-stage boosted voltage is faster than the case where the ground voltage is boosted to the two-stage boosted voltage and returned.

  The booster circuit 31-4 corresponding to the low power consumption memory core 29-4 receives the booster stage number signal of “00” and stops the boosted voltage supply operation. This reduces the leakage current in the memory core and realizes low power consumption.

  At power-down when it is desired to reduce the power consumption of all the memory cores, all the booster circuits 31-1 to 32-4 receive the booster stage number signal of “00” and stop operating. Reduces power consumption by reducing leakage current in all memory cores.

  FIG. 10 is a diagram showing the configuration of the eighth embodiment of the power supply circuit to the memory core. 10, the same components as those in FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. The boosting power supply circuit 25 of FIG. 9 includes boosting circuits 31-1 to 31-4. A plurality of step-down power supply circuits 71-1 to 71-4 are provided corresponding to the memory cores 29-1 to 29-4 on a one-to-one basis. The operations of the booster circuits 31-1 to 31-4 are the same as those in the configuration of FIG.

  During normal operation, the step-down power supply circuits 71-1 to 71-4 receive the step-down power supply signals # 0 to # 3 in the "1" state and supply step-down power to the memory cores 29-1 to 29-4. The word line is driven by the boosted voltage generated by the booster circuits 31-1 to 31-4, and the stepped-down voltage generated by the step-down power supply circuits 71-1 to 71-4 is used as the power supply voltage for the other part of the memory core.

  At the time of power-down, the step-down power supply circuit 71-1 corresponding to the memory core 29-1 to be restored at high speed receives the step-down power supply signal in the “1” state and supplies the step-down power supply to the memory core 29-1. On the other hand, the step-down power supply circuits 71-2 to 71-4 corresponding to the low power consumption memory cores 29-2 to 29-4 receive the step-down power supply signal in the “0” state and stop supplying the step-down voltage. This reduces the leakage current of the memory core and realizes low power consumption.

  At the time of power-down in which it is desired to reduce the power consumption of all the memory cores, all the step-down power supply circuits 71-1 to 71-4 receive the step-down power supply signal in the “0” state and stop the supply of the step-down voltage. This reduces the leakage current in all the memory cores and realizes low power consumption.

  FIG. 11 is a diagram showing the configuration of the ninth embodiment of the power supply circuit to the memory core. In FIG. 11, the same components as those of FIG. 9 are referred to by the same numerals, and a description thereof will be omitted. The boosting power supply circuit 25 of FIG. 11 includes switches 72-1 to 72-3 in addition to the boosting circuits 31-1 to 31-4.

  During normal operation, all the switches 72-1 to 72-3 receive the boosted power supply connection signals # 1 to # 3 in the “1” state from the boost control circuit 24 and become conductive, so that adjacent boosted voltages are exchanged. Link. By connecting the boosted voltage in this way, the memory core capacity is shared, and there is an effect that the boosted power supply circuit noise and noise due to current consumption can be reduced and the boosted voltage can be stabilized. Further, only one of the booster circuits 31-1 to 31-4 may be selected as a two-stage booster by a booster stage number signal and supply a boosted voltage of a two-stage booster to the memory core. In other cases, the supply of boosted power may be stopped. By using only one booster circuit operating between the boosting power supplies connected in this way, the number of booster circuits driven can be reduced, and the power consumption can be reduced.

  At the time of power-down, the booster circuits 31-1 to 31-4 may be driven according to the state of each memory core as in the case of FIG. However, when two adjacent booster circuits are set to the same boosting stage number (the same boosted voltage) by the boosted voltage signal, the switch arranged between them receives the boosted power supply connection signal in the “1” state and is adjacent Connect the boost voltage. Conversely, when two adjacent boosting circuits are set to different boosting stage numbers (different boosting voltages) depending on the boosting voltage signal, the switch arranged between them receives the boosting power supply connection signal in the “0” state, Separate adjacent boosted voltages. The parts connected by the switch may be configured such that only one of the booster circuits is operated to reduce the number of booster circuit drives to reduce power consumption.

  At the time of power-down when it is desired to reduce the power consumption of all the memory cores, the operation of all the booster circuits 31-1 to 31-4 is stopped, and the leakage current is reduced in all the memory cores to realize the low power consumption. The switches 72-1 to 72-3 are turned on in response to the boosted power supply signal in the “1” state, and connect adjacent boosted voltages to all the memory cores.

  FIG. 12 is a diagram showing the configuration of the tenth embodiment of the power supply circuit to the memory core. In FIG. 12, the same components as those of FIG. 9 are referred to by the same numerals, and a description thereof will be omitted. In the configuration of FIG. 12, the operations of the booster circuits 31-1 to 31-4 of the booster power supply circuit 25 are the same as those in the configuration shown in FIG.

  In this embodiment, the memory cores 29-1 to 29-4 receive the starter signals # 0 to # 3, respectively, and can be reset independently. During normal operation, all starter signals # 0 to # 3 are set to "0" and the starter reset is not performed.

  At the time of power-down, the memory cores 29-1 and 29-2 to be refreshed are not reset because the starter signals # 0 and # 1 are in the “0” state. The memory core 29-3 to be restored at high speed is reset because the starter signal # 2 is in the "1" state. As a result, malfunctions can be avoided and through current can be prevented. Similarly, the memory core 29-4 with low power consumption is also reset because the starter signal # 3 is in the "1" state.

  At power-down when it is desired to reduce the power consumption of all memory cores, all starter signals # 0 to # 3 are set to the “1” state, and all the memory cores 29-1 to 29-4 are reset. As a result, malfunctions can be avoided and through current can be prevented.

  FIG. 13 is a block diagram showing an example of a configuration of a mobile phone to which the present invention is applied. The mobile phone shown in FIG. 13 includes a transmission / reception unit 81 having an antenna, an audio signal processing unit 82 that modulates transmission signals, demodulates received signals, and discriminates audio and data, and an audio input / output unit 83 that inputs and outputs audio. A DSP (Digital Signal Processor) 84 that encodes transmission data and decodes reception data, a display unit 85 that displays data, a CPU 86 that performs transmission / reception control and processing associated with each function, a telephone number, and the like Input section 87 and a memory section 88 for storing processing programs, received data, and the like.

  The memory unit 88 is a semiconductor device that includes a boosting power supply circuit that can boost from an external power supply or an internal step-down power supply and select the boosted voltage and the number of boosting stages, and can supply or stop the supply of the boosted voltage selected for each block. The CPU 86 supplies an external address signal having a bit pattern for mode setting together with a mode register setting command to the memory unit 88 in advance, and selects a memory core to be returned from the power down mode at high speed. The memory core that is desired to be restored at high speed is a memory that is used immediately after recovering from low power consumption in a non-operating state. The other memory core is a portion that is not used immediately after the return, and may be set as a low power consumption memory core so that it can be used after a time equivalent to the conventional one. As a result, it is possible to achieve both low power consumption during non-operation and high-speed recovery from non-operation.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present invention includes the following contents.
(Appendix 1)
A step-up power supply circuit that supplies at least one of a first predetermined voltage generated by boosting a predetermined power source and a second predetermined voltage lower than the first predetermined voltage;
A plurality of circuit blocks;
The step-up power supply circuit is controlled to supply the first predetermined voltage to the plurality of circuit blocks in the first operation mode, and a predetermined circuit of the plurality of circuit blocks in the second operation mode. A semiconductor integrated circuit, comprising: a boost control circuit that controls the boost power supply circuit so that the second predetermined voltage is supplied to a block and no voltage is supplied to other circuit blocks.
(Appendix 2)
The semiconductor integrated circuit according to claim 1, further comprising a register for storing data designating the predetermined circuit block, wherein the data of the register can be set from the outside.
(Appendix 3)
The semiconductor integrated circuit according to appendix 1, wherein the second predetermined voltage is a voltage of the predetermined power source.
(Appendix 4)
The plurality of circuit blocks are memory core blocks, and the step-up control circuit applies the first predetermined voltage to a circuit block that immediately executes refresh in the plurality of circuit blocks in the second operation mode. The semiconductor integrated circuit according to appendix 1, wherein the step-up power supply circuit is controlled so as to be supplied.
(Appendix 5)
The semiconductor integrated circuit according to appendix 1, further comprising a step-down power supply circuit configured to supply a voltage generated by stepping down a predetermined power supply independently for each of the plurality of circuit blocks.
(Appendix 6)
The semiconductor integrated circuit according to appendix 1, wherein the plurality of circuit blocks are memory core blocks, and are configured to receive independent starter signals and to be independently reset.
(Appendix 7)
And a switch that is connected between a plurality of voltage supply paths that respectively couple the booster power supply circuit and the plurality of circuit blocks, and that determines electrical connection / disconnection between the plurality of voltage supply paths. The semiconductor integrated circuit according to appendix 1.
(Appendix 8)
The boosting power supply circuit includes a plurality of boosting circuits provided in a one-to-one correspondence with the plurality of circuit blocks, and the boosting circuit corresponding to the circuit block whose power supply paths are electrically connected to each other by the switch, The semiconductor integrated circuit according to appendix 1, wherein the step-up control circuit controls the step-up power supply circuit so as to drive only one of them.
(Appendix 9)
CPU,
A step-up power supply circuit that supplies at least one of a first predetermined voltage generated by boosting a predetermined power source and a second predetermined voltage lower than the first predetermined voltage;
A plurality of circuit blocks;
The step-up power supply circuit is controlled to supply the first predetermined voltage to the plurality of circuit blocks in the first operation mode, and a predetermined circuit of the plurality of circuit blocks in the second operation mode. Including a step-up control circuit for controlling the step-up power supply circuit so that the second predetermined voltage is supplied to the block and no voltage is supplied to the other circuit blocks, and the CPU specifies the predetermined circuit block. Electronic device characterized.

It is a figure which shows the prior art example of a semiconductor memory device. It is a figure which shows an example of a structure of the semiconductor memory device by this invention. It is a figure which shows the structure of the 1st Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 2nd Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 3rd Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 4th Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 5th Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 6th Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 7th Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 8th Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 9th Example of the power supply circuit to a memory core. It is a figure which shows the structure of the 10th Example of the power supply circuit to a memory core. It is a block diagram which shows an example of a structure of the mobile telephone to which this invention is applied.

Explanation of symbols

20 Semiconductor memory device 21 Command control circuit 22 Operation control circuit 23 Mode register 24 Boost control circuit 25 Boost power supply circuit 26 Address input circuit 27 Address decoder 28 Data input / output circuit 29 Memory core circuit 29-1 to 29-4 Memory core 31 Boost Circuits 31-1 to 31-4 Booster circuits 32-1 to 32-4 Switches 42-1 to 42-4 Switch 51 Booster circuits 51-1 to 51-2 Booster circuit 61 Booster power supply clamp circuits 61-1 to 61-2 Step-up power supply clamp circuits 62-1 to 62-2 Switches 71-1 to 71-4 Step-down power supply circuits 72-1 to 72-3 Switch 81 Transmission / reception unit 82 Audio signal processing unit 83 Audio input / output unit 84 DSP (Digital Signal Processor)
85 Display 86 CPU
87 Input unit 88 Memory

Claims (5)

A step-up power supply circuit that supplies at least one of a first predetermined voltage generated by boosting a predetermined power source and a second predetermined voltage lower than the first predetermined voltage;
A plurality of circuit blocks;
The step-up power supply circuit is controlled to supply the first predetermined voltage to the plurality of circuit blocks in the first operation mode, and a predetermined circuit of the plurality of circuit blocks in the second operation mode. A semiconductor integrated circuit, comprising: a boost control circuit that controls the boost power supply circuit so that the second predetermined voltage is supplied to a block and no voltage is supplied to other circuit blocks.   2. The semiconductor integrated circuit according to claim 1, further comprising a register for storing data designating the predetermined circuit block, wherein the data of the register can be set from the outside.   2. The semiconductor integrated circuit according to claim 1, wherein the second predetermined voltage is a voltage of the predetermined power source.   The plurality of circuit blocks are memory core blocks, and the step-up control circuit applies the first predetermined voltage to a circuit block that immediately executes refresh in the plurality of circuit blocks in the second operation mode. 2. The semiconductor integrated circuit according to claim 1, wherein the boosting power supply circuit is controlled so as to be supplied.   2. The semiconductor integrated circuit according to claim 1, further comprising a step-down power supply circuit configured to supply a voltage generated by stepping down a predetermined power supply independently for each of the plurality of circuit blocks.

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