JP2007241315A - Active matrix circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve an area ratio (an aperture ratio) of a display electrode, and to prevent lowering of thin film transistor (TFT) characteristics caused by incidence of light on the TFT, in an active matrix circuit using the TFT as a switching element. <P>SOLUTION: A light shielding area is reduced by arranging a channel of the TFT under a source wire. Additionally, because the source wire is in this way superposed on the channel of the TFT, light incident on the TFT from the upside is cut off with the source wire and does not reach the TFT, and consequently the lowering of the TFT characteristics caused by external light is prevented. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix circuit having, as a switching element, a thin film transistor (TFT) used in an electro-optical device such as a liquid crystal display, or an electro-optical device using the active matrix circuit.

  An active matrix circuit is a method of displaying an image by switching transmission of signals to each pixel electrode using an active element such as a transistor or a diode, and has an excellent image display capability. Therefore, an active matrix circuit is a flat panel display (FPD). ) Is attracting attention as the core technology. Among them, those using TFTs as switching elements can display extremely good images and are commercially available for use in personal computers and projection (projector) display devices.

  An active matrix circuit using TFTs is connected to a plurality of gate lines (also called gate bus lines) and TFT sources for controlling the gate electrodes of TFTs on a single substrate, and transmits image information. A plurality of source lines (also referred to as source bus lines) are formed so as to be substantially orthogonal to each other. One or more pixel electrodes are provided at the intersection of each gate line and source line, and the pixel electrode is connected to the drain of the TFT.

  On the other hand, electrodes are also formed on the substrate facing the active matrix circuit, and a uniform voltage is usually applied thereto. A material having appropriate electro-optical response, for example, liquid crystal, is sandwiched between the active matrix circuit and the counter substrate. In the active matrix circuit, when a signal is applied to the gate line to turn on the TFT and a certain signal is sent to the source line, a signal (charge) passing through the TFT is applied to the pixel electrode. In this state, if the gate line signal is turned OFF, the charge held in the pixel electrode cannot be returned through the TFT, so that it is held until the next ON signal is applied to the gate line. . (Strictly speaking, charge leaks through various routes.)

  As described above, since the TFT, the source line, and the gate line are formed in the active matrix circuit, these prevent the light from being transmitted. That is, of the total area, the area ratio (called aperture ratio) that can be used for image display was small. Typically 30-60%. In particular, in a projection display device that irradiates an active matrix circuit with a powerful light source, the small aperture ratio means that much of the incident light is absorbed by TFTs, liquid crystal materials, etc., and these generate heat. It caused the deterioration of the characteristics. The present invention has been made in view of such problems, and is intended to improve the aperture ratio.

  The present invention is characterized in that a source line is provided to cover a TFT channel. In the present invention, the TFT may be a top gate type layered in the order of a thin film semiconductor region, a gate line (gate electrode), an interlayer insulator, and a source line on the substrate, but the gate line (gate electrode), A bottom gate type in which a thin film semiconductor region, an interlayer insulator, and a source line are stacked in this order may be used. However, when a bottom gate type TFT is used in a normal active matrix circuit, an interlayer insulator is not provided. However, in the present invention, an interlayer insulator is necessary to insulate a channel and a source line. It is.

9 and 10 show arrangement examples of TFTs in a conventional active matrix circuit. Although the gate line 19 and the source line 21 are arranged substantially orthogonally, a branch line 20 is provided from the gate line and is used as a gate electrode of the TFT by overlapping it on the thin film semiconductor region. A pixel electrode 22 and a contact 25 are formed at one end of the thin film semiconductor region, and a source line and a contact 24 are formed at the other end.
The portion of the thin film semiconductor region that substantially overlaps the gate line is the channel 23, which is formed away from the source line 21 as shown in FIGS. 9 and 10. Forming the gate line branch line 20 in this way is a cause of increasing the area occupied by the TFT and lowering the aperture ratio.

  In the present invention, no equivalent to such a branch line 20 is provided, and by providing a channel under the source line, the area occupied by the TFT can be reduced and the aperture ratio can be improved. In addition, the TFT channel is easily affected by light, and normally the entire TFT element is covered and a light shielding film is further formed. Therefore, the aperture ratio is further reduced. Since this shields outside light, it is not particularly necessary to form a light-shielding film, which is extremely effective in improving the aperture ratio.

The active matrix circuit having such a structure is extremely effective for a projection display device. That is, in the projection display device, as described above, in addition to the requirement for a high aperture ratio, since a strong light source is irradiated, it is absolutely necessary to take measures against light shielding of the TFT. In the present invention, if the projection light source is irradiated from the information of the source line, there is no problem because the TFT channel is reliably shielded from light by the source line.
According to the present invention, the aperture ratio of the active matrix circuit can be improved. Therefore, the display characteristics of the electro-optical device using the active matrix circuit can be improved. Thus, the present invention is industrially useful.

  BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the present invention will be described below in more detail with reference to examples.

  1 to 7 show this embodiment. First, a thickness of 100 to 100 having contact forming pad portions 3 and 5 and a channel forming portion 4 therebetween as shown in FIG. An island-shaped thin film silicon region 2 of 1500 mm, for example, 800 mm was formed. The silicon region may be amorphous silicon or polycrystalline silicon. (Figure 1)

  Next, a gate insulating film 6 was formed from silicon oxide having a thickness of 1200 mm. Furthermore, an appropriate amount of phosphorus was mixed to form a polycrystalline silicon film having improved conductivity to a thickness of 3000 mm by low pressure CVD, and this was etched to form the gate line 7. In addition to polycrystalline silicon, a metal material such as aluminum or tantalum may be used for the gate line. In particular, the use of aluminum was effective in reducing the sheet resistance of the gate wire. (Figure 2)

  Then, an impurity (8) (source) and 9 (drain) was formed by ion doping in the island-like silicon region 2 in a self-aligned manner using the gate line 7 as a mask. At this time, no impurity region is formed under the gate electrode, and the channel 4 is formed. After doping, the doped impurities may be activated by appropriate means (for example, thermal annealing or laser annealing). (Figure 3)

Thereafter, a silicon oxide film or a silicon nitride film 10 was formed to a thickness of 2000 to 10,000 mm, for example, 5000 mm by plasma CVD. In this way, a first interlayer insulator was formed. Then, a contact hole 11 reaching the contact pad 3 in the silicon region was formed therein. (Fig. 4)

  Thereafter, an aluminum film was formed to a thickness of 5000 mm by a sputtering method, and this was etched to form a source line 12. In the contact hole 11 formed by the previous step, the source line 12 made contact with the source 8. (Fig. 5)

Further, a second interlayer insulator 13 is formed from a silicon nitride film or a silicon oxide film having a thickness of 2000 to 5000 mm, for example, 000 mm, and a contact hole reaching the contact pad 5 in the island-shaped silicon region is formed therein. . Then, an ITO film having a thickness of 1000 mm was deposited by sputtering, and this was etched to form the pixel electrode 14. (Fig. 6)
In this embodiment, as shown in FIG. 7, the TFT channel direction (the direction from the source to the drain) is parallel to the source line. This is characteristic in comparison with the conventional TFT shown in FIG.

  In the present invention, not limited to this embodiment, since the channel 4 is located below the source line 12, unlike the conventional TFT, a part of the source and drain adjacent to the channel 4 overlaps with the source line and parasitic capacitance. Occurs. Of these, the problem in the operation of the active matrix circuit is the parasitic capacitance 15 formed between the drain 9 and the source line 12. However, as is apparent from FIG. 6, the drain 9 and the source line 12 are separated from each other by the first interlayer insulator 10, and the width of the island-shaped silicon region where the overlap occurs can be sufficiently narrowed. Furthermore, the image display is not greatly affected because the overlap is sufficiently small compared to the area of the pixel electrode 14.

  FIG. 8 shows this embodiment. The manufacturing process was the same as in Example 1. In this example, the island-like silicon region was formed in a substantially U-shape or U-shape, and a gate line was formed across the island-shape silicon region. For this reason, two channels (that is, TFTs) 16 and 17 were formed. Then, one end of the island-like silicon region was brought into contact with the source line and a source trench was formed on the channel 16. The other end was in contact with the pixel electrode.

  That is, as shown in FIG. 8, this embodiment has a structure in which two series TFTs are formed in one pixel. In this structure, it is known that the leakage current from the pixel can be reduced (Japanese Patent Publication No. 3-38755). However, in this embodiment, it is not necessary to provide a branch line from the gate line as in the prior art, so that the area occupied by the TFT is further increased. And the aperture ratio can be improved. Also in this embodiment, an overlap (parasitic capacitance) 18 occurs between the drain of the left TFT (which is also the source of the right TFT) and the source line. In this embodiment, however, compared to the case of the first embodiment. Further, since one TFT is inserted between the parasitic capacitor 18 and the pixel electrode, the influence is further limited. (Fig. 8)

A manufacturing process of a TFT in Example 1 will be described. A manufacturing process of a TFT in Example 1 will be described. A manufacturing process of a TFT in Example 1 will be described. A manufacturing process of a TFT in Example 1 will be described. A manufacturing process of a TFT in Example 1 will be described. A manufacturing process of a TFT in Example 1 will be described. The circuit arrangement of TFTs in Example 1 is shown. The circuit arrangement of TFT in Example 2 is shown. The circuit arrangement of the TFT in the conventional example is shown. The circuit arrangement of the TFT in the conventional example is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Insulating surface 2 ... Island-like silicon region 3, 5 ... Contact formation pad 4 ... Channel 6 ... Gate insulating film 7 ... Gate line 8 ... Source 9 ... Drain 10 ... First interlayer insulator 11 ... Contact hole 12 ... Source line 13 ... Second interlayer insulator 14... Pixel electrode 15... Parasitic capacitance 16, 17 .. Channel 18... Parasitic capacitance 19. Gate line branch (gate electrode)
21... Source line 22... Pixel electrode 23... Channel 24, 25.

Claims (2)

An active matrix circuit having a source line, a gate line, a pixel electrode, a first thin film transistor, and a second thin film transistor,
A source region of the first thin film transistor is connected to the source line;
The channel formation region of the first thin film transistor is entirely covered and shielded by the source line,
The drain region of the first thin film transistor is the source region of the second thin film transistor,
The drain region of the second thin film transistor is connected to the pixel electrode,
The channel formation region and drain region of the second thin film transistor do not overlap with the source line,
The channel formation region of the first thin film transistor and the channel formation region of the second thin film transistor are provided in the same semiconductor film formed in a U shape,
The channel formation region of the first thin film transistor, the channel formation region of the second thin film transistor, and the source line do not overlap the pixel electrode,
An active matrix circuit, wherein a channel formation region of the first thin film transistor and a channel formation region of the second thin film transistor overlap with the gate line. An active matrix circuit having a source line, a gate line, a pixel electrode, a first thin film transistor, and a second thin film transistor,
A source region of the first thin film transistor is connected to the source line;
The channel formation region of the first thin film transistor is entirely covered and shielded by the source line,
The drain region of the first thin film transistor is the source region of the second thin film transistor,
The drain region of the second thin film transistor is connected to the pixel electrode,
The channel formation region and drain region of the second thin film transistor do not overlap with the source line,
The channel formation region of the first thin film transistor and the channel formation region of the second thin film transistor are provided in the same semiconductor film formed in a U shape,
The channel formation region of the first thin film transistor, the channel formation region of the second thin film transistor, and the source line do not overlap the pixel electrode,
The channel formation region of the first thin film transistor and the channel formation region of the second thin film transistor overlap the gate line,
A first interlayer insulating film is provided on the gate line,
The source line is provided on the first interlayer insulating film,
A second interlayer insulating film is provided on the first interlayer insulating film and the source line;
An active matrix circuit, wherein the pixel electrode is provided on the second interlayer insulating film.

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