JP2007241214A5

JP2007241214A5 -

Info

Publication number: JP2007241214A5
Application number: JP2006136663A
Authority: JP
Filing date: 2006-05-16
Publication date: 2007-12-06
Anticipated expiration: 2026-05-16

Claims

A RAM block including a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a data read control circuit;
A data line driver block for driving a plurality of data line groups of the display panel based on data supplied from the RAM block;
Including
The data readout control circuit reads out pixel data corresponding to each data line of the plurality of data line groups from the RAM block in N (N is an integer of 2 or more) times in one horizontal scanning period ,
The data line driver block includes first to Nth divided data line driver blocks, each driving a different data line group of the plurality of data line groups,
Each of the first to Nth divided data line driver blocks is arranged along a first direction in which the plurality of bit lines extend.

In claim 1,
The data read control circuit includes a word line control circuit, and the word line control circuit selects N different word lines from the plurality of word lines in the one horizontal scanning period, and the display panel The integrated circuit device is characterized in that the same word line is not selected a plurality of times in one vertical scanning period during which vertical scanning is performed.

In claim 1 or 2,
The first to Nth divided data line drivers are supplied with first to Nth latch signals,
The integrated circuit device, wherein the first to Nth divided data line drivers latch data supplied from the RAM block based on the first to Nth latch signals.

In claim 3,
When the Kth reading (1 ≦ K ≦ N, K is an integer) is performed from the RAM block in the one horizontal scanning period, the Kth latch signal is set to active, so that the Kth An integrated circuit device, wherein data supplied from the RAM block is latched by the K-th divided data line driver by the second reading.

In claim 3 or 4,
The RAM block includes a sense amplifier circuit that outputs data of M (M is an integer of 2 or more) bits by one reading.
In the RAM block, at least M memory cells are arranged along a second direction in which the plurality of word lines extend,
An integrated circuit device, wherein M bit data is supplied to the sense amplifier circuit by one reading.

In claim 5,
Each of the first to Nth divided data line drivers drives the data line group based on M-bit data supplied from the RAM block,
An integrated circuit wherein each of the first to Nth divided data line drivers drives (M / G) data lines when the gradation of the pixel corresponding to the data line is G bits. apparatus.

In claim 5,
Each of the first to Nth divided data line drivers drives the data line group based on M-bit data supplied from the RAM block,
Each of the first to Nth divided data line drivers includes (M / G) data line driving cells when the gradation of the pixel corresponding to the data line is G bits.
An integrated circuit device, wherein each of the (M / G) data line driving cells drives one data line.

In claim 7,
When the display panel is in color display, (M / G) is a multiple of 3, and the (M / G) data line driving cells drive the data lines corresponding to the R pixels (M / 3G). ) R data line driving cells and data lines corresponding to G pixels (M / 3G) G data line driving cells and data lines corresponding to B pixels are driven (M / 3G) integrated circuit device comprising B data line driving cells.

In claim 7,
When the display panel is a color display, N is a multiple of 3,
(1/3) of the first to N-th divided data line drivers are composed of (M / G) R data line driving cells that drive data lines corresponding to R pixels,
The other (1/3) of the first to N-th divided data line drivers are composed of (M / G) G data line driving cells that drive data lines corresponding to G pixels,
Still another (1/3) of the first to Nth divided data line drivers are composed of (M / G) B data line driving cells that drive data lines corresponding to B pixels. An integrated circuit device.

In any one of Claims 5 thru | or 9,
Each of the first to Nth divided data line drivers includes first to Sth subdivided data line drivers (S is an integer of 2 or more) for subdividing each divided data line driver;
Each of the first to Sth subdivided data line drivers drives one data line when the gradation level of the pixel corresponding to the data line is G bits [M / (G × S)] including data line driving cells,
Each of the first to S subdivided data line drivers is arranged along the first direction.

In claim 10,
The integrated circuit device, wherein each of the first to Sth subdivided data line drivers is supplied with the same latch signal among the first to Nth latch signals.

In claim 8,
Each of the first to Nth divided data line drivers includes first to third subdivided data line drivers that subdivide each divided data line driver;
The first subdivision data line driver includes (M / 3G) R data line driving cells;
The second subdivision data line driver includes (M / 3G) G data line driving cells;
The third subdivision data line driver includes (M / 3G) B data line driving cells;
Each of the first to S subdivided data line drivers is arranged along the first direction.

In any one of Claims 1 to 12,
The integrated circuit device, wherein the plurality of word lines are formed in parallel with a direction in which the plurality of data lines provided on the display panel extend.

An electronic device comprising the integrated circuit device according to claim 1 and a display panel.

In claim 14,
The integrated circuit device is mounted on a substrate that forms the display panel.