JP2007241115A - Drive circuit of plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit of a PDP capable of driving the PDP with high efficiency without destructing a semiconductor element of a scan drive circuit constituting a drive circuit of the PDP. <P>SOLUTION: A collector terminal of an IGMT 25 is connected to a power supply Vcc line and an emitter terminal of the IGBT 25 is connected to an output terminal of an output circuit 21, respectively. A cathode terminal (K) of a diode 29 is connected to a line on the side of a power supply Vcc and an anode terminal of the diode 29 is connected to the output terminal, respectively. A collector terminal of an IGBT 27 is connected to an output terminal and an emitter terminal of the IGBT 27 is connected to a common sustain circuit through a virtual ground line, respectively. A cathode terminal of a diode 31 is connected to the output terminal and an anode terminal of the diode 31 is connected to the common sustain circuit 1 through the virtual ground line, respectively. A rectangular wave pulse is output to the corresponding scan electrode from the output terminal from the common sustain circuit 1 through the virtual ground line and the diode 31. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a driving circuit for driving a plasma display panel (hereinafter referred to as “PDP”).

  Conventionally, in the technical field of PDP, driving of surface discharge type PDP intended to improve the display quality by widening the range of applied voltage for address discharge and reducing the brightness of black display Methods and drive circuits have been proposed. In the reset period, a voltage higher than a discharge start voltage between the first and second sustain electrodes and a wall charge generated on the third sustain electrode side by discharge and a wall charge generated on the first sustain electrode side A voltage pulse for making the voltage between the first and second sustain electrodes higher than the discharge start voltage is applied between the first and second sustain electrodes. At this time, the address electrode potential is set to a substantially average value of both potentials of the first and second sustain electrodes. In the address period, a negative potential pulse is applied to the selected sustain electrode (second sustain electrode), and at the same time, a predetermined positive potential pulse is applied to the address electrode to be lit (see, for example, Patent Document 1).

  In addition, an insulated gate semiconductor device has been proposed that aims to achieve a soft recovery characteristic in which a diode built in a power MOSFET can be used as a protection diode by partially delaying the disappearance of stored carriers. In the insulated gate semiconductor device according to the proposal, the P + type base region is formed on the main surface of the N type semiconductor layer having the N + type layer, the N + source region is formed on the surface of the base region, and the channel portion is formed. A gate electrode is disposed. A P + type annular region is formed so as to surround the cell region in which the FET element is arranged, and an N + type blocking region is formed on the surface of the annular region. A source electrode is brought into contact with the blocking region, and a part of the annular region is partially contacted (see, for example, Patent Document 2).

  In addition, as described above, an insulated gate semiconductor device has been proposed that aims to achieve a soft recovery characteristic in which a diode built in a power MOSFET can be used as a protection diode by partially delaying the disappearance of stored carriers. Yes. In the insulated gate semiconductor device according to the proposal, the P + type base region is formed on the main surface of the N type semiconductor layer having the N + type layer, the N + source region is formed on the surface of the base region, and the channel portion is formed. A gate electrode is disposed. A P + type annular region is formed so as to surround the cell region in which the FET element is arranged. The annular region is partially contacted with the source electrode through a plurality of contact holes arranged at intervals (see, for example, Patent Document 3).

Japanese Laid-Open Patent Publication No. 7-20218 Japanese Patent Laid-Open No. 8-172183 JP-A-8-274311

  In the surface discharge type PDP, each of a plurality of linear address electrodes and scan electrodes for determining a location to emit light is orthogonal in each of a plurality of display cells which are the minimum light emission units arranged in a matrix. Are arranged so as to form a matrix. In addition, a plurality of linear common sustain electrodes for sustaining light emission in each display cell are arranged in parallel to the respective scan electrodes. A driving pulse is supplied to each address electrode from an address driving circuit. To each scan electrode, a rectangular wave pulse generated in the common sustain circuit is applied to each scan drive circuit connected in parallel to the ground line (virtual ground line described later) through the ground line (virtual ground line described later). Thus, a drive pulse is supplied from each scan drive circuit.

  The output stage of each scan drive circuit is, for example, an insulated gate bipolar transistor (hereinafter referred to as “IGBT”) between the power supply line and the output terminal (connected to the scan electrode) and between the output terminal and the ground line. Are connected to each other and have a totem pole configuration. The IGBT connected between the power supply line and the output terminal is provided with a diode having an anode terminal connected to the output terminal side and a cathode terminal connected to the power supply line side. Also, the IGBT connected between the output terminal and the ground line (virtual ground line described later) has an anode terminal connected to the ground line (virtual ground line described later) side and a cathode terminal connected to the output terminal side. A diode is provided. Then, the rectangular wave pulse from the common sustain circuit passes through the scan electrode through a diode connected in parallel to the IGBT connected between the output terminal and the ground line (virtual ground line described later) at the output stage of each scan drive circuit. Is output.

  However, in the output stage of each scan drive circuit, depending on the type of diode employed to connect between the output terminal and a ground line (virtual ground line described later), the drive pulse output from the common sustain circuit If the rise is too steep, there are some that cannot follow the rise of the drive pulse due to a response delay. Such a diode does not show the original characteristic as a diode for a while from the moment when the drive pulse output from the common sustain circuit rises sharply, but shows the characteristic as a general resistance element (that is, The diode appears to be a resistive element equivalently). In other words, a certain time (referred to as a forward recovery time of the diode) is required until the characteristic of the original diode (forward characteristic) is recovered from the characteristic as a general resistance element due to a response delay. The forward recovery time requires a time required for the diode forward voltage to return to about 0.6V to 0.7V by generating carriers from a state where no carriers are generated at the P / N junction. .

  For this reason, during the period from when the drive pulse having a steep rise is output from the common sustain circuit until the predetermined time elapses, current flows from the common sustain circuit to the diode connected between the output terminal and the ground line. A fairly large voltage will be applied to the diode. As a result, the diode may be destroyed, but a considerably large voltage is also applied to the IGBT connected between the output terminal and a ground line (virtual ground line described later). When the voltage exceeds the reverse withstand voltage (for example, about 20V) of the IGBT, there is a possibility that the IGBT is destroyed.

  As a measure to prevent the destruction of such diodes and IGBTs, if a drive pulse with a slow rise is output from the common sustain circuit, the PDP can be driven with high efficiency even if the destruction of the diodes and IGBTs can be avoided. The problem of being unable to do so arises.

  Accordingly, an object of the present invention is to provide a plasma display panel drive circuit capable of driving the plasma display panel with high efficiency without destroying the semiconductor elements of the scan drive circuit constituting the plasma display panel drive circuit. There is to do.

  A driving circuit for driving a plasma display panel according to the present invention includes a rectangular wave pulse voltage output for outputting a rectangular wave pulse voltage to the electrode, the output stage of which is connected to an electrode disposed inside the plasma display panel. A semiconductor power switching element that is turned on / off by an input control signal, and a rise time of the rectangular wave pulse voltage that is connected in parallel to the semiconductor power switching element. A semiconductor rectifying device having a small forward recovery time.

  In a preferred embodiment according to the present invention, the plasma display panel is an AC type plasma display panel.

  In another embodiment, the semiconductor power switching element is an insulated gate bipolar transistor.

  In an embodiment different from the above, the electrodes arranged inside the plasma display panel are a plurality of scan electrodes.

  In another embodiment, the rectangular wave pulse voltage output circuit receives the rectangular wave pulse voltage supplied from the rectangular wave pulse voltage generation circuit and applies the rectangular wave pulse voltage to the scan electrodes. It is a plurality of scan drive circuits provided for each electrode.

  In another embodiment different from the above, the rectangular wave pulse voltage generation circuit is a common sustain circuit.

  In another embodiment, the forward recovery time of the semiconductor rectifier element is 150 ns or less.

  Further, in another embodiment different from the above, after the discharge current for light emission finishes flowing in the plasma display panel, the rectangular wave pulse voltage is increased after the charged particles are accumulated in the semiconductor rectifier element. It is shorter than the time to fall.

  According to the present invention, there is provided a driving circuit for a plasma display panel capable of driving the plasma display panel with high efficiency without destroying the semiconductor elements of the scan driving circuit constituting the driving circuit for the plasma display panel. be able to.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a circuit configuration of a PDP drive circuit according to an embodiment of the present invention.

  The PDP drive circuit described above includes the common sustain circuit 1 and scan drive circuit group 3 shown in FIG. 1, and an address drive circuit group (not shown).

  The PDP 5 has a structure in which two glass plates (that is, a glass substrate and a glass plate) are bonded to each other with an appropriate interval therebetween. In the internal space defined by the two glass plates, a plurality of linear address electrodes (not shown) arranged parallel to the vertical direction of FIG. 1 and the horizontal direction of FIG. 1 are arranged. A plurality of linear scan electrodes (not shown) are orthogonal to each other to form a matrix. Further, a plurality of linear common sustain electrodes (not shown) are arranged in parallel with the respective scan electrodes. Each of the common sustain electrodes is for continuing light emission in the PDP 5.

  A display cell (not shown) which is a display pixel of the minimum light emission unit is formed by a location where each address electrode and each scan electrode are orthogonal and a location where each address electrode and each common sustain electrode are orthogonal. It is formed. A driving pulse is supplied to each address electrode from each address driving circuit (not shown) constituting an address driving circuit group, and a driving pulse is supplied from the common sustain circuit 1 to each common sustain electrode. .

  The common sustain circuit 1 generates light emission discharge in the PDP 5, generates a predetermined rectangular wave pulse, and outputs the predetermined rectangular wave pulse to the scan drive circuit group 3.

  The scan drive circuit group 3 includes a plurality of scan drive circuits provided for each scan electrode arranged in parallel in the horizontal direction of FIG. 1 in the internal space of the PDP 5 (in FIG. 9 and 11 are shown only). Each of the scan drive circuits has the same configuration, and includes a scan circuit power supply Ec13 that is a DC power supply (storage battery) and an output circuit 15, for example, as shown in the scan drive circuit 9. The negative side terminal of the scan circuit power supply Ec13 and the negative side power supply terminal of the output circuit 15 are all connected to a virtual ground line, and both terminals are in a so-called floating state. The output circuit 15 includes a + side power supply terminal, a scan signal input terminal 17, and an output terminal 19 connected to the scan electrode, in addition to the − side power supply terminal described above. The output circuit 15 performs a predetermined circuit operation (for example, switching operation) based on the scan signal applied to the scan signal input terminal 17.

  In the present embodiment, the output circuit 15 includes two IGBTs and two diodes as shown in the output circuit 21 of the scan drive circuit 7 and the output circuit 23 of the scan drive circuit 11, for example. In the following, by giving the same reference numerals to the ICBT and the diode on the output circuit 21 side, and the IGBT and the diode on the output circuit 23 side, respectively, and taking only the internal configuration on the output circuit 21 side as an example, Avoided duplication of explanation.

  In the output circuit 21, an IGBT 25 is connected between a line on the power supply Vcc side and an output terminal (connected to the scan electrode), and a diode 29 is connected in parallel with the IGBT 25. Further, an IGBT 27 is connected between the output terminal and the virtual ground line, and a diode 31 is connected in parallel with the IGBT 27. That is, the IGBT 25 and the IGBT 27 are connected by a totem pole connection. The diode 29 between the power supply line and the output terminal has an anode terminal connected to the output terminal side and a cathode terminal connected to the power supply Vcc side line, and a diode between the output terminal and the virtual ground line. 31 has an anode terminal connected to the virtual ground line side and a cathode terminal connected to the output terminal side.

  The operation (switching operation) of the IGBT 25 is performed by a voltage signal applied to the gate terminal of the MOSFET configuration (from a control unit (not shown)), and the operation (switching operation) of the IGBT 27 is the same (from a control unit (not shown)). Each is controlled by a voltage signal applied to the gate terminal of each.

  FIG. 2 is an enlarged view of a main part of the internal configuration of the scan drive circuit shown in FIG.

  As is clear from the contents described in FIG. 1, the IGBT 25 has its collector terminal (C) connected to the power supply Vcc side line and its emitter terminal (E) connected to the output terminal side (of the output circuit 21). Yes. The diode 29 connected in parallel to the IGBT 25 has its cathode terminal (K) connected to the power supply Vcc side line and its anode terminal (A) connected to the output terminal side (of the output circuit 21).

  On the other hand, the IGBT 27 has its collector terminal (C) connected to the output terminal side and its emitter terminal (E) connected to the common sustain circuit 1 through a virtual ground line. The diode 31 connected in parallel to the IGBT 27 has its cathode terminal (K) connected to the output terminal side and its anode terminal (A) connected to the common sustain circuit 1 through a virtual ground line.

  The rectangular wave pulse generated in the common sustain circuit 1 is output from the output terminal (of the output circuit 21) to the corresponding scan electrode (not shown) through the virtual ground line and the diode 31 from the common sustain circuit 1.

  FIG. 3 is a diagram illustrating the forward characteristics of a general diode.

  If the diode (29, 31) shown in FIG. 1 and FIG. 2 does not cause a response delay with respect to the rectangular wave pulse from the common sustain circuit 1, the current / anode-cathode voltage of the diode (29, 31). The characteristic indicates a forward characteristic as shown in FIG. That is, the forward voltage (anode-cathode voltage) in the diodes (29, 31) is about 0.6V to 0.7V as shown in FIG.

  Here, the configuration of the PDP 5 will be further described.

  As the PDP (5), an AC (alternating current) type PDP is used. The PDP (5) is in principle the same as a large number of micro fluorescent lamps arranged in an inner space defined by two glass plates (ie, a glass substrate and a glass plate), and equivalently, It is a capacitor (glass capacitor) including electrodes in an opposing relationship. Accordingly, the sustain drive voltage applied between the electrodes on the surface side of the PDP (5) through the scan drive circuit (7) from the common sustain circuit 1 rises, and the potential difference between the two electrodes is increased between the two electrodes. When the discharge start voltage is reached, discharge is started between the two electrodes, thereby causing the PDP (5) to emit light. On the other hand, when the sustain drive voltage falls below the discharge start voltage between the two electrodes, the discharge between the two electrodes is stopped, thereby stopping the light emission of the PDP (5).

  Further, the relationship between the sustain drive voltage and the sustain drive current in the PDP (5) will be described.

  When a sustain drive voltage (rectangular wave pulse) is applied to the common sustain circuit 1 to the PDP (5) (equivalently forming a glass capacitor when viewed from the circuit) through the scan drive circuit (7), they are arranged in parallel. In order to charge the capacitance (the glass capacitor) formed between the electrodes, first, a charging current (ineffective component of the sustain drive current) for charging the capacitance (the glass capacitor) flows. This charging current is independent of the discharge that occurs in the PDP (5). Next, after a lapse of a certain time (discharge delay time) after the charging current flows, a discharge current (sustain drive current) for actually causing light emission in the PDP (5) causes discharge. It flows between the electrodes arranged in parallel for the purpose.

  After the light emission discharge current (sustain drive current) for causing light emission flows in the PDP (5), even if the voltage level of the sustain drive voltage (rectangular wave pulse) is “High”, the light emission discharge current (Sustain drive current) does not flow. The reason is that PDP (5) is an AC type PDP.

  As an AC type PDP, for example, when a sustain drive voltage (rectangular wave pulse voltage) is applied between the electrodes on the surface side of the PDP (5), one electrode that becomes a positive potential by the application of the sustain drive voltage On the opposite parallel electrode opposite to, charged particles of opposite polarity (that is, negative) stick. On the other hand, charged particles of opposite polarity (that is, positive) stick to the opposite electrode that becomes negative potential by the application of the sustain drive voltage. Therefore, the application of the sustain drive voltage cancels the electric field to be formed inside the PDP (5) due to the above-described sticking of the positive and negative charged particles to the electrode. Therefore, even if the voltage level of the sustain drive voltage applied to the PDP (5) is still “High”, no light emission discharge current (sustain drive current) flows through the PDP (5).

  Next, when the voltage level of the sustain drive voltage described above for PDP (5) switches from "High" to "Low", it is accumulated on the parallel interelectrode capacitance (the glass capacitor) (PDP (5)) side. The charged electric charge becomes a discharge current (sustain drive current having a reverse flow direction) and flows from the PDP (5) side to the scan drive circuit (7) side.

  FIG. 4 is a diagram showing a waveform of a sustain drive voltage applied from the common sustain circuit 1 to the PDP (5) through the scan drive circuit (7), and FIG. 5 shows a PDP from the common sustain circuit 1 through the scan drive circuit (7). It is a figure which shows the waveform of the sustain drive current which flows into (5).

  4, the vertical axis represents the sustain drive voltage, the horizontal axis represents time, and in FIG. 5, the vertical axis represents the sustain drive current (discharge current), and the horizontal axis represents the time. As is clear from the above description, the waveform of the sustain drive voltage (generated by the common sustain circuit 1 and applied to the PDP (5) through the scan drive circuit (7)) is ideally a rectangular wave pulse. It is. However, the actual sustain drive voltage waveform is not a regular rectangular wave as shown in FIG.

  In FIG. 4, time tr is the time required for the sustain drive voltage to rise, and time tf is the forward recovery time of the diodes (29, 31) (the state in which no carriers are generated in the vicinity of the P / N junction). To the time required until sufficient carriers are generated). In order to drive the PDP (5) with high efficiency, it is necessary to satisfy the condition that tr is sufficiently small and tf is further small. As shown in FIG. 5 for the time tr, the sustain drive current (the charging current described above) flows from the common sustain circuit 1 to the PDP (5) through the scan drive circuit (7).

  Next, during a certain period of time from when the sustain driving current (the above-described charging current) starts to flow, that is, until the discharge delay time elapses (t1-tr), the voltage level of the sustain driving voltage is Even if it is “High” as shown in FIG. 4, the sustain drive current (the discharge current for the light emission discharge described above) does not flow. When the discharge delay time elapses and the time t1 is reached, as shown in FIG. 5, the sustain drive current for the light emission discharge described above flows. The sustain drive voltage at that time is as shown in FIG. It will be in a slightly lowered state.

  At the time t2 from the time when the sustain driving current for the light emission discharge ends to the time when the sustain driving voltage starts to shift from the voltage level “High” to the voltage level “Low” as shown in FIG. Even if the voltage level of the sustain drive voltage is “High”, the sustain drive current does not flow for the reasons described above. Then, as the voltage level of the sustain drive voltage starts to shift from “High” to “Low” at time t2, the discharge current (reverse direction) from the PDP (5) side toward the scan drive circuit (7) side. (Sustain driving current) starts to flow, and stops flowing when the voltage level of the sustain driving voltage becomes "Low".

  In FIG. 4, tsus indicates a time width during which the sustain drive voltage is at the voltage level “High”, tstg is a time during which charged particles are accumulated in the diodes (29, 31), and tstg < There is a relationship of t2. In other words, the time from when the discharge current for light emission ends to when the discharge current starts to flow from the PDP (5) side toward the scan drive circuit (7) is longer than the diode (29, 31) longer than the time during which the current is present.

  In general, in order to improve the forward recovery characteristics (shortening the forward recovery time) of the diode (29, 31), it is necessary to generate a large number of carriers particularly in the vicinity of the P / N junction of the diode (29, 31). There is. However, if a large number of carriers are generated, even if the forward recovery time of the diode (29, 31) can be shortened, the reverse recovery characteristic of the diode deteriorates (reverse recovery time becomes longer). Will come.

  However, at time t2 shown in FIG. 5, even if the voltage level of the sustain drive voltage is “High” as shown in FIG. 4, the sustain drive current (discharge current) is the AC type as described above. Since it does not flow due to the characteristics of the PDP (5), only residual carriers exist in the diodes (29, 31), and it is sufficient that they disappear during t2. Therefore, in improving the forward recovery characteristic of the diode (29, 31), it is not necessary to consider the adverse effect on the reverse recovery characteristic of the diode (29, 31).

  FIG. 6 is a diagram showing a waveform of the sustain drive voltage applied to the PDP (5) from the PDP drive circuit according to the embodiment of the present invention. In FIG. 6, the vertical axis represents voltage (unit V), and the horizontal axis represents time (unit ns).

  6A shows the waveform of the sustain drive voltage with a rise of 80 ns / div. FIG. 6B shows the waveform of the sustain drive voltage with a rise of 200 ns / div. The inventors of the present invention have used the PDP drive circuit configured as described above, and the sustain drive voltage shown in FIG. 6 (a) is 80 ns / div. And the rise shown in FIG. 6 (b) is 200 ns / div. By applying a sustain drive voltage to the PDP (5), a breakdown voltage experiment of the scan ICs constituting the scan drive circuit (7, 9, 11) shown in FIG. 1 was performed. A scan IC having a model number of STV-7697A (manufactured by ST Micro) was used as a scan IC as an object of the pressure resistance experiment.

  As a result of this experiment, when the sustain drive voltage having a rise of 80 ns / div. Shown in FIG. 6A is applied to the PDP (5), the rise shown in FIG. 6B is 200 ns / div. It was found that the scan IC constituting the scan drive circuit (7, 9, 11) shown in FIG. 1 has a much higher frequency of destruction than when the sustain drive voltage waveform is applied. Note that when the sustain drive voltage with a rise of 200 ns / div. Was applied, the scan IC was hardly destroyed.

  Therefore, the inventors of the present invention based on the results of this experiment, raised the sustain drive voltage that can drive the plasma display panel with high efficiency without destroying the scan drive circuit (7, 9, 11). The time is set to 130 ns to 150 ns, preferably 150 ns. In other words, when an element having a forward recovery time of about 150 ns is used for the diode (29, 31), a large voltage is not generated at both ends of the diode (29, 31). The PDP (5) can be driven with high efficiency without being destroyed by the application of the sustain drive voltage. The present invention is based on such novel findings.

  As a technical document related to the forward recovery time of the diodes (29, 31) described above, E.sukegawa et.al. "Well-tempered combination of ultra-high voltage IGBT and Diode rated 6.5kV" Proc. Of The 15th See international Symposium on Power Semiconductor Devices and Integrated Circuits (ISPSD'03), p.160.

  Incidentally, the forward recovery time of the diode (29, 31) is obtained by filling the conduction carrier in the n-layer in the diode (29, 31) as shown in FIG. 29, 31) by shortening the time until the resistance is reduced. Furthermore, the transient maximum forward voltage VF transient of the diode (29, 31) can also be reduced. In the above-mentioned document, there is no description about a specific method for shortening the forward recovery time in the diode (29, 31). However, as knowledge of the present inventors, the diode (29, 31) is not found. Examples of means for shortening the time during which the inside can be filled with excess conductive carriers are listed below.

  (1) Excess carriers to the n− layer by increasing the impurity concentration of the p-layer on the anode side or increasing the impurity concentration of the n + layer on the cathode side and increasing the impurity concentration gradient To increase the injection efficiency of the carrier and thereby reduce the time required for carrier accumulation.

  (2) A method for reducing the time required for carrier accumulation by reducing the thickness of the n− layer.

  The preferred embodiments of the present invention have been described above, but these are merely examples for explaining the present invention, and the scope of the present invention is not limited to these embodiments. The present invention can be implemented in various other forms.

The figure which shows the circuit structure of the drive circuit of PDP which concerns on one Embodiment of this invention. FIG. 2 is an enlarged view of a main part of the internal configuration of the scan drive circuit shown in FIG. The figure which shows the forward direction characteristic of a general diode. The figure which shows the waveform of the sustain drive voltage applied to PDP. The figure which shows the waveform of the sustain drive current which flows into PDP. The figure which shows the waveform of the sustain drive voltage applied with respect to PDP from the drive circuit of PDP which concerns on one Embodiment of this invention.

Explanation of symbols

1 Common sustain circuit 3 Scan drive circuit group 5 AC type plasma display panel (AC type PDP)
7, 9, 11 Scan drive circuit 13 Scan circuit power supply Ec which is a DC power supply (storage battery)
15, 21, 23 Output circuit 17 Scan signal input terminal 19 Output terminal (connected to scan electrode) 25, 27 Insulated gate bipolar transistor (IGBT)
29, 31 Diode

Claims (8)

In a drive circuit for driving a plasma display panel,
A rectangular wave pulse voltage output circuit for outputting a rectangular wave pulse voltage to the electrode, wherein an output stage is connected to an electrode disposed inside the plasma display panel;
With
The output stage is
A semiconductor power switching element that is turned on / off by an input control signal;
A semiconductor rectifier element connected in parallel to the semiconductor power switching element and having a forward recovery time sufficiently smaller than a rise time of the rectangular wave pulse voltage;
A driving circuit for a plasma display panel. In the drive circuit of the plasma display panel according to claim 1,
A driving circuit for a plasma display panel, wherein the plasma display panel is an AC type plasma display panel. In the drive circuit of the plasma display panel according to claim 1,
A driving circuit of a plasma display panel, wherein the semiconductor power switching element is an insulated gate bipolar transistor. In the drive circuit of the plasma display panel according to claim 1,
A driving circuit for a plasma display panel, wherein the electrodes arranged inside the plasma display panel are a plurality of scan electrodes. In the drive circuit of the plasma display panel according to claim 1,
A plurality of scan driving circuits provided for each of the scan electrodes, wherein the rectangular wave pulse voltage output circuit receives the rectangular wave pulse voltage supplied from the rectangular wave pulse voltage generation circuit and applies the rectangular wave pulse voltage to the scan electrodes; A driving circuit for a plasma display panel. In the driving circuit of the plasma display panel according to claim 5,
A driving circuit for a plasma display panel, wherein the rectangular wave pulse voltage generation circuit is a common sustain circuit. In the drive circuit of the plasma display panel according to claim 1,
A driving circuit for a plasma display panel, wherein a forward recovery time of the semiconductor rectifier element is 150 ns or less. In the drive circuit of the plasma display panel according to claim 1,
The time during which charged particles are accumulated in the semiconductor rectifier element is shorter than the time until the rectangular wave pulse voltage falls after the discharge current for light emission finishes flowing in the plasma display panel. Driving circuit for plasma display panel.

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