JP2007239003A - Au plating method and manufacturing method of au circuit by au plating - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an Au plating method capable of forming an Au plating layer uniformly on an Si substrate or forming a continuous Au plating fine line of nanometer level. <P>SOLUTION: The Au plating method of forming the Au plating layer 2 on the Si substrate 1 comprises: a substrate layer forming process of forming a substrate layer 3 consisting of a C-S-Au film which includes C, S and Au and has a semiconductive property; and an Au plating process of subjecting the substrate layer 3 to Au plating according to electroplating to form the Au plating layer 2 on the substrate layer 3. Therein, the substrate layer 3 is formed on the surface of the Si substrate 1, then a resist film is partially formed, C-S-Au exposure parts where the C-S-Au film of the substrate layer 3 are exposed on parts besides the resist film are formed in a prescribed pattern and, when forming the Au plating layer 2 on the C-S-Au exposure parts by using a working pattern of resist as a mask, the continuous Au plating fine line of nanometer level can be formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an Au plating method for forming an Au plating layer on a Si substrate, and a method for manufacturing an Au circuit by Au plating in which an Au circuit made of an Au plating layer is formed on a Si substrate in a predetermined pattern.

  Conventionally, aluminum wiring has been used for semiconductor integrated circuits. However, in recent years, copper wiring having high conductivity has been used due to the demand for miniaturization of wiring circuits. As research on single-electron transistors operating at room temperature progresses, it is desired to further miniaturize element devices of high-density integrated circuits. For this reason, not only the element dimensions but also further miniaturization of the wiring circuit is required.

  When the wiring circuit is miniaturized, the ratio of the surface area to the cross-sectional area increases, so that the substantial conductor cross-sectional area decreases. In addition, since many metals are oxidized, the substantial conductor cross-sectional area is significantly reduced by oxidation.

  Therefore, the present inventor adopted chemically stable and hardly oxidized gold as a metal material for wiring in order to achieve further miniaturization of the wiring circuit while suppressing a substantial decrease in the conductor cross-sectional area, and wiring by gold plating. Invented to form a circuit.

  However, even if gold plating is attempted on a Si base material used for a semiconductor device, a uniform plating layer cannot be formed. This is presumably because the bonding force between Si and Au is low.

  Further, even if gold plating is performed in a groove having a width of 500 nm, for example, in order to form a nanometer-level gold-plated fine wire on the Si substrate, it becomes discontinuous, and a continuous gold-plated fine wire cannot be formed. The reason why such a discontinuous thin wire is formed is not necessarily clear, but it may be due to the non-uniformity of the plating current, the non-uniform oxidation of the Si substrate, and the microloading effect due to the difficulty of ions entering narrow areas. .

  In addition, a compound thin film containing a metal and an organic substance is known as a new material that replaces a conventional material system that is widely used in the fields of electronics and optics (see, for example, Patent Document 1).

This compound thin film was devised for the purpose of providing a novel optical system material having a high refractive index and a high transmittance, and is a C—S—Au film made of C, S and Au. This C—S—Au film introduces a hydrocarbon gas, SF ₆ gas and Ar gas between a pair of parallel plate electrodes, applies a high frequency voltage between the pair of parallel plate electrodes, and discharges the gas by plasma discharge. At the same time, by sputtering an Au plate placed on one electrode surface, a C—S—Au film is deposited on a substrate placed on the other electrode surface. This C—S—Au film is promising as an optical system material that is transparent and has a high refractive index because even if a relatively large amount of Au is contained, Au is not uniformly dispersed to form a cluster.
JP 2004-100012 A

  The present invention has been made in view of the above circumstances, and the first technical problem is to create a novel Au plating method capable of uniformly forming an Au plating layer on a Si substrate. The second technical problem is to form nanometer-level continuous gold-plated fine wires on the Si substrate using the Au plating method.

  The Au plating method of the present invention that solves the above-mentioned problems is an Au plating method for forming an Au plating layer on a Si substrate, and contains C, S, and Au on the Si substrate and has semiconductivity. A base layer forming step of forming a base layer made of a C—S—Au film; and an Au plating step of forming an Au plating layer on the base layer by performing Au plating by electroplating. It is what.

  In this Au plating method, a uniform Au plating layer can be formed by performing Au plating on a semiconductive C—S—Au film formed as a base layer. In the C—S—Au film, C—S—Au molecules are bonded in the order of C, S, and Au. Note that it is considered that C and S are bonded by a covalent bond or an ionic bond, and S and Au are bonded by an ionic bond. Then, it is considered that C in the C—S—Au film is bonded to Si by a covalent bond, and Au in the C—S—Au film is bonded to the Au plating layer by a metal bond. For this reason, C in the C—S—Au film is bonded to the Si substrate with a large bonding force, and Au in the C—S—Au film is bonded to the Au plating layer with a large bonding force. Therefore, the Au plating layer can be reliably bonded to the Si substrate via the C—S—Au film functioning as an adhesive layer, and a uniform Au plating layer can be formed.

  In a preferred embodiment, the Au plating method of the present invention is a C—S— in which a resist film is partially formed on the underlayer, and the C—S—Au film is exposed in a portion other than the resist film. After performing a resist process for forming the Au film exposed portion in a predetermined pattern, the Au plating step is performed to form the Au plated layer on the C—S—Au film exposed portion.

  In this Au plating method, a resist film is partially formed on a semiconductive C—S—Au film formed as an underlayer, thereby forming a C—S—Au film exposed portion in a predetermined pattern. To do. A uniform Au plating layer is formed by performing Au plating on the C—S—Au film exposed portion. For this reason, a uniform Au plating layer can be formed with a predetermined pattern on the Si substrate by forming the CS—Au film exposed portion with a predetermined pattern by forming a resist film.

  In this Au plating method, an Au plating layer is formed on the groove-like C—S—Au film exposed portion partitioned by the resist film. For this reason, when the width | variety of the CS-Au film | membrane exposed part is narrowed, an Au plating layer will be formed in a thin groove | channel. When an Au plating layer is formed in such a narrow groove, it is difficult to form a continuous Au plating layer due to the microloading effect described above. In this regard, in the plating method of the present invention, an Au plating layer is formed using a semiconductive C—S—Au film as a base layer. For this reason, it is possible to form a continuous Au plating layer even when the width of the CS-Au film exposed portion is narrowed and the Au plating layer is formed in a narrow groove.

  Therefore, if the resist film is oxidized and removed after the Au plating step, nanometer-level continuous gold-plated fine wires can be formed on the Si substrate.

In a preferred aspect, the Au plating method of the present invention is a method in which the surface of the Si base is lithographically processed to form a Si pillar portion and / or Si wall portion and the Si pillar portion and / or the Si wall portion having a predetermined pattern. A lithography process for forming Si grooves other than the surface on the surface, and oxidizing at least the entire Si pillar part and / or the Si wall part and the surface of the Si groove part to obtain SiO ₂ pillar parts and / or SiO ₂ walls. and parts as well as the oxidation treatment step of forming a SiO ₂ groove, wherein by the surface of the Si substrate is isotropically etched to be substantially flat, at least the SiO while leaving the insulating SiO ₂ parts of the SiO ₂ groove ₂ pillar portions and / or the SiO ₂ wall portion are removed to form a conductive Si exposed portion where the Si base material is exposed at the site where the SiO ₂ pillar portion and / or the SiO ₂ wall portion is removed. Isotropic etch And a step after carrying implements the underlying layer forming step.

In this Au plating method, first, a Si pillar portion and / or Si wall portion and a Si groove portion having a predetermined pattern are formed on the surface of the Si base material by lithography, and then at least a Si pillar portion and / or by an oxidation treatment. The entire Si wall portion and the surface of the Si groove portion are oxidized to form the SiO ₂ pillar portion and / or the SiO ₂ wall portion and the SiO ₂ groove portion. Thereafter, by performing an isotropic etching process so that the surface of the Si base becomes substantially flat, at least the SiO ₂ column part and / or the SiO ₂ wall part is removed while leaving the insulating SiO ₂ part of the SiO ₂ groove part. A conductive Si exposed portion is formed in the removed portion. Thus, after forming the insulating SiO ₂ portion and the conductive Si exposed portion in a predetermined pattern on the surface of the Si base material, the underlayer is formed. Then, a uniform Au plating layer is formed by performing Au plating on the semiconductive C—S—Au film formed as the base layer. At this time, the Au plating layer formed by electroplating is not formed on the insulating SiO ₂ portion, but only on the conductive Si exposed portion where current flows. For this reason, by forming a Si pillar portion and / or Si wall portion with a predetermined pattern by lithography processing, and forming a Si exposed portion at this portion, uniform Au with a predetermined pattern on the Si substrate A plating layer can be formed.

  Further, in this Au plating method, Au plating is performed on the Si base that has been made substantially flat by isotropic etching through the underlayer, so that the Au plating property is not deteriorated by the microloading effect. Therefore, it is possible to form a continuous Au plating layer having a narrower width than that of the Au plating method according to claim 2. Accordingly, by reducing the diameter of the Si pillar portion or reducing the thickness of the Si wall portion, it is possible to form a continuous gold-plated fine wire at a nanometer level.

  5. The method of manufacturing an Au circuit by Au plating according to claim 4, wherein the Au circuit made of an Au plating layer is formed in a predetermined pattern on an Si substrate, the Au circuit being manufactured by Au plating, A base layer forming step of forming a base layer made of a C—S—Au film containing C, S and Au and having a semiconductivity; and a resist film is partially formed on the base layer; A resist process for forming a CS-Au film exposed portion where the CS-Au film is exposed in a portion other than the resist film in a predetermined pattern, and electroplating on the CS-Au film exposed portion An Au plating process for forming the Au plating layer by applying Au plating, a resist film removing process for removing the resist film, an oxidation treatment on the surface of the Si base material, and Insulation process to insulate from materials That it comprises a and is characterized in.

In this Au circuit manufacturing method by Au plating, a continuous Au plating layer having a predetermined pattern is formed using the Au plating method according to claim 2. Then, after removing the resist film, the surface of the Si base is oxidized to insulate the Au plating layer from the Si base. In this manner, an Au circuit made of an Au plating layer having a predetermined pattern can be formed on the Si substrate via the insulating SiO ₂ layer.

  Therefore, according to the Au circuit manufacturing method by Au plating according to claim 4, it is possible to form a fine nanometer level Au circuit.

An Au circuit manufacturing method by Au plating according to claim 5 is a method of manufacturing an Au circuit by Au plating in which an Au circuit made of an Au plating layer is formed in a predetermined pattern on an Si substrate, wherein the Si substrate A lithographic process of forming a Si pillar portion and / or Si wall portion and a Si groove portion and / or Si groove portion other than the Si wall portion in a predetermined pattern on the surface by lithography processing the surface of An oxidation treatment step of oxidizing the entire Si pillar part and / or the Si wall part and the surface of the Si groove part to form an SiO ₂ pillar part and / or SiO ₂ wall part and SiO ₂ groove part, and the Si base material substantially by isotropic etching such that the flat, removing the SiO ₂ at least the SiO ₂ column portion while leaving the insulating SiO ₂ parts of grooves and / or the SiO ₂ wall surface of Te, and an isotropic etching step for forming the SiO ₂ column portions and / or the SiO ₂ wall conductive Si exposed portion Si substrate is exposed to the site that was removed, on the Si substrate, A base layer forming step of forming a base layer made of C—S—Au containing C, S and Au and having semiconductivity; Au plating is performed on the base layer, and only the conductive Si portion is An Au plating step for forming an Au plating layer; and an insulating treatment step for oxidizing the surface of the Si base material to insulate the Au plating layer from the Si base material. is there.

In this Au circuit manufacturing method by Au plating, a continuous Au plating layer having a predetermined pattern is formed using the Au plating method according to claim 3. Then, the surface of the Si base is oxidized to insulate the Au plating layer from the Si base. In this manner, an Au circuit made of an Au plating layer having a predetermined pattern can be formed on the Si substrate via the insulating SiO ₂ layer.

  Therefore, according to the method for manufacturing an Au circuit by Au plating according to claim 5, it is possible to form a finer nanometer level Au circuit than the method for manufacturing an Au circuit by Au plating according to claim 4. Become.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

  In the following description, “%” means “atomic%”.

(Embodiment 1)
The embodiment shown in FIGS. 1 and 2 embodies the Au plating method according to claim 1. This Au plating method forms the Au plating layer 2 on the Si substrate 1, and includes an underlayer forming step and an Au plating step.

<Underlayer formation process>
In the base layer forming step, as shown in FIG. 1A, the base layer 3 made of a C—S—Au film having semiconductivity is formed on the Si base material 1.

  The Si substrate 1 is not particularly limited as long as it has semiconductivity doped with impurities.

  The underlayer 3 is a C—S—Au film containing C, S, and Au and having semiconductivity, and is interposed between the Si base 1 and the Au plating layer 2 formed on the underlayer 3. It has adhesiveness for adhering the Au plating layer 2 to the Si substrate 1 and semiconductivity that enables Au plating by flowing electricity in a direction parallel to the film surface during Au plating.

  Here, the C—S—Au film having semiconductivity is a film in which a conductor (conductive particles) is dispersed in an insulator, and a film that enables Au plating on the C—S—Au film. Means. In the C—S—Au film having semiconductivity, the electric conduction characteristics change depending on the applied electric field, but electricity flows in a direction perpendicular or parallel to the film surface by movement of electrons by hopping or the like. In the C—S—Au film, conductive particles of about 0.4 to 1.5 nm formed by bonding 2 to 3 C—S—Au molecules are semiconductive to the C—S—Au film. Gives sex. The semiconductivity of this C—S—Au film varies depending on the Au content in the film.

  When the Au content in the C—S—Au film is less than 7%, the size and number of the conductive particles are insufficient and the semiconductivity is reduced. On the other hand, when the Au content in the film is 7% or more, a large number of conductive particles bonded with 2 to 3 C—S—Au molecules are uniformly dispersed in the film, and good semiconductivity is exhibited. To do. From the viewpoint of improving the semiconductivity of the C—S—Au film, the Au content in the film is more preferably 8% or more, and particularly preferably 10% or more. The Au content in the C—S—Au film is adjusted by changing the gas pressure and the flow rate of the supplied reactive gas (Ar, etc.) when the C—S—Au film is formed by the plasma CVD method. be able to. However, it is not always easy to increase the Au content. Further, if the Au content in the C—S—Au film becomes too large, the bonding strength between the C—S—Au film and the Si substrate may be reduced due to the lack of the C content in the film. Therefore, the upper limit of the Au content is preferably about 30%, more preferably about 15%.

  Further, the S content in the C—S—Au film is preferably equal to or greater than the Au content, and particularly preferably equal to the Au content. In the C—S—Au film, Au is not bonded to C but bonded to S. For this reason, when S content in a film | membrane becomes less than Au content, the C-S-Au molecule | numerator in a film | membrane will run short, and semiconductivity will fall. On the other hand, if the S content in the C—S—Au film is too high, the bonding strength between the C—S—Au film and the Si substrate may be reduced due to the insufficient C content in the film.

  Note that the C content in the C—S—Au film is preferably larger than the S content from the viewpoint of securing the bonding strength with the Si substrate.

  Further, the C—S—Au film is preferably less if the content of the impurity element is small, but if it is small enough not to impair the functions (adhesiveness and semiconductivity) required for the C—S—Au film. , C, S and elements other than Au (F, O, etc.) may be included.

  The thickness of the base layer 3 made of a C—S—Au film may be set to the size of one conductive particle in which 2 to 3 C—S—Au molecules are bonded, that is, about 0.4 to 5 nm. preferable. If the underlayer 3 is too thin, the effect of undercoating the C—S—Au film cannot be obtained sufficiently. On the other hand, if the thickness of the underlayer 3 is too thick, the underlayer 3 becomes unstable, and the adhesion and uniformity of the Au plating layer 4 may be reduced. For this reason, it is more preferable that the thickness of the underlayer 3 is about 0.8 to 1.5 nm.

  The underlayer 3 made of this C—S—Au film can be suitably formed using the apparatus schematically shown in FIG.

  This apparatus is a reactor for plasma CVD and Au sputtering, and has a chamber 4, a pair of parallel plate electrodes 5, 6 disposed in the chamber 4 so as to face each other, and a pair of parallel plate electrodes 5, 6. Are provided with a high-frequency power source 7 for applying a high-frequency power, a gas supply path 8 for supplying a reaction gas into the chamber 4, and an exhaust pump 9 for maintaining the chamber 4 at a predetermined gas pressure.

  The Si base 1 is placed on the opposing surface 5a of the parallel plate electrode 5 on one side (lower side in FIG. 2), and the mesh-like opposing surface 6a of the parallel plate electrode 6 on the other side (upper side in FIG. 2). With the Au plate 10 installed, a reaction gas is introduced into the chamber 4 from the gas supply path 8 and a predetermined high frequency power is applied from the high frequency power source 7 to the pair of parallel plate electrodes 5 and 6. Under the gas pressure, the reactive gas is discharged and the Au plate 10 is sputtered to form a C—S—Au film on the Si substrate 1. At this time, the composition ratio of the C—S—Au film to be formed can be adjusted by changing the gas pressure in the chamber 4 or the flow rate ratio of the reaction gas.

As the reaction gas, for example, a hydrocarbon gas as a C source and a mixed gas of SF ₆ gas and Ar gas as an S source can be suitably used. The gas pressure in the chamber 4 is preferably about 0.07 to 0.2 Torr, so that the Au content in the C—S—Au film can be about 7 to 15%, which is preferable.

  In the C—S—Au film thus formed, Au is uniformly dispersed in the film without aggregation and forming clusters.

<Au plating process>
In the Au plating step, as shown in FIG. 1B, Au plating by electroplating is performed to form the Au plating layer 2 on the base layer 3.

  The plating conditions for Au plating by this electroplating are not particularly limited and can be set as appropriate. Further, the thickness of the Au plating layer 2 is not particularly limited and can be set as appropriate.

  According to the experiments by the present inventors, the Au plating layer 2 could be formed on the Si substrate 1 by connecting the Si substrate 1 to the negative electrode side during electroplating.

  The Au plating layer 2 obtained in this way becomes a uniform film that is securely bonded to the Si substrate 1.

(Embodiment 2)
This embodiment shown in FIG. 3 embodies the Au plating method according to claim 2. In this Au plating method, in the first embodiment, a resist process is performed after the underlayer forming process, and a resist film removing process is performed after the Au plating process.

<Underlayer formation process>
As in the first embodiment, in the underlayer forming step, as shown in FIG. 3A, the underlayer 3 made of a semiconductive C—S—Au film is formed on the Si base 1. To do.

<Resist process>
In the resist process, as shown in FIG. 3B, a patterned resist film 11 is partially formed on the base layer 3.

  The formation method of this resist film 11 is not specifically limited, For example, the method of developing, after spin-coating and pattern-drawing an electron beam resist on Si base material 1 can be used suitably. The conditions at this time are not particularly limited, and can be set as appropriate.

  Thus, the resist film 11 is partially formed on the underlayer 3, and a C—S—Au film exposed portion 12 in which the C—S—Au film of the underlayer 3 is exposed to a portion other than the resist film 11 is predetermined. Form with a pattern.

<Au plating process>
In the Au plating step, as shown in FIG. 3C, Au plating is performed by electroplating, and the Au plating is formed on the CS-Au film exposed portion 12 formed on the underlayer 3. Layer 2 is formed.

<Resist film removal process>
In the resist film removing step, the resist film 11 is removed as shown in FIG.

  The method for removing the resist film 11 is not particularly limited, and for example, an oxidation removal method using oxygen plasma can be suitably used. The conditions at this time are not particularly limited, and can be set as appropriate.

  In this manner, a linear Au plating layer 2 can be formed in a predetermined pattern on the surface of the Si substrate 1.

  In the Au plating method of this embodiment, an Au plating layer is formed using a semiconductive C—S—Au film as a base layer. Therefore, even when the Au exposed layer 12 is narrowed to form the Au plated layer 2 in a narrow groove, the continuous Au plated layer 2 can be formed. Therefore, according to this embodiment, nanometer-level continuous gold-plated fine wires can be formed on the Si substrate 1.

(Embodiment 3)
This embodiment shown in FIG. 4 embodies the Au circuit manufacturing method according to claim 4 by Au plating. In the Au circuit manufacturing method by Au plating, the underlayer forming step, the resist step, the Au plating step, and the resist film removing step (FIGS. 4A to 4D) similar to those in the second embodiment are performed. After the implementation, an insulation treatment process is performed.

<Insulation process>
In this insulating treatment step, as shown in FIG. 4 (e), the surface of the Si base 1 is oxidized to form an insulating SiO ₂ layer 13 having a predetermined thickness on the surface layer portion. The plating layer 2 is insulated from the Si substrate 1.

In this way, the Au circuit 14 made of the Au plating layer 2 having a predetermined pattern can be formed on the Si base 1 via the insulating SiO ₂ layer 13.

  Therefore, according to the Au circuit manufacturing method by the Au plating of the present embodiment, it is possible to form a fine nanometer level Au circuit 14.

(Embodiment 4)
This embodiment shown in FIG. 5 embodies the Au plating method according to claim 3. In this Au plating method, in the first embodiment, a lithography process, an oxidation treatment process, and an isotropic etching process are performed before the base layer forming process.

<Lithography process>
In the lithography process, as shown in FIG. 5A, the surface of the Si substrate 1 is subjected to lithography processing to form a Si pillar portion and / or Si wall portion 15 having a predetermined pattern, and the Si pillar portion and / or Alternatively, Si grooves 16 other than the Si wall 15 are formed on the surface.

  The shape, size, and the like of the Si pillar portion and / or the Si wall portion 15 processed in this lithography process can be appropriately set according to the Au plating layer 2 to be formed. Further, only one of the Si pillar portion and the Si wall portion may be formed, or both may be combined.

  Also, the lithography processing method, conditions, and the like are not particularly limited, and can be set as appropriate. For example, an electron beam negative resist is used to form a resist film having a thickness that can withstand Si etching, and after drawing and developing an electron beam, the surface of the Si substrate 1 is subjected to RIE plasma etching using the resist pattern as a mask. The Si pillar portion and / or the Si wall portion 15 having a predetermined pattern can be formed by etching.

<Oxidation process>
In the oxidation treatment step, as shown in FIG. 5 (b), at least the entire Si pillar portion and / or Si wall portion 15 and the surface of the Si groove portion 16 are oxidized to form SiO ₂ pillar portions and / or SiO ₂ walls. The part 17 and the SiO ₂ groove part 18 are formed.

  At this time, oxidation treatment is performed until the Si pillar portion and / or the Si wall portion 15 are all oxidized. Note that the surface of the Si substrate 1 at the portion where the Si pillar portion and / or the Si wall portion 15 stands may be either not oxidized or slightly oxidized.

<Isotropic etching process>
The isotropic etching process, FIG. 5 as shown in (c), by isotropic etching so that the surface of the Si substrate 1 is substantially flat, insulated portion of the SiO ₂ groove 18 of SiO ₂ Conductivity in which the Si substrate 1 is exposed at a portion where the SiO ₂ pillar part and / or the SiO ₂ wall part 15 is removed by removing at least the SiO ₂ pillar part and / or the SiO ₂ wall part 15 while leaving the part 19. The reactive Si exposed portion 20 is formed.

At this time, the SiO ₂ column part and / or the SiO ₂ wall part 15 are completely removed, and isotropic etching is performed until the Si base material 1 is exposed in this part. The method and conditions of this isotropic etching process are not particularly limited, and can be set as appropriate. For example, by exposing to an isotropic etching plasma of SiO _{2, the} SiO ₂ pillar part and / or the SiO ₂ wall part 15 can be removed from the horizontal direction, and the SiO ₂ pillar part and / or the SiO ₂ wall part 15 disappears. At the time, the surface of the Si substrate 1 can be made substantially flat. Further, by continuing isotropic etching, the non-oxidized Si base material 1 can be exposed in a predetermined size.

Thus, the insulating SiO ₂ portion 19 and the conductive Si exposed portion 20 are formed in a predetermined pattern on the surface of the Si base 1.

  Then, the said foundation | substrate layer formation process is implemented and the said foundation | substrate layer 3 is formed in the whole surface of Si base material 1. FIG.

Then, the Au plating process is performed, and the uniform Au plating layer 2 is formed by performing Au plating on the semiconductive C—S—Au film formed as the base layer 3. At this time, the Au-plated layer 2 formed by electroplating is not formed on the insulating SiO ₂ portion 19 because the C—S—Au film as the underlayer 3 is extremely thin. It is formed only on the Si exposed portion 20.

  For this reason, the Si pillar portion and / or the Si wall portion 15 having a predetermined pattern is formed by lithography processing, and the Si exposed portion 20 is formed at this portion, thereby forming a predetermined pattern on the Si substrate 1. A uniform Au plating layer 2 can be formed.

  Further, in this Au plating method, Au plating is performed on the Si base 1 made substantially flat by the isotropic etching process through the base layer 3, so that the Au plating property may be lowered by the microloading effect. Absent. For this reason, it is possible to form a continuous Au plating layer 2 having a narrower width than the Au plating method of the second embodiment. Therefore, for example, by making the thickness of the Si wall portion thinner, it is possible to form a continuous fine gold-plated fine wire of nanometer level.

(Embodiment 5)
This embodiment shown in FIG. 6 embodies the Au circuit manufacturing method by Au plating according to claim 5. In this Au circuit manufacturing method by Au plating, the lithography process, the oxidation treatment process, the isotropic etching process, the underlayer formation process, and the Au plating process similar to those in the fourth embodiment (FIG. 6A to FIG. 6). After carrying out (e)), an insulation treatment process is carried out.

<Insulation process>
In this insulating treatment step, as shown in FIG. 6 (f), the surface of the Si base material 1 is oxidized, and a SiO ₂ layer is formed so as to overlap the insulating SiO ₂ portion 19. An insulating SiO ₂ layer 13 having a predetermined thickness is formed on the part to insulate the Au plating layer 2 from the Si base 1.

By this oxidation treatment, the C—S—Au film of the base layer 3 in the region not covered with the Au plating layer 2 is oxidized, and carbon, CO ₂ , and sulfur are vaporized and removed as SO ₂ .

In this way, the Au circuit 20 made of the Au plating layer 2 having a predetermined pattern can be formed on the Si base 1 via the insulating SiO ₂ layer 13.

  Therefore, according to the Au circuit manufacturing method by Au plating of the present embodiment, it is possible to form a nanometer level Au circuit 21 that is finer than the Au circuit 14 formed in the third embodiment.

Example 1
In accordance with the Au plating method of the second embodiment, an Au fine wire having a width of 500 nm was formed on a Si substrate.

  A resist film is formed by spin coating an electron beam resist (“SAL601”, manufactured by Shipley Co., Ltd.) on an impurity-doped semiconductive n-type Si substrate. Thus, a groove having a width of 500 nm (corresponding to the Si exposed portion 12 shown in FIG. 3) was formed.

The pattern was drawn using an electron beam drawing apparatus (“JBX-6000SG”, manufactured by JEOL) under the conditions of 50 kV, 1000 pA, and an irradiation dose of 100 μC / cm ² .

Then, using the plasma CVD and Au sputtering reaction vessel using the resist processing pattern as a mask, an underlayer made of a C—S—Au film having a thickness of about 1 nm is formed in the groove under the conditions shown in Table 1 below. 3 was formed. In Table 1, SCCM is a flow rate (cm ³ ) converted to an ideal gas (0 ° C., 760 mmHg) per minute. Further, 100 W, 13.56 MHz high frequency power was applied from the high frequency power source 7, and the reaction time was 30 minutes.

  As a result, a C—S—Au film containing 8% Au atoms and including conductive particles of 0.4 to 0.6 nm and showing semiconductivity was formed as shown in Table 1. Note that the atomic ratio of the C—S—Au film was analyzed by ESCA (Electron Spectroscopy for Chemical Analysis). In addition, the C—S—Au film exhibits semiconductivity when a DC voltage of 4 to 5 kV is applied between a pair of electrodes made of a deposited Cu film arranged to face each other with a 1 mm gap. This was confirmed by not discharging.

Then, Au plating was performed using the resist processing pattern as a mask. In this Au plating, electroplating was performed by applying a voltage of 9 V using a plating solution in which NaAuCl ₄ was dissolved in ethanol at 0.5 atomic% and using an impurity-doped semiconductive n-type Si substrate as a negative electrode.

  As a result, as shown in the SEM image of FIG. 7, a continuous Au thin wire having a width of 500 nm could be created.

(Comparative Example 1)
A C—S—Au film was prepared in the same manner as in Example 1 except that the gas pressure and gas flow rate shown in Table 1 were changed.

  As a result, as shown in the atomic ratio in Table 1, a C—S—Au film having a content of Au atoms of 2% and showing no semiconductivity was obtained.

(Comparative Example 2)
Au plating was performed using the resist processing pattern as a mask in the same manner as in Example 1 except that the base layer 3 made of the C—S—Au film was not formed.

  As a result, as shown in the SEM image of FIG. 8, a thin line pattern having a line and space width of 100 nm was confirmed. However, this Au thin wire is discontinuous and cannot be used for circuit wiring, for example.

It is a fragmentary sectional view explaining typically an Au plating method of Embodiment 1, (a) shows a foundation layer formation process, and (b) shows an Au plating process. It is a figure which shows roughly the reactor for plasma CVD and Au sputtering used with Au plating method of Embodiment 1. FIG. It is a fragmentary sectional view showing typically an Au plating method of Embodiment 2, (a) shows foundation layer formation affirmation, (b) shows a resist process, (c) shows an Au plating process, d) shows a resist film removing step. FIG. 6 is a partial cross-sectional view schematically illustrating a method of manufacturing an Au circuit by Au plating according to Embodiment 3, wherein (a) shows a resist process, (b) shows an underlayer forming process, and (c) shows Au plating. (D) shows a resist film removal process, (e) shows an insulation treatment process. It is a fragmentary sectional view which explains Au plating method of Embodiment 4 typically, (a) shows a lithography process, (b) shows an oxidation treatment process, (c) shows an isotropic etching process, d) shows an underlayer forming process, and (e) shows an Au plating process. FIG. 10 is a partial cross-sectional view schematically illustrating a method of manufacturing an Au circuit by Au plating according to Embodiment 5, wherein (a) shows a lithography process, (b) shows an oxidation treatment process, and (c) shows isotropic etching. (D) shows an underlayer forming process, (e) shows an Au plating process, and (f) shows an insulation treatment process. 2 is a SEM (scanning electron microscope) photograph showing an Au fine wire created in Example 1. FIG. 5 is a SEM (scanning electron microscope) photograph showing an Au fine wire created in Comparative Example 2.

Explanation of symbols

1 ... Si substrate 2 ... Au plating layer 3 ... underlayer (C-S-Au film) 11 ... resist film 12 ... Si exposed portion 13 ... insulating SiO ₂ layer 14, 21 ... Au circuit 15 ... Si pillar portion ( Si wall)
16 ... Si groove part 17 ... SiO ₂ pillar part (SiO ₂ wall part)
18 ... SiO ₂ groove portion 19 ... insulating SiO ₂ portion 20 ... conductive Si exposed portion

Claims (5)

An Au plating method for forming an Au plating layer on a Si substrate,
A base layer forming step of forming a base layer made of a C—S—Au film containing C, S and Au and having semiconductivity on the Si substrate;
An Au plating method comprising: an Au plating step of performing Au plating by electroplating to form the Au plating layer on the underlayer.   A resist process in which a resist film is partially formed on the base layer, and a CS-Au film exposed portion in which the CS-Au film is exposed in a portion other than the resist film is formed in a predetermined pattern 2. The Au plating method according to claim 1, wherein the Au plating step is performed to form the Au plating layer on the C—S—Au film exposed portion. 3. Lithographic process of lithographically processing the surface of the Si base to form Si pillar portions and / or Si wall portions of a predetermined pattern and Si groove portions other than the Si pillar portions and / or the Si wall portions on the surface. When,
An oxidation treatment step of oxidizing at least the entire Si pillar part and / or the Si wall part and the surface of the Si groove part to form a SiO ₂ pillar part and / or a SiO ₂ wall part and a SiO ₂ groove part;
By surface of the Si substrate is isotropically etched to be substantially flat, removing at least the SiO ₂ column portion and / or the SiO ₂ wall portion while leaving the insulating SiO ₂ parts of the SiO ₂ groove Then, after performing the isotropic etching step of forming a conductive Si exposed portion where the Si base material is exposed at the site where the SiO ₂ pillar portion and / or the SiO ₂ wall portion is removed, 2. The Au plating method according to claim 1, wherein a formation step is performed. A method of manufacturing an Au circuit by Au plating, in which an Au circuit comprising an Au plating layer is formed in a predetermined pattern on a Si substrate,
A base layer forming step of forming a base layer made of a C—S—Au film containing C, S and Au and having semiconductivity on the Si substrate;
A resist process in which a resist film is partially formed on the base layer, and a CS-Au film exposed portion in which the CS-Au film is exposed in a portion other than the resist film is formed in a predetermined pattern When,
An Au plating step of forming the Au plating layer by performing Au plating by electroplating on the CS-Au film exposed portion;
A resist film removing step for removing the resist film;
A method of manufacturing an Au circuit by Au plating, comprising: an oxidation treatment step of oxidizing the surface of the Si substrate to insulate the Au plating layer from the Si substrate. A method of manufacturing an Au circuit by Au plating, in which an Au circuit made of an Au plating layer is formed in a predetermined pattern on a Si substrate,
Lithographic process of lithographically processing the surface of the Si base to form Si pillar portions and / or Si wall portions of a predetermined pattern and Si groove portions other than the Si pillar portions and / or the Si wall portions on the surface. When,
An oxidation treatment step of oxidizing at least the entire Si pillar part and / or the Si wall part and the surface of the Si groove part to form a SiO ₂ pillar part and / or a SiO ₂ wall part and a SiO ₂ groove part;
By surface of the Si substrate is isotropically etched to be substantially flat, removing at least the SiO ₂ column portion and / or the SiO ₂ wall portion while leaving the insulating SiO ₂ parts of the SiO ₂ groove Then, an isotropic etching step of forming a conductive Si exposed portion where the Si base material is exposed at the site where the SiO ₂ pillar portion and / or the SiO ₂ wall portion is removed,
A base layer forming step of forming a base layer made of a C—S—Au film containing C, S and Au and having semiconductivity on the Si substrate;
An Au plating step of performing Au plating by electroplating on the underlayer and forming the Au plating layer only on the conductive Si portion;
A method of manufacturing an Au circuit by Au plating, comprising: an oxidation treatment step of oxidizing the surface of the Si substrate to insulate the Au plating layer from the Si substrate.

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