JP2007235986A - Data processing apparatus and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing apparatus which obviates reproduction of a system clock utilizing a PCR superimposed on a broadcasting signal and is configured by omitting a PLL circuit. <P>SOLUTION: A system clock at a fixed frequency is generated and in accordance with this system clock, decode processing of encoded video data is carried out. At this time, based on the amount of the encoded video data temporarily accumulated before demodulation processing, the output timing of a video signal to be demodulated is controlled. Thus, even without making a circuit system for demodulating the encoded video data operate by the system clock in synchronizism with a reference clock (PCR) transmitted from an encoding device side, a demodulation output timing of the encoded video data in synchronism with the PCR can be obtained and the PLL circuit for system clock generation synchronized with the PCR can be dispensed with. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing apparatus for demodulating encoded data obtained by encoding time-series data such as a video signal, such as an MPEG decoder, and a data processing method thereof.

Conventionally, with the start of digital satellite broadcasting services, digital satellite broadcasting receivers have generally started to spread. As is well known, in the digital satellite broadcasting system, MPEG2 (Moving Picture Experts Group Layer2) system is adopted as the digital video / audio encoding format.
For this reason, the digital satellite broadcast receiver first obtains stream data including a video / audio signal received by the parabolic antenna and compressed by, for example, the MPEG2 system from the supplied broadcast signal. The compressed audio signal, video signal, etc. are distributed from the stream. Then, these signals are demodulated by the MPEG decoder.

FIG. 12 is a diagram showing a configuration in the MPEG decoder 105 provided in the conventional digital satellite broadcast receiver. In this figure, only the part related to the demodulation of the video signal of the MPEG decoder 105 is extracted and shown.
First, the demultiplexer 104 shown in this figure extracts a video signal encoded by the MPEG2 system from the supplied stream data. PCR and PTS are separated.
Of each signal and information separated in this way, the PCR is supplied to the PCR demodulator 112. The PTS is supplied to the PTS demodulator 113. The video signals are supplied to the delay memories 114, respectively.

Here, as is well known, PCR (Program Clock Reference) and PTS (Presentation Time Stamp) are superimposed on stream data as a broadcast signal by time division multiplexing in a digital satellite broadcasting system adopting the MPEG2 format. Information.
This PCR is also called a program time base reference value, and is generated based on the timing of the system clock in the MPEG encoder on the encoder side (encoding device side) of the broadcast signal. That is, it has information on the frequency of the system clock at the time of encoding on the encoder side. This PCR is multiplexed so as to be inserted at intervals of about 100 ms depending on the format of the PCR packet.
PTS is reproduction output time management information, which is attached by an MPEG encoder. By this PTS, for example, the reproduction output timing for each frame image or each access unit of encoded data is designated. That is, it functions as information for designating the reproduction output timing.

  The PCR demodulator 112 demodulates the PCR from the PCR packet separated and extracted from the demultiplexer 104, and obtains the value as the PCR. The PCR value thus obtained is supplied to the comparator 116.

  An STC (System Time Clock) counter 111 is a part that counts clocks generated by a PLL (Phase Locked Loop) circuit 120, and the count value of the STC counter 111 is also supplied to the comparator 116.

  The comparator 116 compares the PCR value with the count value of the STC counter 111 and outputs error information to the PLL circuit 120.

The PLL circuit 120 is a so-called voltage variable PLL circuit including, for example, a VCXO (voltage variable crystal oscillator), and operates to lock based on error information output from the comparator 116. Thereby, in a state where the PLL circuit 120 is locked, a system clock having a frequency synchronized with the PCR is generated. That is, a system clock that matches the MPEG encoder can be obtained also on the decoder side. The frequency signal output from the PLL circuit 120 is supplied to each unit as a system clock in the MPEG decoder 105. The decoder unit 105 executes demodulation (decoding) processing on the encoded video signal based on the system clock.
Further, since the STC counter 111 generates an STC by inputting a system clock, the STC becomes synchronization information faithful to the timing of the system clock.

The PTS demodulator 113 is a part that demodulates the PTS and acquires a value as a time stamp that specifies the playback output timing of the decoded video signal.
The acquired PTS value is supplied to the output timing control unit 117.

  The output timing control unit 117 compares the PTS value supplied in this way with the count value supplied from the STC counter 111 as shown in the figure, and the value (output time) indicated by the PTS and the value of the STC counter ( The decoder unit 115 is controlled so that a required video signal is output in accordance with the coincidence of the current time.

The video signal output from the demultiplexer 104 is first input to the delay memory 114, temporarily stored therein, and then output to the decoder unit 115. The decoder unit 115 performs an MPEG decoding process on the input video signal at a timing based on the system clock, and outputs a demodulated video signal.
At this time, the reproduction output timing of the demodulated video signal is controlled by the control of the output timing control unit 117 described above.

  With such a configuration, the MPEG decoder 105 can accurately reproduce the system clock that matches the encoder side, and at the proper timing that is supposed to match the system clock on the encoder side. Signal reproduction output can be performed.

  As described above, in a conventional MPEG decoder, a PLL circuit is provided to generate a system clock synchronized with PCR. Then, the MPEG decoder 5 operates based on this system clock, so that decoding processing can be performed and reproduced and output at an appropriate timing that coincides with the system clock on the encoding device side.

However, a PLL circuit including a VCXO (Voltage Variable Oscillator) is widely used for the MPEG decoder, but such a PLL circuit is generally expensive, and the cost of manufacturing a conventional MPEG decoder is low. It has been difficult to achieve reduction.
In addition, it is difficult to configure a PLL circuit including the VCXO as a one-chip LSI, and the VCXO is generally externally attached. For this reason, in manufacturing a conventional MPEG decoder, it is difficult to reduce the size of the apparatus.

  In addition, when a broadcast signal including a non-standard MPEG stream is received, for example, the continuity of PCR is not guaranteed, an internal clock is generated based on the PCR as described above depending on the conventional MPEG decoder. Therefore, there is a problem that the frequency of the generated clock is significantly different.

  Further, in the conventional MPEG decoder, since the output of the predetermined image data is executed when the current time by STC coincides with the output time by PTS, in principle, when the continuity of PTS is not guaranteed. There is a possibility that output images may be missing or overlapped.

For this reason, in the present invention, in view of the above problems, the data processing apparatus is configured as follows.
That is, the data processing apparatus of the present invention demodulates encoded video data in which a video signal is encoded, encoded audio data in which an audio signal is encoded, and the encoded video data and encoded audio data. The data processing apparatus is supplied with output time management information for specifying the reproduction output timing when reproducing the video signal and the audio signal, and includes a clock generation means for generating a system clock with a fixed frequency.
A data storage means for temporarily storing the encoded video data; and a video signal obtained by demodulating the encoded video data read from the data storage means at a timing according to a system clock having the fixed frequency. Is provided with video demodulating means for reproducing and outputting the video.
In addition, audio demodulation means for demodulating the encoded audio data and reproducing and outputting an audio signal is provided.
Further, the storage amount of the encoded video data stored by the data storage means is compared with a predetermined threshold value, and if the storage amount is equal to or less than the predetermined threshold value as a result of this comparison, the video signal is Control means for controlling the video demodulation means so that the video signal is reproduced and output repeatedly in a predetermined time unit, and the video signal is skipped and reproduced in a predetermined time unit when the accumulated amount is equal to or greater than a predetermined threshold; Synchronous output means for synchronously outputting a video signal demodulated by the video demodulating means and an audio signal demodulated by the audio demodulating means based on the output time management information.

Depending on the above configuration, when the video signal encoded by the encoding device is demodulated and output, the encoded video data is demodulated with a system clock having a fixed frequency.
At this time, the output timing of the demodulated video signal is controlled based on the accumulation amount of the encoded video data temporarily accumulated before the demodulation process.
In such a configuration, the demodulated output of the encoded video data synchronized with the reference clock can be performed without operating a circuit system for demodulating the encoded video data with a system clock synchronized with the reference clock transmitted from the encoding device side. Timing will be obtained.

In this way, according to the present invention, the reproduction output timing specified by the encoding device side is synchronized with the actual reproduction output timing without generating a system clock synchronized with the reference clock transmitted from the encoding device side. It becomes possible to plan. This means that a PLL circuit for generating a system clock synchronized with the reference clock is not necessary, and the manufacturing cost of the apparatus can be reduced and the apparatus can be downsized.
In particular, as compared with the case where a voltage variable type PLL circuit is used, this voltage variable type PLL circuit cannot be made into one chip because of the need for an external component. The benefits of conversion will be significant.

  If the reference clock (PCR) is not required, even if a non-standard MPEG stream is input, for example, the continuity of the PCR superimposed on the broadcast signal is not guaranteed, Inconvenience that the frequency of the system clock greatly deviates due to malfunctioning is also eliminated.

Conventionally, since the display timing of frame images is controlled so that the output time management information (PTS) coincides with the system clock (STC), if the continuity of PTS is not guaranteed, the output is performed in principle. There was a possibility of missing or overlapping images. For example, if such a phenomenon occurs frequently, the displayed image will be unnatural.
On the other hand, in the present invention, since the decoding process is performed only in accordance with a clock with a fixed frequency, the synchronous control for outputting the frame image due to the coincidence of the PTS and the STC is not performed as described above. As a result, for example, missing or overlapping output images due to failures such as discontinuity of PTS do not occur, and it is possible to prevent the quality of displayed images from being deteriorated.

  Hereinafter, embodiments of the present invention will be described. In this embodiment, a decoder that decodes a video signal encoded by the MPEG method is taken as an example. In this embodiment, it is assumed that this decoder is provided in a digital satellite broadcast receiver.

<First Embodiment>
First, the first embodiment will be described.
FIG. 1 shows a configuration of a main part of a digital satellite broadcast receiver 1 as the present embodiment.
As is well known, in digital satellite broadcasting, a digital broadcast signal is output from a communication satellite or a broadcast satellite. The parabolic antenna 7 receives a broadcast signal from the satellite, converts it to a predetermined high frequency signal by a built-in LNB (Low Noise Block Down Converter), and supplies the signal to the digital satellite broadcast receiver 1.

In the digital satellite broadcast receiver 1, a reception signal received by the parabolic antenna 7 and converted into a predetermined frequency is input by the front end unit 2.
The front end unit 2 receives a carrier (reception frequency) determined by the setting signal based on a setting signal in which transmission specifications and the like are set from the system controller 6, and for example, a Viterbi demodulation process or an error correction process To obtain TS (Transport Stream).

As is well known, the TS according to the digital satellite broadcast standard is compressed data obtained by compressing video signals and audio signals of a plurality of programs (programs) by, for example, MPEG2 (Moving Picture Experts Group Layer2) method, and various additional information. Are multiplexed. The compressed data obtained by compressing the video signal and the audio signal is multiplexed as an ES (Elementary Stream). Further, as additional information to be inserted by the broadcast side, PSI (Program Specific Information) for storing tables such as PAT (Program Association Table), PMT (Program Map Table), and SI (Service Information: Program Sequence Information) ) Etc.
Also, a PTS (Presentation Time Stamp) is added for each video signal corresponding to one frame when an image is displayed, and presents the timing for outputting the video signal for one frame.
The information is multiplexed by forming a TS with a 188-byte transport stream packet (TS packet) and storing the ES and various additional information in the TS packet. Is called.
The TS obtained at the front end unit 2 is supplied to the descrambler 3.

  Further, the front end unit 2 acquires a PSI (Program Specific Information) packet from the TS, updates the channel selection information, obtains a component PID (Program ID) of each channel in the TS, For example, it is transmitted to the system controller 6. The system controller 6 uses the acquired PID for received signal processing.

In the descrambler 3, descramble key data prepared in advance is received from the system controller 6, and a PID is set by the system controller 6. Then, the descrambling process is executed based on the descrambling key data and the PID.
For confirmation, the TS output from the descrambler 3 may have multiple programs ES multiplexed, and additional information such as PSI is also removed. Without being multiplexed.

  The demultiplexer 4 separates necessary TS packets from the TS supplied from the descrambler 3 in accordance with the filter conditions set by the system controller 6. Thus, for example, the demultiplexer 4 obtains a TS packet of a video signal compressed by the MPEG2 system and a TS packet of audio data compressed by the MPEG2 system as TS packets for one target program. Become. The compressed video signal and the compressed audio data obtained in this way are output to the MPEG decoder 5.

The individual packets of compressed video / audio data separated by the demultiplexer 4 are input to the MPEG decoder 5 in a format called PES (Packetized Elementary Stream).
In addition, the filter condition is set such that, for example, the demultiplexer 4 extracts PAT, PMT, and the like included in the TS and transfers them to the system controller 6. Then, the system controller 6 sets filter conditions for the demultiplexer 4 based on the information content described in the transferred PAT, PMT, and the like.

In the MPEG decoder 5, a video decoder that decodes (decompresses) a compressed video signal according to the MPEG2 format, and an audio decoder that decodes compressed audio data according to the MPEG2 format so as to be synchronized with the video signal output. It has.
Then, the input compressed video signal is decoded by a video decoder and output as a video signal.
Also, the input compressed audio data is decoded by an audio decoder and output as audio data.
In this case, the decoded video signal is subjected to necessary signal processing so as to properly display an image in accordance with a predetermined television system such as the NTSC system, and is converted into an analog video signal. It can also be output.
The decoded audio data can be output as an analog audio signal by performing D / A conversion, for example.

  As described above, the digital satellite broadcast receiver 1 according to the present embodiment can output the video signal and the audio signal from the broadcast signal received by the parabolic antenna 7 by the basic configuration as described above. Has been.

  By the way, in this digital satellite broadcasting system, the system clock frequency for encoding on the MPEG encoder (encoding device) side is defined as 27 MHz. However, this frequency changes within a range of about ± 10 ppm because, for example, the MPEG encoder is different for each station that transmits a broadcast signal or each time the relay is switched even in the same station. Along with this, the PCR superimposed on the broadcast signal also changes.

  In the conventional digital satellite broadcast receiver, as described with reference to FIG. 12, for example, by providing a voltage variable type PLL circuit, a system clock coinciding with the MPEG encoder side is generated. The encoding process is executed based on the system clock. Thereby, for example, the error of the system clock as described above is absorbed.

  However, the PLL circuit as described above is generally expensive, and it is difficult to obtain a single chip because of the need for external parts. Miniaturization has been hindered.

  Therefore, in this embodiment, instead of using an expensive voltage variable PLL circuit as described above, a system clock is obtained using a fixed clock generator, and a video signal is decoded using this fixed system clock. I decided to make it run.

However, as described above, the clock frequency on the broadcast encoder side (encoding device side) is not strictly 27 MHz, and there is, for example, an error of about ± 10 ppm as described above.
On the other hand, in the present embodiment, the video signal decoding process is executed based on the fixed clock as described above.
This means that in this embodiment, the decoding timing of the video signal is not synchronized with the clock frequency requested by the emission side.
Actually, the error of ± 10 ppm with respect to the clock frequency of 27 MHz is very small. Therefore, in a relatively short time, there is a large error between the clock timing on the encoder side and the decoding timing of the image. Does not occur. However, when synchronization is not achieved, for example, when viewed for a long time of about 1 hour or more, the error may be expanded to about 1 frame image, for example. Therefore, it becomes necessary to adjust such an error.

  Therefore, the present embodiment is also configured to adjust the image output timing to an appropriate one in response to the difference in timing between the received clock frequency on the encoder side and the decoder side. It is. Hereinafter, a configuration for this purpose will be described.

The MPEG decoder 5 as the present embodiment capable of realizing the timing adjustment as described above is configured as shown in the block diagram of FIG.
As shown in the figure, the MPEG decoder 5 as the first embodiment includes a fixed clock generator 11, an STC (System Time Clock) counter 12, a PTS demodulator 13, a delay memory 14, a decoder unit 15, and an output timing. An adjustment portion 17 is formed.
In this figure, only the main part relating to the video signal demodulation operation is mainly shown, and the other parts are omitted.

First, in this figure, a fixed clock generator 11 is a part that includes a crystal oscillator, for example, and generates a clock fixed at a predetermined frequency. The clock frequency here is 27 MHz, which is defined as the system clock frequency on the decoder side. The clock generated in this way is supplied to the required units as the system clock of the MPEG decoder 5 as shown in the figure. A decoder unit 15 to be described later demodulates a video signal encoded and modulated by the MPEG2 system at a timing according to the system clock.
That is, in the present embodiment, as described above, the PLL circuit for generating the system clock using the PRC is omitted, and a fixed frequency system clock is obtained by the fixed clock generator 11 instead. . For this reason, no PRC is input to the MPEG decoder 5 in this embodiment.

The STC counter 12 receives a system clock generated by the fixed clock generator 11 as shown in the figure, and counts this to generate a value as an STC. The STC is essentially reference synchronization information that is a reference for the demodulation processing timing of encoded data, and has a timing that matches the system clock on the encoder side. However, since the STC in this case is generated by counting a fixed system clock at 27 MHz, it has a timing coincident with the fixed system clock in the MPEG decoder 5. This means that the reference synchronization information corresponds only to the decoding processing timing of the decoder unit 15 operating with a fixed system clock.
The STC value generated by the STC counter 12 is supplied to the output timing adjustment unit 17 as shown.

The PTS demodulator 13 receives the PTS supplied from the demultiplexer 4 described with reference to FIG. 1 and demodulates it to obtain the PTS value.
As described above, the PTS is information generated by the MPEG encoder and multiplexed on the stream data. This PTS is also called time management information for reproduction output, and functions as information for designating reproduction output timing. With this PTS, for example, the reproduction output timing for each frame image or for each access unit of encoded data is designated.
The value of this PTS is supplied to the output timing adjustment unit 17. Further, this PTS value is also supplied to the STC counter 12 as an initialization value when the count value of the STC counter 12 is initialized.

  The delay memory 14 receives an encoded video signal supplied from the demultiplexer 4 and buffers (temporarily accumulates) the encoded video signal. The delay memory 14 is provided to guarantee the decoding processing time in the decoder unit 15 at the subsequent stage. . The video signal accumulated in this way is supplied to the decoder unit 15.

The decoder unit 15 receives the video signal read from the delay memory 14 according to the fixed frequency system clock generated by the fixed clock generator 11 and performs a demodulation process. Then, the video signal as time-series data obtained by demodulation is reproduced and output as a video output.
The decoder unit 15 adjusts the output timing of the video signal to be decoded and output in accordance with the Repeat instruction signal and the Skip instruction signal supplied from the output timing adjusting unit 17 described below. Will be described later.

  The output timing adjustment unit 17 compares the count value supplied from the STC counter 12 with the value of the PTS supplied from the PTS demodulation unit 13, and detects an error between these values. Based on the detection result, the repeat instruction signal and the skip instruction signal are output. Thereby, as described later, the output timing of the video signal is adjusted, and as a result, synchronization with the output timing of the video signal designated by the encoder side is obtained.

The internal configuration of the output timing adjustment unit 17 for realizing the above operation is as shown in FIG.
As shown in the figure, the output timing adjustment unit 17 includes an error detection unit 31, a Repeat threshold 32, a Skip threshold 33, a comparator 34, and a comparator 35.
First, the error detector 31 detects an error between the supplied PTS value and the count value of the STC counter 12. As this detection method, for example, the STC count value is subtracted from the PTS value to obtain the value.
Then, a value obtained by subtracting the STC count value from this PTS value (value of “PTS-STC”) is supplied to the comparator 34 and the comparator 35.

The comparator 34 compares the “PTS-STC” value supplied in this way with the Repeat threshold supplied from the Repeat threshold 32. Here, as the Repeat threshold 32, a negative value is set. For example, when the output timing is adjusted based on the timing shift amount for one frame as described later, a Repeat threshold corresponding to a time width of about −30 ms is set, for example.
The comparator 34 supplies a repeat instruction signal to the decoder unit 15 when the value of “PTS-STC” is smaller than the repeat threshold. That is, for example, assuming that the Repeat threshold 32 is −30 ms, the Repeat instruction when the value of “PTS-STC” becomes a number smaller than −30 ms (when the absolute value is larger than 30 msec). Output a signal.

The comparator 35 compares the value of “PTS-STC” supplied from the error detection unit 31 with the Skip threshold supplied from the Skip threshold 33. In this case, a positive threshold value is set as the Skip threshold value. When the output timing is adjusted based on the timing shift amount for one frame, for example, a positive number corresponding to about +30 ms corresponding to one frame period is set.
Then, as the value of “PTS-STC” becomes larger than the Skip threshold, a Skip instruction signal is supplied to the decoder unit 15 as shown in the figure.

Here, the case where the Repeat instruction signal is output is a case where the PTS is smaller than the STC by the Repeat threshold value.
As can be understood from the above description, the PTS can be regarded as information specifying the reproduction output timing of the decoder specified by the encoder side. On the other hand, the STC according to the present embodiment indicates the actual reproduction output timing in the decoder unit 15 that performs the decoding process using the fixed-frequency system clock.
Therefore, when the PTS is smaller than the STC by the repeat threshold and the repeat instruction signal is output, the reproduction output timing of the video signal decoded by the decoder unit 15 with the fixed system clock is This means that the playback output timing specified by the system clock is advanced by the time corresponding to the Repeat threshold.
On the other hand, the case where the Skip instruction signal is output is a case where the PTS is larger than the STC by the Skip threshold, so that the output timing of the video signal decoded by the decoder unit 15 is This means that the reproduction output timing specified by the side is delayed by a time corresponding to the Skip threshold.

In the MPEG decoder 5 of the present embodiment configured as described above, for example, the following operation is obtained.
As described above, in the present embodiment, the decoding timing by the decoder unit 15 is not synchronized with the clock frequency on the encoder side. For this reason, as the decoding process is executed, the difference between the PTS value superimposed on the broadcast signal and the STC count value counted by the STC counter 11 increases with time. there is a possibility.
Here, it is assumed that the above-described deviation is detected by the output timing adjustment unit 17 and exceeds the Repeat threshold value or the Skip threshold value. In response to this, a Repeat instruction signal or a Skip instruction signal for adjusting the video signal output is supplied to the decoder unit 15.

Here, as described above, the decoder unit 15 adjusts the timing of the video signal reproduction output based on the Repeat instruction signal and the Skip instruction signal. In this embodiment, two examples of the timing adjustment operation are given.
First, as a first example, an output video signal is adjusted in units of frame images. In this case, the reproduction output of the video signal corresponding to one frame is repeated (repeat), or the next frame is reproduced and output without performing the reproduction output of the video signal corresponding to one frame (skip). To be done.
As a second example, the video signal reproduction output repeat / skip as described above is performed in units of horizontal lines in one frame image.

First, the output timing adjustment operation of the decoder unit 15 based on the Repeat / Skip instruction signal as a first example will be described with reference to FIG.
FIG. 4A schematically shows the reproduction output timing for the video signal after the decoding process when it is assumed that the video signal is reproduced and output at a timing according to the system clock on the encoder side. . That is, the decoding process should be executed by the decoder unit 15 at this timing.

On the other hand, FIG. 4B shows a state in which the playback output timing of the video signal after the decoding processing by the decoder unit 15 is ahead of the timing specified by the encoder system clock. In addition, as this advanced state, a state in which it is advanced by almost one frame is shown.
FIG. 4C shows a state where the playback output timing of the video signal after the decoding processing by the decoder unit 15 is delayed by about one frame from the timing according to the system clock on the encoder side.
Each rectangular frame shown in the figure represents a display image for one frame, and the number shown in the frame indicates the output order of field images for convenience.

  For example, when the decoding processing timing by the decoder unit 15 is advanced as shown in FIG. 4B with respect to the appropriate timing shown in FIG. 4A, the reproduction output timing is gradually increased as shown in FIG. Finally, for example, the frame “6” is reproduced and output at a timing at which the frame “5” should be reproduced and output. That is, the state is advanced by about one frame from the reproduction output timing of the video signal based on the system clock.

In this case, in the output timing adjustment unit 17 of FIG. 3, it is determined by the comparator 34 that the value of “PTS-STC” calculated by the error detection unit 31 is smaller than the Repeat threshold (= about −30 ms), and the decoder The repeat instruction signal is supplied to the unit 15.
Then, the decoder unit 15 repeats (repeatedly reproduces and outputs) the video signal for one frame to be reproduced and output based on the Repeat instruction signal supplied in this manner.
That is, as shown in FIG. 4B, the frame “6” is repeatedly output, and as a result, the frame “6” can be displayed at an appropriate timing to display the frame “6”. It becomes possible.

  When the decoding processing timing by the decoder unit 15 is delayed with respect to the appropriate timing shown in FIG. 4A, the reproduction output timing is gradually increased as shown in FIG. There is a delay with respect to the timing of a), and finally, for example, a state in which frame “4” is reproduced and output at a timing at which frame “5” should be reproduced and output is obtained. That is, a state delayed by about one frame from the reproduction output timing based on the system clock on the encoder side is obtained.

In this case, the output timing adjustment unit 17 determines that the value of “PTS-STC” calculated by the error detection unit 31 is larger than the Skip threshold (= about +30 ms) by the comparator 35, and the decoder unit 15 A Skip instruction signal is supplied.
Then, the decoder unit 15 skips and outputs the video signal for one frame to be reproduced and output in accordance with this.
That is, as shown in FIG. 4C, the frame “5” is skipped, so that the frame “6” can be displayed at the timing when the frame “6” should be displayed.

  In this way, when the system clock and the supplied PTS value deviate from each other, the decoder unit 15 decodes and outputs the result by matching the timing at which the predetermined frame should be displayed on the way. The video signal can be displayed at an appropriate timing.

  In FIG. 4, in order to make the explanation easy to understand, the timing shown in FIGS. 4B and 4C differs from the appropriate timing shown in FIG. It is in a state that has occurred. However, as described above, the actual system clock frequency error on the encoder side is about ± 10 ppm with respect to 27 MHz. For this reason, an error for one frame as described with reference to FIG. 4 occurs only once per hour, for example. Therefore, the opportunity to execute repeat output or skip output in units of frame images as described with reference to FIG. 4 is also about once per hour. In other words, since the display image is not frequently repeated / skip output in units of frames, the quality of the displayed image is not particularly reduced.

Next, the reproduction output timing adjustment operation of the decoder unit 15 as the second example will be described with reference to FIG. 5A, 5B, and 5C each show an image for one frame in the form of a set of horizontal lines.
In performing this output timing adjustment operation, it is not always necessary to set a threshold corresponding to the time for one frame as the Repeat threshold 32 and the Skip threshold 33, but here, as in the previous case It is assumed that a threshold value corresponding to the time for one frame is set.

Here, for example, it is assumed that the value of “PTS-STC” is within the range of the Repeat threshold 32 and the Skip threshold 33 as the amount of deviation between the timing based on the system clock on the encoder side and the decoding processing timing by the decoder unit 15. In such a state, it is considered that almost normal reproduction output timing is obtained.
In this state, as shown in FIG. 5A, the horizontal lines forming the frame image decoded and output by the decoder unit 15 are reproduced and output without excess or deficiency.

On the other hand, it is assumed that the decoding processing timing by the decoder unit 15 has advanced beyond the allowable range as a deviation amount between the timing based on the system clock on the encoder side and the decoding processing timing by the decoder unit 15. That is, the decoding processing timing by the decoder unit 15 is advanced by a time corresponding to approximately one frame with respect to the timing based on the system clock on the encoder side.
In this case, in the output timing adjustment unit 17 of FIG. 3, the value of “PTS-STC” calculated by the error detection unit 31 is smaller than the Repeat threshold, so that the repeat instruction signal is sent from the comparator 34 to the decoder unit 15. Will be supplied.

In this case, the decoder unit 15 is formed so that one horizontal line is added to the video signal for one frame image to be reproduced and output from the timing at which the Repeat instruction signal is output. That is, as shown in the figure, for example, one extra horizontal line A is inserted (repeated) with respect to the last line in the video signal corresponding to a normal display image.
Then, the output of the video signal as the frame image with the horizontal line A added in this way is continued. As a result, the video signal output timing from the decoder unit 15 is gradually delayed, and can be adjusted to an appropriate timing at a certain time. When an appropriate output timing from the decoder unit 15 is obtained, a normal video signal is output as shown in FIG.

  As described above, the video signal in units of lines added by the decoder unit 15 may be line data as an actual image or dummy line data.

  On the other hand, it is assumed that the decoding processing timing by the decoder unit 15 is delayed by approximately one frame beyond the allowable range as a deviation amount between the timing based on the system clock on the encoder side and the decoding processing timing by the decoder unit 15. In this case, since the value of “PTS-STC” by the error detection unit 31 exceeds the Skip threshold value, a Skip instruction signal is supplied from the comparator 35 to the decoder unit 15.

When the Skip instruction signal is obtained in this way, the decoder unit 15 in the video signal for one frame to be decoded and reproduced and output, as shown by a broken line in FIG. The horizontal line is omitted (skip).
Also in this case, the reproduction output of the video signal as the frame image from which the final horizontal line is deleted as described above is continued, and the video signal output timing from the decoder unit 15 is gradually advanced. Then, if it is assumed that it has caught up to an appropriate timing at a certain time, it is returned to the normal video signal reproduction output shown in FIG.

For example, when performing repeat / skip in units of frame images as in the first example, even if this operation is not performed frequently, the frame images will overlap or fall. In particular, when a fast moving image is displayed, it may become unnatural.
On the other hand, when repeating / skipping the horizontal line of the video signal as in the second example, if the final line is repeated / skip, the horizontal line to be repeated / skipped is For example, since the display image is an overscanned region, the image is not visually disturbed.

<Second Embodiment>
The MPEG decoder 5 as the first embodiment described above detects a shift in image output timing with respect to the system clock by comparing the PTS value superimposed on the received broadcast signal with the STC count value. It is composed.
On the other hand, in the second embodiment, instead of this detection method, a shift in image output timing with respect to the system clock is detected based on the amount of codes buffered in the delay memory 14. is there.

FIG. 6 is a diagram for conceptually explaining such a detection method as the second embodiment.
In this figure, as conceptually showing data writing / reading with respect to the delay memory 14, codes (video signals) sequentially supplied from the demultiplexer 4 are written from above and buffered (temporarily accumulated). The state in which the buffered code is read from below and output to the decoder unit 15 is shown.

Here, for example, it is assumed that the amount of codes buffered in the delay memory 14 has decreased. In this case, the timing of output to the decoder unit 15 is more advanced than the code supply timing to the delay memory 14. Therefore, the decoder unit 15 outputs a video signal at a timing advanced from an appropriate timing.
On the other hand, when the amount of code buffered in the delay memory 14 is increasing, the video signal output timing by the decoder unit 15 is delayed.

  Therefore, by monitoring the increase or decrease in the amount of code buffered in the delay memory 14 in this way, the playback output timing of the video signal of the decoder unit 15 is compared with the playback output timing specified by the encoder side. It is possible to detect whether the vehicle is moving forward or late.

Therefore, in the second embodiment, as shown in the figure, two threshold values of “Near Full” and “Near Empty” are provided for this code amount, and the video signal reproduction output by the decoder unit 15 is at an appropriate timing. In this case, it is detected whether or not it is performed in step (b).
That is, if the code amount falls below the “Near Empty” threshold, it is considered that the video signal output timing of the decoder unit 15 has advanced beyond the allowable range. If the “Near Full” threshold value is exceeded, the video signal playback output timing is regarded as being delayed beyond the allowable range.

  In addition, when the amount of codes buffered in the delay memory 14 is less than “Near Empty”, a Repeat instruction signal is supplied to the decoder unit 15 and exceeds “Near Full”. In this case, a Skip instruction signal is supplied. As a result, as in the first embodiment, it is possible to realize an operation for adjusting the reproduction output timing of the video signal to an appropriate timing.

An internal configuration of the MPEG decoder 5 as the second embodiment for this purpose is shown in FIG.
In this figure, parts already described in the first embodiment are denoted by the same reference numerals and description thereof is omitted. Further, the PTS demodulated by the PTS demodulator 13 shown in this figure is not used for adjusting the reproduction output timing in the second embodiment. However, it is used for image / audio synchronization control of the decoded video signal and audio signal, not shown here. The PTS is used for the image / audio synchronization control as well in the first embodiment.

First, in the MPEG decoder 5 as the second embodiment shown in FIG. 8, the delay memory 14 is actually configured to operate as a ring buffer as shown in FIG. .
As is well known, the ring buffer is configured such that the write pointer “Write Pointer” (WP) circulates the address of the same memory area and performs addressing to write data. Note that when writing is to be performed on an already written area, the write pointer WP is shifted so as to be overwritten. At the same time, the written data is read while shifting the read pointer “Read Pointer” (RP) so as to follow the write pointer WP.
Therefore, in order to compare the code amount buffered in the delay memory 14 with the “Near Full” threshold value and also with the “Near Empty” threshold value, in practice, the read amount corresponding to the value of the write pointer WP is read. This is based on the value of the address difference (WP-RP) of the pointer RP.
That is, a Skip threshold value corresponding to the address difference (WP-RP) value corresponding to the “Near Full” threshold value is set, and a Repeat threshold value corresponding to the address difference (WP-RP) value corresponding to the “Near Empty” threshold value. To be set. In addition, the current address difference (WP-RP) is compared with the above Skip threshold and Repeat threshold. Such processing is executed by the code amount detection unit 20 described below.

  In the MPEG decoder 5 as the second embodiment, a code amount detection unit 20 is provided as shown in FIG. The internal configuration of the code amount detection unit 20 is as shown in FIG.

As shown in FIG. 9, the code amount detection unit 20 includes a subtracter 41, a Repeat threshold 42, a Skip threshold 43, a comparator 44, and a comparator 45.
First, the value of the write address WP and the value of the read address RP supplied from the delay memory 14 are input to the subtractor 41 as shown in the figure. Then, the subtractor 41 subtracts the value of the read address RP from the value of the address WP, and supplies this address difference value “WP−RP” to the comparator 44 and the comparator 45.

The comparator 44 compares the value of “WP-RP” supplied in this way with the repeat threshold supplied from the repeat threshold 42, and the value of “WP-RP” exceeds the repeat threshold. Then, a Repeat instruction signal is supplied to the decoder unit 15.
The comparator 45 compares the “WP-RP” value supplied from the subtractor 41 with the Skip threshold value supplied from the Skip threshold value 43, and responds when the “WP-RP” value falls below the Skip threshold value. Then, the Skip instruction signal is supplied to the decoder unit 15.

As the output timing adjustment operation of the decoder unit 15 based on the Repeat / Skip instruction signal in the second embodiment, an operation equivalent to that in the first embodiment is obtained. That is, adjustment is performed by repeat / skip output (first example) in units of one frame or repeat / skip output (second example) of one horizontal line.
In this case, if the output timing adjustment of the decoder unit 15 based on the Repeat / Skip instruction signal is the same as that in the first embodiment, the Repeat threshold is set to a decoding process for one frame. In accordance with the progress of the code, it may be determined based on the code amount stored in the delay memory 14. Further, the Skip threshold may be determined based on the amount of code stored in the delay memory 14 in accordance with the delay of decoding processing for one frame.

As can be understood from the above description, in each of the above embodiments, the fixed clock generator 11 is provided so as to generate a system clock having a fixed frequency. The decoding process of the decoder unit 15 is executed at a timing according to this fixed clock.
And after having comprised in this way, in 1st Embodiment, the output timing adjustment part 17 is provided, and the value of video signal output timing is compared by comparing the value of PTS and STC count value. Is to be detected.
In the second embodiment, the code amount detection unit 20 is provided to detect the code amount buffered in the delay memory 14, so that the playback output timing of the video signal in the decoder unit 15 is appropriate. The detection of whether or not is performed.

  Further, the output timing adjusting unit 17 or the code amount detecting unit 20 determines that the repeat instruction signal is delayed when it is determined that the reproduction output timing is ahead of a predetermined value based on this detection. In this case, the Skip instruction signal is supplied to the decoder unit 15 so that the playback output timing of the video signal by the decoder unit 15 is adjusted.

As described above, in each embodiment, when a deviation out of the allowable range occurs with respect to the reproduction output timing of the video signal in the decoder unit 15, an operation for adjusting the deviation is obtained each time.
As a result, even in the MPEG decoder 5 of each embodiment, it is possible to omit the PLL circuit that has been conventionally required for reproducing the reference clock (PCR) superimposed on the broadcast signal.

<Modification: Configuration by software processing>
By the way, in the description as each of the above embodiments, the operations of the output timing adjustment unit 17 and the code amount detection unit 20 are realized by a hardware configuration. However, the operations of the output timing adjustment unit 17 and the code amount detection unit 20 can be realized by software processing. In practice, the operations of the output timing adjustment unit 17 and the code amount detection unit 20 are also performed. There are many opportunities to configure the system by software processing.
Therefore, the case where the operations as the output timing adjustment unit 17 and the code amount detection unit 20 are realized by software processing will be described.

  In this way, when the operations of the output timing adjustment unit 17 and the code amount detection unit 20 are configured by software processing, in the present embodiment, the processing operation shown in FIGS. 10 and 11 is executed by the controller 6. To.

First, the processing operation of the controller 6 corresponding to the operation of the output timing adjustment unit 17 in the first embodiment is as shown in FIG.
In order to realize the processing operation of the controller 6 in this figure, the STC count value of the STC counter 12 shown in FIG. 2 and the PTS value demodulated by the PTS demodulator 13 are supplied to the controller 6. At the same time, it is assumed that a Repeat threshold and a Skip threshold are set by the software.

First, in step S101 shown in the figure, the controller 6 recognizes the STC count value and the PTS value supplied from the STC counter 12 and the PTS demodulator 13.
In subsequent step S102, based on this recognition, the value of “PTS-STC” is obtained, and it is determined whether or not this value is smaller than the Repeat threshold.

If it is determined in step S102 that the value of “PTS-STC” is smaller than the Repeat threshold value, the process proceeds to step S104 as shown in the figure, and a Repeat instruction signal is supplied to the decoder unit 15. When this process is executed, for example, the process once returns to the main routine, and the processing operation shown in this figure is repeated from step S101.
If it is determined in step S102 that the value of “PTS-STC” is larger than the Repeat threshold value, the process proceeds to step S103.

In step S103, the value of “PTS-STC” is compared with the Skip threshold value, and it is determined whether or not the value of “PTS-STC” is larger than the Skip threshold value.
If it is determined that the value of “PTS-STC” is larger, the process proceeds to step S105, an operation of supplying a Skip instruction signal to the decoder unit 15 is executed, and the processing operation shown in this figure is repeated from step S101. In Step S103, if it is determined that the value of “PTS-STC” is smaller than the Skip threshold, the processing operation shown in this figure is repeated from Step S101.

  Further, the processing operation of the controller 6 corresponding to the code amount detection unit 20 in the second embodiment is as shown in FIG. In this case as well, it is assumed that a Repeat threshold value and a Skip threshold value are set in the controller 6. In this case, it is assumed that the controller 6 is configured to be supplied with the values of WP and RP generated in the delay memory 14.

First, as shown in the figure, the processing operation of the controller 6 in this case is to recognize the values of the current write address WP and read address RP in step S201.
In step S202, an address difference value “WP-RP” is obtained based on the write address WP and read address RP values recognized in step S201, and the address difference value “WP-RP” is obtained. "Is smaller than the Repeat threshold. If a positive determination result is obtained, the video signal reproduction output timing by the decoder unit 15 is ahead of the timing designated by the encoder. A Repeat instruction signal is output to the decoder unit 15.
On the other hand, if it is determined in step S203 that the address difference value “WP-RP” is larger than the Skip threshold value, the playback output timing of the video signal by the decoder unit 15 is delayed. Therefore, the skip instruction signal is output in step S205.
In this way, an operation similar to that of the code amount detection unit 20 described above is obtained.

In each embodiment, the digital satellite broadcast receiver 1 is described as an example of a device in which the MPEG decoder 5 is built. However, the present invention is not limited to this. For example, it may be built in another device such as a playback device that plays back media on which data encoded by the MPEG system is recorded.
In addition, the encoding method to which the present invention is applicable is not limited to the MPEG2 method, but may be another encoding method.

It is a block diagram which shows the example of an internal structure of the digital satellite broadcast receiver with which the data processing apparatus (MPEG decoder) as embodiment in this invention is incorporated. It is a block diagram which shows the example of an internal structure of the data processor as the 1st Embodiment of this invention. It is a block diagram which shows the internal structure of the output timing adjustment part with which a data processor is equipped. It is a figure explaining the timing adjustment (1st example) of a video signal output based on control of an output timing adjustment part. It is a figure explaining the timing adjustment (2nd example) of video signal output based on control of an output timing adjustment part. It is a figure which illustrates notionally the code amount detection method in the data processor as 2nd Embodiment. It is a conceptual diagram of a ring buffer. It is a block diagram which shows the internal structure of the data processor as 2nd Embodiment. It is a block diagram which shows the internal structure of a code amount detection part. It is a flowchart which shows the processing operation at the time of implement | achieving operation | movement of the output timing adjustment part shown in FIG. 3 by software. 10 is a flowchart showing a processing operation when the operation of the code amount detection unit shown in FIG. 9 is realized by software. It is a block diagram which shows the structure of the principal part inside the conventional data processor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Digital satellite broadcast receiver, 2 Front end part, 3 Descrambler, 4 Demultiplexer, 5 MPEG decoder, 6 System controller, 11 Fixed clock generator, 12 STC counter, 13 PTS demodulation part, 14 Delay memory, 15 Decoder part , 17 Output timing adjustment unit, 20 Code amount detection unit, 31 Error detection unit, 41 Subtractor, 32, 42 Repeat threshold, 33, 43 Skip threshold, 34, 35, 44, 45 Comparator

Claims (8)

Encoded video data in which a video signal is encoded, encoded audio data in which an audio signal is encoded, and the encoded video data and encoded audio data are demodulated to reproduce the video signal and the audio signal. A data processing device to which output time management information for specifying reproduction output timing at the time of
Clock generating means for generating a system clock with a fixed frequency;
Data storage means capable of temporarily storing the encoded video data;
Video demodulation means for demodulating the encoded video data read from the data storage means at a timing according to the system clock with the fixed frequency and reproducing and outputting a video signal;
Audio demodulation means for demodulating the encoded audio data and reproducing and outputting an audio signal;
The amount of encoded video data stored by the data storage means is compared with a predetermined threshold, and if the result of this comparison is that the amount of storage is less than or equal to a predetermined threshold, the video signal is Control means for controlling the video demodulation means so that the video signal is repeatedly reproduced and output in units and the video signal is skipped and reproduced in predetermined time units when the accumulated amount is equal to or greater than a predetermined threshold;
Data comprising: synchronous output means for synchronously outputting a video signal demodulated by the video demodulation means and an audio signal demodulated by the audio demodulation means based on the output time management information Processing equipment.   The data processing apparatus according to claim 1, wherein the predetermined time unit is a frame unit.   The data processing apparatus according to claim 1, wherein the predetermined time unit is a horizontal line unit. The control means includes
4. The data processing apparatus according to claim 3, wherein control is performed so that the horizontal line scanned in the overscan region is repeatedly reproduced and output, or skipping is performed. Encoded video data in which a video signal is encoded, encoded audio data in which an audio signal is encoded, and the encoded video data and encoded audio data are demodulated to reproduce the video signal and the audio signal. A data processing method in a data processing apparatus to which output time management information for specifying reproduction output timing is provided,
A clock generation process for generating a system clock with a fixed frequency;
A data storage process for temporarily storing the encoded video data in a memory area;
A video demodulation process for demodulating the encoded data read from the memory area at a timing according to the system clock with the fixed frequency to reproduce and output a video signal;
An audio demodulation process for demodulating the encoded audio data and reproducing and outputting an audio signal;
The amount of the encoded video data accumulated by the data accumulation process is compared with a predetermined threshold, and if the result of this comparison is that the amount of accumulation is less than the predetermined threshold, the video signal is Based on a control process for controlling the video signal to be skipped and reproduced in a predetermined time unit when the accumulated amount is equal to or greater than a predetermined threshold and the output time management information A data processing method comprising: synchronization processing for synchronously outputting a video signal obtained by demodulation by video demodulation processing and an audio signal obtained by demodulation by audio demodulation processing.   6. The data processing method according to claim 5, wherein the predetermined time unit is a frame unit.   6. The data processing method according to claim 5, wherein the predetermined time unit is a horizontal line unit. The above control process
The data processing method according to claim 7, wherein control is performed so that the horizontal line scanned in the overscan area is repeatedly reproduced and output, or skipping is performed.

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