JP2007235405A - Waveform improvement circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a waveform improvement circuit capable of coping with a high speed signal by optimizing a discharge timing of electric charges charged in a capacitor. <P>SOLUTION: In the waveform improvement circuit 1 for improving a waveform of a digital signal St transmitted to a signal line 4, when a level detection circuit 11A detects that a level of the signal St exceeds a prescribed value, a switch circuit 12A is conductive on the basis of an output voltage Vd, and a power supply voltage V<SB>B</SB>is applied to the capacitor 131 of a charging circuit 13A to charge up the capacitor 131. The capacitor 131 is discharged to the signal line 4 via a diode 141 of a discharge circuit 14A in a timing when the voltage level of the signal St is lower than the charging voltage Vc of the capacitor 131 to improve undershoot. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a waveform improving circuit for reducing undershoot generated in a signal waveform by discharging a charge of a capacitor to a signal line.

  With the development of integrated circuit technology, the speed of digital signals is increasing, and as a method for transmitting signals at high speed, there is a method for reducing the impedance of the output driver.

  However, in this method, the rate of current change is large, and signal distortion is likely to occur due to parasitic inductance generated in the transmission line. In addition, an LC circuit is formed by parasitic capacitance and parasitic inductance generated in the transmission path, and signal oscillation (ringing) occurs.

  As a measure for the above, a method of matching the input / output of a signal and the impedance of the transmission line is widely known. However, in order to actually match the impedance of the transmission line perfectly, as a result, useless power consumption is reduced. In other words, there is a drawback that it is necessary to design / manage advanced print patterns and is expensive.

  In order to improve these drawbacks, for example, an undershoot prevention circuit described in Patent Document 1 has been proposed.

In this undershoot prevention circuit, the cathode of the first diode is grounded, the cathode of the second diode is connected to the signal line, the anodes of the first and second diodes are connected to each other, and the first and second The anode of the diode is connected to the power source V _B via the resistor R, and the capacitor C is connected in parallel to the first diode. When the signal line becomes a negative voltage, the capacitor C starts to be charged. When the signal line becomes a positive voltage, the charge charged in the capacitor C is injected into the signal line, so that undershoot can be prevented.
Japanese Patent Laid-Open No. 1-112811

  In the conventional undershoot prevention circuit, when the signal speed is increased, the charging time for the capacitor C is naturally shortened, and it is necessary to complete predetermined charging in a short time. In order to complete charging in a short time, the resistance R needs to be a small value.

However, in the conventional undershoot prevention circuit, when simply the resistor R small, when the signal level is Low, with the discharge current from the capacitor C, through resistors R from the power supply V _B, to the signal line V _{B /} R (A ) Current flows in, and the ability of the driver to drive the signal line is limited, and there is a problem that it is not possible to cope with high speed.

  Further, simply increasing the drive capability increases the rate of current change at the time of signal switching, and signal distortion is likely to occur, which may have an adverse effect.

  Therefore, an object of the present invention is to provide a waveform improvement circuit that can optimize the discharge timing of the charge charged in the capacitor and can cope with a high-speed signal.

  In order to achieve the above object, one embodiment of the present invention provides the following waveform improvement circuit.

[1] In a waveform improvement circuit for improving the waveform of a digital signal transmitted to a signal line, charging means having a capacitor to be charged during a period when the level of the digital signal exceeds a predetermined value, and the level of the digital signal A waveform improving circuit comprising: a discharging circuit that discharges the charging charge of the capacitor from the charging means to the signal line at a timing lower than a charging voltage of the capacitor.

  According to the waveform improvement circuit having the above configuration, when the digital signal on the signal line reaches a predetermined level, charging to the capacitor is started by the charging means, and when the level of the digital signal drops below the charging voltage, By starting the discharge of the charge, the undershoot generated in the digital signal is corrected and the response to the high-speed signal is achieved.

[2] The charging unit includes a level detection circuit that outputs a drive voltage when the level of the digital signal exceeds a predetermined value, and a voltage for charging the capacitor based on the drive voltage from the level detection circuit. The waveform improving circuit according to [1], further comprising: a switch circuit that applies voltage. According to this configuration, the charging unit can be configured with a simple configuration.

[3] The level detection circuit includes a plurality of resistors connected in series between the signal line and ground, and outputs the output voltage from a voltage dividing point of the resistors. [2] The waveform improvement circuit described in 1. According to this configuration, the level detection circuit can be configured with only a resistor.

[4] The waveform improvement circuit according to [2], wherein the level detection circuit includes a buffer and outputs the output voltage to the switch circuit. According to this configuration, the level detection circuit can be configured with a simple configuration.

[5] The waveform improvement circuit according to [2], wherein the switch circuit includes a transistor or a MOSFET. According to this configuration, the switch circuit can be configured by one transistor or MOSFET.

[6] The waveform improvement circuit according to [1], wherein the discharge circuit includes a circuit element that establishes a one-way energization path from the capacitor toward the signal line. According to this configuration, the discharge timing can be determined only by the circuit elements.

[7] The waveform improvement circuit according to [6], wherein the circuit element includes a diode. According to this configuration, a readily available diode can be used for the circuit element.

[8] The waveform improving circuit according to [7], wherein the diode is a Schottky diode. According to this configuration, the forward voltage Vfd can be lowered by using a Schottky diode as the diode, and the potential correction effect when the potential of the signal line is lowered can be enhanced.

[9] The waveform improving circuit according to [2], wherein the capacitor is connected in series with a resistor that limits a current flowing through the switch circuit. According to this configuration, the rush current flowing through the capacitor due to the resistance can be reduced, so that the elements of the switch circuit can be protected.

[10] The waveform improvement circuit according to [2], wherein the discharge circuit includes a voltage limiting element that is connected in parallel to the capacitor and defines the charging voltage. According to this configuration, the voltage limiting element can limit the upper limit of the terminal voltage of the capacitor.

[11] The waveform improvement circuit according to [10], wherein the voltage limiting element is a Zener diode. According to this configuration, an excellent voltage limiting characteristic can be obtained by using a Zener diode as the voltage limiting element.

[12] The waveform improvement circuit according to [10], wherein the voltage limiting element includes one diode or a plurality of diodes connected in series with the same energization direction. According to this configuration, an inexpensive diode can be used for the voltage limiting element.

  According to the present invention, it is possible to obtain a waveform improvement circuit that optimizes the discharge timing of the charge charged in the capacitor and can cope with a high-speed signal.

[First Embodiment]
(Configuration of waveform improvement circuit)
FIG. 1 shows the basic configuration of a waveform improvement circuit according to a first embodiment of the present invention. The waveform improvement circuit 1 is connected to a signal line 4, and a transmission circuit 2 that transmits a digital signal and a reception circuit 3 that receives a signal from the transmission circuit 2 are connected to the signal line 4. ing.

The waveform improvement circuit 1 is connected between a level detection circuit 11A connected to the signal line 4, a switch circuit 12A having a control terminal connected to the level detection circuit 11A, and the power source V _B and the ground via the switch circuit 12A. Charging circuit 13A and a discharging circuit 14A connected between the output terminal of charging circuit 13A and signal line 4 are configured. Here, the level detection circuit 11A and the switch circuit 12 constitute a charging means.

(Detailed configuration of waveform improvement circuit)
FIG. 2 shows a detailed configuration of the waveform improvement circuit.

  The transmission circuit 2 includes a transmission side driver 20 and outputs a digital signal to the signal line 4. The reception circuit 3 includes a reception side driver 30 and receives a signal from the transmission circuit 2 via the signal line 4.

  The level detection circuit 11A includes resistors 111 and 112 connected in series and connected between the signal line 4 and the ground, and a connection point of the resistors 111 and 112 is an output terminal that outputs an output voltage (drive voltage) Vd. It has become. The resistance ratio (= {R2 / (R1 + R2)}) so that an “H” level output voltage Vd for driving the switch circuit 12A is output when the voltage of the signal St on the signal line 4 is equal to or higher than a predetermined threshold voltage. Is set.

Switching circuit 12A is made of transistor 121 to a switching operation, based the control terminal is connected to the connection point of the level detection circuit 11, the collector is connected to the power supply voltage V _B, the emitter is connected to a charging circuit 13A Has been.

  The charging circuit 13A includes a capacitor 131 having a predetermined capacitance, one end of which is connected to the emitter of the transistor 121 and the other end connected to the ground.

  The discharge circuit 14 </ b> A includes a diode 141 as a circuit element, the anode thereof being connected to the high potential side of the capacitor 131, and the cathode being connected to the signal line 4.

(Operation of waveform improvement circuit)
FIG. 3 shows an operation waveform of each part of the waveform improvement circuit. The operation of the waveform improvement circuit 1 will be described below with reference to FIGS.

  The transmission side driver 20 of the transmission circuit 2 transmits a digital signal St to the reception circuit 3 via the signal line 4 as shown in FIG. As shown in FIG. 3A, this signal St generates, for example, an overshoot OS and an undershoot US due to a combination of a “0” level (for example, 0V) and a “1” level (for example, + 5V). Waveform.

  The signal St transmitted to the signal line 4 is applied to the level detection circuit 11A, divided by the resistors 111 (R1) and 112 (R2), and is output from the level detection circuit 11A as shown in FIG. Output voltage Vd is output. The output voltage Vd becomes “H” level when the transistor 121 of the switch circuit 12A is turned on when the voltage Vs of the signal St on the signal line 4 is equal to or higher than a threshold voltage (for example, 2V) Vt.

Therefore, when the voltage Vs of the signal St is more than 2V, as shown in (c) of FIG. 3, the transistor 121 is turned on, for example, the power supply voltage _{V B} of + 5V is applied to the capacitor 131 through the transistor 121, the charge Is started. The power supply voltage V _B has been set to a voltage to optimize the charging voltage of the charging circuit 13A, or may be shared with the power source for operating the other electronic circuitry.

The charging circuit 13A is charged with the power supply voltage V _B as shown in FIG. 3D while the transistor 121 is on, and the terminal voltage of the capacitor 131 is approximately the power supply voltage V V until the transistor 121 is turned off. The charging voltage Vc becomes a DC voltage equal to _B.

When the signal St on the signal line 4 becomes “L” level, the output voltage Vd of the level detection circuit 11A becomes “L” level, thereby turning off the transistor 121 and applying the power supply voltage V _B to the capacitor 131. finish.

  The charging voltage Vc of the capacitor 131 is applied to the discharging circuit 14A. Since the diode 141 of the discharging circuit 14A has a predetermined forward voltage Vfd, (charging voltage Vc−forward voltage Vfd ≧ voltage of signal St When Vs) is established, the electric charge of the capacitor 131 is discharged to the signal line 4. That is, the charging voltage Vc of the capacitor 131 has a waveform as shown in FIG. 3D, and the discharging voltage Vo of the discharging circuit 14A is output and applied to the signal line 4 as shown in FIG. The undershoot US is improved by correcting the voltage Vs of the signal St of the signal line 4 by (charging voltage Vc−forward voltage Vfd).

  The lower the forward voltage Vfd, the higher the waveform improving effect of the diode 141 when the potential of the signal line 4 is lowered. Therefore, it is desirable to use a diode having a low forward voltage Vfd (for example, 0.55 V), a so-called Schottky diode, as the diode 141.

Note that when the voltage level of the signal St is, for example, “L” level of less than 2V, that is, the potential of the signal line 4 is “L” level, the transistor 121 is turned off and the charging circuit 13A is not charged. , is not a voltage is applied by the signal line 4 to the supply voltage V _B. For this reason, a situation in which an excessive sink current flows to the transmission side driver 20 does not occur.

(Effects of the first embodiment)
According to the first embodiment, the following effects are obtained.
(A) By charging the capacitor 131 of the charging circuit 13A at the timing when the voltage level of the signal St of the signal line 4 is “H” level, it is possible to cope with a high-speed signal.
(B) Since the capacitor 131 can be charged without using a current limiting series resistor required by a circuit, the capacitor 131 can be charged in a short time, thereby handling a high-speed signal. be able to.
(C) When the voltage level of the signal St of the signal line 4 is reduced by using a Schottky diode or the like having a low forward voltage Vfd, the diode 141 is compared to using a diode having a high forward voltage Vfd. The waveform improvement effect can be enhanced.

[Second Embodiment]
FIG. 4 shows a waveform improvement circuit according to the second embodiment of the present invention. In this embodiment, the charging circuit 13B is configured by adding a current limiting resistor 132 between the transistor 121 and the capacitor 131 in the configuration of FIG. 2 of the first embodiment. The configuration is the same as in the first embodiment.

(Operation of waveform improvement circuit)
Next, the operation of the waveform improvement circuit 1 according to the second embodiment will be described. The transmission circuit 2 transmits a digital signal St to the reception circuit 3 via the signal line 4. The signal St is applied to the level detection circuit 11A, divided by resistors 111 (R1) and 112 (R2), and the output voltage Vd is output from the level detection circuit 11A. This output voltage Vd becomes “H” level when the voltage Vs of the signal St transmitted on the signal line 4 is equal to or higher than the threshold voltage Vt, thereby turning on the transistor 121 of the switch circuit 12A, and the capacitor of the charging circuit 13B. Charging 131 is started.

  At this time, as shown in FIG. 3D, a voltage is applied to the capacitor 131 having almost no electric charge, so that the transistor 121 is temporarily short-circuited on the load side. In this embodiment, the resistor 132 connected to the emitter of the transistor 121 limits the conduction current, so that the current flowing between the collector and the emitter of the transistor 121 is limited. An excessive current is prevented from flowing through the transistor 121.

The charging circuit 13B is charged while the transistor 121 is on. When the signal St on the signal line 4 becomes “L” level, the output voltage Vd of the level detection circuit 11A becomes “L” level, thereby turning off the transistor 121 and applying the power supply voltage V _B to the capacitor 131. finish.

  The charging voltage Vc of the capacitor 131 is applied to the discharging circuit 14A, and the diode 141 of the discharging circuit 14A causes the charging voltage Vc of the capacitor 131 when (charging voltage Vc−forward voltage Vfd ≧ voltage Vs of the signal St) is established. Is applied to the signal line 4 to improve the undershoot US of the signal St on the signal line 4.

(Effect of the second embodiment)
According to the second embodiment, since the current flowing between the collector and the emitter of the transistor 121 is limited by the resistor 132, the transistor 121 can be protected from an excessive current.

[Third Embodiment]
FIG. 5 shows a waveform improving circuit according to the third embodiment of the present invention. In the second embodiment, a discharge circuit 14B is configured from the diode 141 and the Zener diode 142 as a voltage limiting element connected between the anode of the diode 141 and the ground in the second embodiment. There are other configurations similar to those of the second embodiment.

(Operation of waveform improvement circuit)
Next, the operation of the waveform improvement circuit 1 according to the third embodiment will be described. The transmission circuit 2 transmits a digital signal St to the reception circuit 3 via the signal line 4. The signal St is applied to the level detection circuit 11A, divided by resistors 111 (R1) and 112 (R2), and the output voltage Vd is output from the level detection circuit 11A. This output voltage Vd becomes “H” level when the voltage Vs of the signal St transmitted on the signal line 4 is equal to or higher than the threshold voltage Vt, thereby turning on the transistor 121 of the switch circuit 12A, and the capacitor of the charging circuit 13B. Charging 131 is started.

  In the process of increasing the charging voltage Vc of the capacitor 131, the Zener diode 142 of the discharging circuit 14B limits the charging voltage Vc of the capacitor 131 so as not to exceed the Zener voltage. At this time, the resistor 132 limits the collector current flowing through the transistor 121 and also limits the current flowing through the Zener diode 142.

  The diode 141 applies the charging voltage Vc of the capacitor 131 to the signal line 4 when (charging voltage Vc−forward voltage Vfd ≧ voltage Vs of the signal St) is established, and performs an undershoot US of the signal St of the signal line 4. Improve.

(Effect of the third embodiment)
According to the third embodiment, the same effects as those of the second embodiment can be obtained, and the charging voltage Vc of the capacitor 131 does not exceed a predetermined value by providing the Zener diode 142 in the discharge circuit 14B. Thus, the maximum value of the charging voltage Vc can be prevented from fluctuating, whereby the waveform improving operation can be stabilized.

[Fourth Embodiment]
(Configuration of waveform improvement circuit)
FIG. 6 shows a waveform improving circuit according to the fourth embodiment of the present invention. In the present embodiment, in the second embodiment, the level detection circuit 11B is configured by a buffer 113 configured by an IC or the like instead of the resistors 111 and 112 of the level detection circuit 11A, and the transistor 121 of the switch circuit 12A is connected to the transistor 121. Instead, a switch circuit 12B is configured from a MOS (Metal-Oxide-Silicon) FET (Field Effect Transistor) 122, and diodes 143A and 143B connected in series instead of the Zener diode 142 of the discharge circuit 14B are used as voltage limiting elements. The other configuration is the same as that of the second embodiment.

  The MOSFET 122 of the switch circuit 12B has a gate connected to the output terminal of the buffer 113, a drain connected to the power supply, and a source connected to the resistor 132.

The diodes 143A and 143B of the discharge circuit 14C are connected in series so as to be forward with respect to the ground. A value obtained by adding the two forward voltages Vfd of the diodes 143A and 143B becomes the charging voltage Vc of the capacitor 131. Accordingly, here, the diode 143A, but is two and the 143B, in accordance with the voltage of the power supply voltage _{V B,} such that (the supply voltage _{V B} ≒ charging voltage Vc = Vfd × 2), 3 or more or 1 You may set the number to one.

(Operation of waveform improvement circuit)
Next, the operation of the waveform improvement circuit 1 according to the fourth embodiment will be described. The transmission circuit 2 transmits a digital signal St to the reception circuit 3 via the signal line 4. When the signal St transmitted to the signal line 4 reaches a level at which the buffer 113 of the level detection circuit 11B can operate (for example, 2 V or more), the output voltage Vd of “H” level is output from the buffer 113.

When the output voltage Vd of the level detection circuit 11B becomes "H" level, MOSFET 122 of the switching circuit 12B is turned on, the power supply voltage _{V B} is applied to the capacitor 131 of the discharge circuit 13B through MOSFET 122 and the resistor 132, charging is performed .

Charging of the capacitor 131 in the period of ON of MOSFET 122, is performed as shown in (d) of FIG. 3, the terminal voltage of the capacitor 131 will charge voltage Vc equal DC voltage approximately the power supply voltage _{V B.}

  The charging voltage Vc of the capacitor 131 is applied to each anode of the diode 141 and the diode 143A of the discharging circuit 14C. The diodes 143A and 143B connected in series function as one type of Zener diode, and regulate the charging voltage Vc of the capacitor 131 to Vfd × 2 (V). At this time, the resistor 132 limits the drain-source current flowing through the MOSFET 122 and also limits the current flowing through the diodes 143A and 143B.

  The diode 141 applies the charging voltage Vc of the capacitor 131 to the signal line 4 when (charging voltage Vc−forward voltage Vfd ≧ voltage Vs of the signal St) is established, and performs an undershoot US of the signal St of the signal line 4. Improve.

(Fourth embodiment)
According to the fourth embodiment, the same effects as those of the second embodiment can be obtained, and the switch circuit 12B uses the MOSFET 122 that operates at high speed, so that the signal transmission can be speeded up. it can. In addition, by providing the diodes 143A and 143B between the diode 141 and the ground in the discharge circuit 14C, the maximum value of the charging voltage Vc of the capacitor 131 can be prevented from fluctuating, and the waveform improving operation can be stabilized. be able to.

[Other embodiments]
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, the combination of the components between the embodiments can be arbitrarily performed.

  For example, in the second to fourth embodiments, the resistor 132 provided in the charging circuit 13B may be provided on the switch circuit 12A side.

  In the second to fourth embodiments, the Zener diode 142 and the diodes 143A and 143B provided in the discharge circuits 14B and 14C may be provided on the charging circuit 13B side.

It is a block diagram which shows the fundamental structure of the waveform improvement circuit which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the detailed structure of a waveform improvement circuit. It is a wave form diagram which shows the operation | movement waveform of each part of a waveform improvement circuit. It is a circuit diagram which shows the waveform improvement circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the waveform improvement circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the waveform improvement circuit which concerns on the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Waveform improvement circuit 2 Transmission circuit 3 Reception circuit 4 Signal line 11A, 11B Level detection circuit 12A, 12B Switch circuit 13A, 13B Charging circuit 14A, 14B Discharge circuit 20 Transmission side driver 30 Reception side driver 111, 112 Resistance 113 Buffer 121 Transistor 122 MOSFET
131 Capacitor 132 Resistance 141 Diode 142 Zener Diode 143A, 143B Diode

Claims (12)

In the waveform improvement circuit that improves the waveform of the digital signal transmitted to the signal line,
Charging means having a capacitor to be charged during a period in which the level of the digital signal exceeds a predetermined value;
A waveform improving circuit comprising: a discharging circuit that discharges the charge of the capacitor from the charging means to the signal line at a timing when the level of the digital signal becomes lower than a charging voltage of the capacitor. The charging means includes a level detection circuit that outputs a drive voltage when the level of the digital signal exceeds a predetermined value;
The waveform improvement circuit according to claim 1, further comprising: a switch circuit that applies a charging voltage to the capacitor based on the driving voltage from the level detection circuit.   The waveform according to claim 2, wherein the level detection circuit includes a plurality of resistors connected in series between the signal line and ground, and outputs the output voltage from a voltage dividing point of the resistors. Improvement circuit.   3. The waveform improvement circuit according to claim 2, wherein the level detection circuit includes a buffer and outputs the output voltage to the switch circuit.   The waveform improvement circuit according to claim 2, wherein the switch circuit includes a transistor or a MOSFET.   The waveform improvement circuit according to claim 1, wherein the discharge circuit includes a circuit element that establishes a one-way energization path from the capacitor toward the signal line.   The waveform improving circuit according to claim 6, wherein the circuit element includes a diode.   The waveform improving circuit according to claim 7, wherein the diode is a Schottky diode.   The waveform improving circuit according to claim 2, wherein the capacitor is connected in series with a resistor that limits a current flowing through the switch circuit.   The waveform improvement circuit according to claim 2, wherein the discharge circuit includes a voltage limiting element that is connected in parallel to the capacitor and defines the charging voltage.   The waveform improving circuit according to claim 10, wherein the voltage limiting element is a Zener diode.   11. The waveform improving circuit according to claim 10, wherein the voltage limiting element is composed of one or a plurality of diodes connected in series in accordance with energization directions.

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