JP2007227132A - Plasma display panel and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-reliability PDP capable of reducing the occurrence of a breakdown voltage failure even in high-definition display, and its manufacturing method. <P>SOLUTION: The plasma display panel is composed so that a discharge space is formed by sealing the periphery while oppositely arranging a front-face plate 2, in which a display electrode 6, a dielectric layer 8, and a protective layer 9 are formed on a front-face glass substrate 3, and a rear-face plate 10 in which address electrodes, barrier ribs 14, and a phosphor layer are formed on a rear-face glass substrate 11. The surface roughness of the protective layer 9 is set so as to be over 0.25 μm and not less than 0.49 μm in arithmetic average roughness Ra by setting a roughness curve cutoff value λc as λc=2.5 mm and a profile curve filter cutoff value λs as λs=8 μm. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a plasma display panel used for a display device and the like and a manufacturing method thereof.

  A plasma display panel (hereinafter referred to as PDP) can achieve high definition and a large screen, and therefore, a 65-inch class large-sized high-definition television has been commercialized.

  A PDP basically includes a front plate and a back plate. The front plate covers a display electrode composed of a glass substrate of sodium borosilicate glass by a float method, a striped transparent electrode and a bus electrode formed on one main surface of the glass substrate, and the display electrode. The dielectric layer functions as a capacitor, and a protective layer made of magnesium oxide (MgO) formed on the dielectric layer.

  The back plate includes a glass substrate, stripe-shaped address electrodes formed on one main surface thereof, a base dielectric layer covering the address electrodes, a partition formed on the base dielectric layer, and a space between each partition And phosphor layers emitting red, green and blue light respectively.

  The front plate and the back plate are hermetically sealed with their electrode forming surfaces facing each other, and Ne—Xe discharge gas is sealed at a pressure of 400 Torr to 600 Torr in a discharge space partitioned by a partition wall. PDP discharges by selectively applying a video signal voltage to the display electrodes, and the ultraviolet rays generated by the discharge excite each color phosphor layer to emit red, green, and blue light, thereby realizing color image display is doing.

  In recent years, PDP has been increasingly applied to full-spec high-definition televisions having more than twice the number of scanning lines as compared with the conventional NTSC system. As a result of such high definition, the number of scanning lines is increased, the number of display electrodes is increased, and the display electrode interval is further reduced.

  As a result, a phenomenon has occurred in which silver ions diffuse more from the silver electrode constituting the display electrode to the dielectric layer or the glass substrate. When silver ions diffuse into the dielectric layer or the glass substrate, they are reduced by alkali metal ions in the dielectric layer or divalent tin ions contained in the glass substrate to form silver colloids. As a result, the silver oxide undergoes a reducing action to generate oxygen and generate bubbles in the dielectric layer.

  Bubbles generated in these dielectric layers form protrusions that protrude from the surface of the protective layer formed on the dielectric layer, and the protrusions and the partition walls come into contact with each other when the front plate and the rear plate are bonded together. In some cases, the bubbles were broken and the dielectric layer could not secure a sufficient film thickness for electrical insulation, resulting in dielectric breakdown.

As countermeasures against such dielectric breakdown, the dielectric layer has a two-layer structure, and bubbles generated in the first layer are ruptured during manufacturing, and the bubble portion is filled with a dielectric formed in the second layer to electrically insulate. A structure and a manufacturing method for ensuring the necessary film thickness of the dielectric layer are disclosed (for example, see Patent Document 1).
JP 2005-149937 A

  However, in such a configuration, in addition to the problem that the effect is not obtained with respect to the bubbles generated in the second layer, the protrusions having a low height have a large number of occurrences per front plate, and Although contact also occurs with a high probability, it has been difficult to determine whether or not a bubble is broken, and it has been difficult to determine whether it is good or bad in an inspection at the time of manufacture.

  The present invention solves such a conventional problem, and an object of the present invention is to provide a highly reliable PDP and a method for manufacturing the same that reduce the occurrence of breakdown voltage failure even in high-definition display.

  In order to solve the above problems, the PDP of the present invention includes a first substrate in which an electrode, a dielectric layer, and a protective layer are formed on a first glass substrate, and an electrode on a second glass substrate. A PDP in which a barrier rib and a second substrate on which a phosphor layer is formed are opposed to each other, wherein the surface roughness of the protective layer is a roughness curve cutoff value λc = 2.5 mm, and a contour curve filter cutoff Assuming that the value λs = 8 μm, the arithmetic average roughness Ra is more than 0.25 μm and 0.49 μm or less.

  According to such a configuration, by dispersing the load received from the partition wall by the unevenness formed on the surface of the protective layer, it is possible to reduce the breakage of the bubbles in the dielectric layer, even in high-definition display, It is possible to realize a highly reliable PDP with less occurrence of breakdown voltage failure.

  The dielectric glass material constituting the dielectric layer of the PDP of the present invention may contain bismuth oxide and at least one of molybdenum oxide and tungsten oxide.

  When such a material is used as the dielectric glass material, it is particularly easy to control the surface roughness of the dielectric layer.

  According to the present invention, a first substrate in which an electrode, a dielectric layer, and a protective layer are formed on a first glass substrate, and an electrode, a partition, and a phosphor layer are formed on a second glass substrate. A method of manufacturing a plasma display panel in which a second substrate is disposed opposite to each other, where Ts is a softening point of the dielectric glass material constituting the dielectric layer, and a firing temperature Tf of the dielectric glass material is (Ts-15). ° C) ≦ Tf ≦ Ts.

  If the dielectric layer is baked in such a temperature range, the surface roughness of the protective layer can be formed within the above-mentioned surface roughness range, which can reduce the breakage of bubbles in the dielectric layer. it can.

  As described above, according to the present invention, it is possible to reduce the breakage of bubbles in the dielectric layer by dispersing the load received from the partition wall by the unevenness formed on the surface of the protective layer, and to achieve a high-definition display. However, it is possible to realize a highly reliable PDP with less occurrence of breakdown voltage failure.

  Hereinafter, a PDP according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a perspective view showing the structure of a PDP according to an embodiment of the present invention. As shown in FIG. 1, the PDP 1 includes a front plate 2 of a first substrate made of a front glass substrate 3 of a first glass substrate and a second substrate made of a rear glass substrate 11 of a second glass substrate. The back plate 10 is disposed so as to face the outer periphery, and the outer peripheral portion thereof is hermetically sealed with a sealing material made of a glass material or the like. A discharge gas such as neon (Ne) and xenon (Xe) is sealed in the sealed discharge space 16 inside the PDP 1 at a pressure of 400 Torr to 600 Torr.

  On the front glass substrate 3 of the front plate 2, a pair of strip-like display electrodes 6 composed of scanning electrodes 4 and sustain electrodes 5 and black stripes (light shielding layers) 7 are arranged in a plurality of rows in parallel with each other. . A dielectric layer 8 serving as a capacitor is formed on the front glass substrate 3 so as to cover the display electrode 6 and the light shielding layer 7, and a protective layer made of magnesium oxide (MgO) or the like is further formed on the surface. 9 is formed.

  On the back glass substrate 11 of the back plate 10, a plurality of strip-like address electrodes 12 are arranged in parallel to each other in a direction orthogonal to the scanning electrodes 4 and the sustain electrodes 5 of the front plate 2. Is covered. Further, on the underlying dielectric layer 13 between the address electrodes 12, barrier ribs 14 having a predetermined height for partitioning the discharge space 16 are formed. A phosphor layer 15 that emits red, blue, and green light by ultraviolet rays is sequentially formed in each groove between the barrier ribs 14 for each address electrode 12. A discharge cell is formed at a position where the scan electrode 4 and the sustain electrode 5 and the address electrode 12 intersect, and the discharge cell having the red, blue, and green phosphor layers 15 arranged in the direction of the display electrode 6 performs color display. It becomes a pixel for.

  FIG. 2 is a cross-sectional view showing a detailed structure of the front plate 2 of the PDP 1 of FIG. FIG. 2 shows FIG. 1 upside down. As shown in FIG. 2, display electrodes 6 including scanning electrodes 4 and sustaining electrodes 5 and black stripes 7 are formed in a pattern on a front glass substrate 3 manufactured by a float method or the like.

Scan electrode 4 and sustain electrode 5 include transparent electrodes 4a and 5a made of indium tin oxide (ITO), tin oxide (SnO ₂ ) and the like, and bus electrodes 4b and 5b formed on transparent electrodes 4a and 5a, respectively. It is comprised by. The bus electrodes 4b and 5b are used for the purpose of imparting conductivity in the longitudinal direction of the transparent electrodes 4a and 5a, and are formed of a conductive material mainly composed of a silver material.

  A dielectric layer 8 is formed on the front glass substrate 3 so as to cover the transparent electrodes 4a and 5a, the bus electrodes 4b and 5b, and the black stripes 7 formed on the front glass substrate 3. Further, a protective layer is formed on the dielectric layer 8. Layer 9 is formed. Here, the surface roughness of the protective layer 9 is such that the cutoff value for the roughness curve λc = 2.5 mm and the contour curve filter cutoff value λs = 8 μm, the arithmetic average roughness Ra exceeds 0.25 μm, and 0.49 μm. It is as follows.

  Here, since the bus electrodes 4b and 5b are mainly composed of a silver material, a phenomenon in which silver ions diffuse from the bus electrodes 4b and 5b to the dielectric layer 8 and the front glass substrate 3 occurs. As a result, the alkali metal ions contained in the dielectric layer 8 and the divalent tin ions contained in the front glass substrate 3 are subjected to a reducing action to form a silver colloid. As a result, the silver oxide receives a reducing action to generate oxygen, and bubbles 21 are generated in the dielectric layer. The bubbles 21 generated in the dielectric layer 8 form protrusions 22 protruding on the surface of the protective layer 9 formed on the dielectric layer 8.

  However, by setting the surface roughness of the protective layer 9 described above, the surface of the protective layer 9 is in a state where innumerable irregularities 9a are formed over the entire area. Therefore, the protrusions 22 formed on the surface of the protective layer 9 by the bubbles 21 generated in the dielectric layer 8 are a part of these innumerable irregularities 9a.

  Next, a method for manufacturing the PDP 1 will be described.

  The front plate 2 is formed as follows. In FIG. 1, first, scan electrodes 4, sustain electrodes 5, and black stripes 7 are formed on a front glass substrate 3. The transparent electrodes 4a and 5a and the bus electrodes 4b and 5b are formed by patterning using a photolithography method or the like. The transparent electrodes 4a and 5a are formed using a thin film process or the like, and the bus electrodes 4b and 5b are solidified by baking a paste containing a silver material at a desired temperature. Similarly, the black stripe 7 is formed by screen printing a paste containing a black pigment, or by forming a black pigment on the entire surface of the glass substrate and then patterning and baking using a photolithography method. .

  Next, a dielectric paste is applied on the front glass substrate 3 so as to cover the scan electrodes 4, the sustain electrodes 5 and the black stripes 7 by a die coating method or the like to form a dielectric layer paste layer, which is left for a predetermined time. To make a flat surface. Thereafter, the dielectric paste layer is baked and solidified to form the dielectric layer 8 that covers the scan electrode 4, the sustain electrode 5, and the light shielding layer 7.

The dielectric paste is a paint containing a dielectric glass material, a binder and a solvent. Here, the dielectric glass material is bismuth oxide (Bi ₂ O ₃ ) 25 wt% to 40 wt%, zinc oxide (ZnO) 27.5 wt% to 34 wt%, boron oxide (B ₂ O ₃ ). 17 wt% to 36 wt%, silicon oxide (SiO ₂ ) 1.4 wt% to 4.2 wt%, and aluminum oxide (Al ₂ O ₃ ) 0.5 wt% to 4.4 wt%. Yes. Furthermore, it contains 5 wt% to 13 wt% of at least one selected from calcium oxide (CaO), strontium oxide (SrO), and barium oxide (BaO), and is selected from molybdenum oxide (MoO ₃ ) and tungsten oxide (WO ₃ ). At least one selected from 0.1% by weight to 7% by weight. When such a dielectric glass material is used, it is particularly easy to control the surface roughness of the dielectric layer.

  The conventional dielectric layer was baked at a temperature of 590 ° C. or higher, which is slightly higher than the softening point 580 ° C. of the dielectric glass material, but the dielectric layer 8 in the present invention has a softening point of the dielectric glass material Ts. Then, the firing temperature Tf of the dielectric glass material is fired in a temperature range of (Ts−15 ° C.) ≦ Tf ≦ Ts. As a result, the surface roughness of the dielectric layer 8 can be formed rougher than that of the conventional dielectric layer.

  Next, a protective layer 9 made of magnesium oxide (MgO) is formed on the dielectric layer 8 by a vacuum deposition method. Through the above steps, predetermined components (scanning electrode 4, sustaining electrode 5, light shielding layer 7, dielectric layer 8, and protective layer 9) are formed on front glass substrate 3, and front plate 2 is completed. Since the protective layer 9 is an extremely thin layer of 2 μm or less, the surface roughness of the dielectric layer 8 is substantially equal to the surface roughness of the protective layer 9.

  The back plate 10 is formed as follows. First, the structure for the address electrode 12 is formed by a method of screen printing a paste containing a silver material on the rear glass substrate 11 or a method of patterning using a photolithography method after forming a metal film on the entire surface. An address electrode 12 is formed by forming a material layer to be formed and firing it at a desired temperature.

  Next, a dielectric paste layer is formed on the rear glass substrate 11 on which the address electrodes 12 are formed by applying a dielectric paste so as to cover the address electrodes 12 by a die coating method or the like. Thereafter, the base dielectric layer 13 is formed by firing the dielectric paste layer. The dielectric paste is a paint containing a dielectric material such as a glass material, a binder, and a solvent.

  Next, a partition wall forming paste containing a partition wall material is applied on the base dielectric layer 13 and patterned into a predetermined shape to form a partition wall material layer, followed by firing to form the partition walls 14. Here, as a method of patterning the partition wall paste applied on the base dielectric layer 13, a photolithography method and a sand blast method can be used.

  Next, the phosphor layer 15 is formed by applying and baking a phosphor paste containing a phosphor material on the base dielectric layer 13 between the adjacent barrier ribs 14 and on the side surfaces of the barrier ribs 14. Through the above steps, the back plate 10 having predetermined components on the back glass substrate 11 is completed.

  In this way, the front plate 2 and the back plate 10 provided with predetermined constituent members are arranged to face each other so that the scanning electrodes 4 and the address electrodes 12 are orthogonal to each other, and the periphery thereof is sealed with a glass material. The PDP 1 is completed by enclosing a discharge gas containing neon, xenon, etc. in the discharge space 16.

  FIG. 3 is a cross-sectional view showing the detailed structure of the front plate 20 and the back plate 10 of the PDP 1 of FIG. 1 and is shown upside down. As shown in FIG. 3, when the protrusions 22 formed on the surface of the protective layer 9 and the partition walls 14 formed on the back plate 10 come into contact with each other, the countless unevenness 9 a formed on the surface of the protective layer 9 The load received from the partition wall 14 is dispersed. As a result, the stress applied to the protrusions 22 is greatly reduced, and the bubbles 21 can be prevented from cracking.

  Next, the reason why the protective layer 9 has the above-described surface roughness and the dielectric layer 8 may be fired at the firing temperature in the above-described range will be described.

  First, the relationship between the diameter of the bubbles in the dielectric layer and the protrusion height will be described. FIG. 4 is a diagram showing the relationship between the diameter of the bubbles in the dielectric layer of the PDP according to the embodiment of the present invention and the protrusion height. As shown in FIG. 4, the diameter of the bubbles 21 is distributed between about 20 μm and 80 μm, and has an average size of about 40 μm. The height of the protrusion due to the bubble having a diameter of 40 μm is about 2 μm.

  FIG. 5 is a diagram for explaining the roughness of the surface of the dielectric layer of the PDP according to the embodiment of the present invention. The roughness of the surface of the dielectric layer is represented by a roughness curve cutoff value λc = 2.5 mm, It is a figure which shows the relationship between the number for every protrusion height in different arithmetic mean roughness Ra, and the number of cracked bubbles by setting the contour curve filter cutoff value λs = 8 μm.

  5A shows a case where Ra on the surface of the dielectric layer 8 is 0.25 μm, and FIG. 5B shows a case where Ra is 0.49 μm. In both cases, the number of protrusions is 100. It is the figure which compared the ratio which the bubble 21 breaks. Here, the white bar graph represents the height distribution of the protrusions 22, and the hatched bar graph represents the number of bubbles 21 broken in each distribution. As shown in FIG. 4, the average height of the protrusion is about 2 μm. From the graph of FIG. 5, the protrusion height is often 3 μm or less, and when Ra is 0.25 μm, the protrusion height is 3 μm or less. It can be seen that there are many broken bubbles. For example, in the case of a protrusion having a height of 2 μm with the largest distribution of protrusion height, when Ra is 0.25 μm, 18 bubbles 21 are cracked in 30 protrusions, while Ra is 0.49 μm. Then, the number is significantly reduced to 7 out of 31 protrusions.

  FIG. 6 is a diagram for explaining the firing temperature range of the dielectric layer of the PDP according to the embodiment of the present invention, and the relationship between the firing temperature of the dielectric layer 8 and the arithmetic average roughness Ra of the surface of the dielectric layer 8. FIG. FIG. 6 shows the displacement measured on the surface of the dielectric layer 8 with a surface roughness measuring device (manufactured by ULVAC, Inc., Dektak 3ST) on the vertical axis and the moving distance on the horizontal axis. 6A, 6B, and 6C show the results when the dielectric glass material having a softening point of 580 ° C. is set to a firing temperature of 595 ° C., 580 ° C., and 565 ° C., respectively.

  As shown in FIG. 6A, when the firing temperature of the dielectric layer 8 is 595 ° C., the Ra of the dielectric layer 8 is 0.25 μm. As shown in FIG. 6B, when the firing temperature of the dielectric layer 8 is 580 ° C., the Ra of the dielectric layer 8 is 0.30 μm. As shown in FIG. 6C, when the firing temperature of the dielectric layer 8 is 565 ° C., the Ra of the dielectric layer 8 is 0.49 μm. Thus, as the firing temperature of the dielectric layer 8 is lowered, Ra of the dielectric layer 8 increases, but if Ra exceeds 0.49 μm, the ratio of scattered light increases, which is not desirable. This roughness curve is within the range of the roughness curve cutoff value λc = 2.5 mm and the contour curve filter cutoff value λs = 8 μm, excluding those with extremely rough surface roughness. Yes. That is, the present invention requires a large number of average irregularities and disperses the load with the irregularities.

  FIG. 7 is a diagram showing the relationship between the breakdown voltage failure rate of the PDP and the surface roughness of the dielectric layer according to the embodiment of the present invention. Here, the withstand voltage failure rate is a ratio of panels that are not lit due to insulation withstand voltage failure when a completed PDP lighting test is performed. In FIG. 7, the vertical axis represents the breakdown voltage failure rate of the PDP, the horizontal axis represents the roughness of the surface of the dielectric layer, the roughness curve cutoff value λc = 2.5 mm, and the contour curve filter cutoff value λs = 8 μm. The arithmetic average roughness Ra is taken.

  In FIG. 7, when Ra = 0.2 μm, the breakdown voltage failure rate is as large as 1.7%, but when Ra = 0.25 μm, the breakdown voltage failure rate decreases to 0.8%, and when Ra = 0.49 μm, the breakdown voltage failure rate is Reduced to 0.5%. Thus, as the surface roughness of the dielectric layer 8 becomes rough, the breakdown voltage failure rate is improved. This is because when the surface roughness Ra is 0.25 μm or less and the surface roughness is relatively smooth, the height of the protrusion due to the bubbles in the dielectric layer is often higher, and the load from the partition wall on the bubbles It is thought that it takes. Further, if Ra exceeds 0.25 μm, the height of the protrusion due to the bubbles is often smaller than the unevenness of the surface roughness, and the load from the partition walls is not applied to the bubbles, so that the breakdown voltage failure rate is considered to decrease. It is done.

  In the embodiment of the present invention, the arithmetic average roughness Ra of the surface of the dielectric layer 8 has been described. As described above, the dielectric layer 8 has a thickness of about 40 μm, and the protective layer 9 has a thickness of 2 μm or less. Therefore, the surface roughness of the dielectric layer 8 may be considered as the surface roughness of the protective layer 9.

  As described above, according to the PDP of the present invention, it is possible to reduce the breakage of the bubbles in the dielectric layer by dispersing the load received from the partition wall by the unevenness formed on the surface of the protective layer, and high definition. Also in display, a PDP with less occurrence of breakdown voltage failure and high reliability can be realized.

  As described above, the PDP of the present invention is less likely to cause a breakdown voltage failure and is useful for a high-definition and large-screen display device.

The perspective view which shows the structure of PDP of embodiment of this invention Sectional drawing which shows the detailed structure of the front plate of PDP of FIG. Sectional drawing which shows the detailed structure of the front plate and back plate of PDP of FIG. The figure which shows the relationship between the diameter of the bubble in the dielectric material layer of PDP of embodiment of this invention, and protrusion height The figure explaining the surface roughness of the dielectric layer of the PDP, (a) showing the case where Ra is 0.25 μm, (b) showing the case where Ra is 0.49 μm The figure explaining the firing temperature range of the dielectric layer of the PDP (a) The figure showing the case where the firing temperature is 595 ° C. (b) The figure showing the case where the firing temperature is 580 ° C. (c) The firing temperature is 565 ° C. Illustration showing the case The figure which shows the relationship between the pressure | voltage resistant defect rate of the same PDP, and the roughness of the surface of a dielectric material layer

Explanation of symbols

1 PDP
2 Front plate (first substrate)
3 Front glass substrate (first glass substrate)
4 Scan electrode 4a, 5a Transparent electrode 4b, 5b Bus electrode 5 Sustain electrode 6 Display electrode 7 Black stripe (light shielding layer)
8 Dielectric layer 9 Protective layer 9a Concavity and convexity 10 Back plate (second substrate)
11 Back glass substrate (second glass substrate)
12 Address electrode 13 Base dielectric layer 14 Partition 15 Phosphor layer 16 Discharge space 21 Bubble 22 Projection

Claims (3)

A first substrate in which an electrode, a dielectric layer and a protective layer are formed on a first glass substrate; and a second substrate in which an electrode, a partition and a phosphor layer are formed on a second glass substrate; The surface roughness of the protective layer is set to a roughness curve cutoff value λc = 2.5 mm and a contour curve filter cutoff value λs = 8 μm in terms of arithmetic average roughness Ra. A plasma display panel, wherein the plasma display panel is more than 0.25 μm and not more than 0.49 μm. The plasma display panel according to claim 1, wherein the dielectric glass material constituting the dielectric layer contains bismuth oxide and at least one of molybdenum oxide and tungsten oxide. A first substrate in which an electrode, a dielectric layer and a protective layer are formed on a first glass substrate; and a second substrate in which an electrode, a partition and a phosphor layer are formed on a second glass substrate; Is a method for manufacturing a plasma display panel in which the dielectric glass material composing the dielectric layer is Ts, where Ts is a softening point of the dielectric glass material, and the firing temperature Tf of the dielectric glass material is (Ts−15 ° C.) ≦ A manufacturing method of a plasma display panel, wherein Tf ≦ Ts.

Images