JP2007221507A - Flip-flop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-flop circuit which has a reset function and causes no leakage path. <P>SOLUTION: When a reset signal becomes high level, PMOS transistor PT5 is cut off and NMOS transistor NT6 is turned on. Consequently, a node N2 and a node N3 are separated by the PMOS transistor PT5 while electric charge is discharged from a node N3 via the NMOS transistor NT6, and thereby the node N3 becomes low level. Accordingly, PMOS transistor PT4 is turned on NMOS transistor NT5 is cut off, and an output signal of an inverting output terminal XQ is fixed to high level. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a dynamic flip-flop circuit having a reset function.

The flip-flop circuit is a basic and important circuit used in a synchronous circuit such as a frequency divider, a counter, a shift register, a pipeline register, and the like.
As the flip-flop circuit, for example, a dynamic flip-flop circuit as shown in FIG.

However, since the dynamic flip-flop circuit shown in FIG. 6 charges and discharges the drain terminal on the assumption that a clock signal that always toggles is input, the clock signal and the data signal are fixed at the power supply level or the ground level. In such a case, it is not assumed that the intermediate voltage is generated inside the circuit.
“High-speed CMOS circuit technique”, Solid-State Circuits, IEEE Journal of Volume 24, issue 1, Feb. 1989 p. 62-70, by Yuan. J, Svensson. C

  Therefore, when the clock signal and the data signal are fixed at the power supply potential level or the ground level, respectively, for example, when the clock signal and the data signal are both fixed at the power supply potential level in FIG. As shown, a leak path may occur, a large amount of through current flows, and a disadvantage that power consumption increases.

  An object of the present invention is to provide a flip-flop circuit that has a reset function and does not generate a leak path in order to eliminate the disadvantages described above.

  In order to eliminate the disadvantages described above, a flip-flop circuit according to a first aspect of the present invention includes a data signal input terminal for inputting a data signal, a synchronization signal input terminal for inputting a synchronization signal, an inverted output terminal, An output node formed to be connected to a non-inverting output terminal that performs output opposite to the inverting output terminal, a reset terminal that inputs a reset signal, a first intermediate node, a second intermediate node, Three intermediate nodes, first and second first conductivity type transistors connected in series and sequentially between a power supply potential and the first intermediate node, and between the first intermediate node and the ground potential A first second conductivity type transistor connected to the first power supply potential, a third first conductivity type transistor connected between the power supply potential and the second intermediate node, the second intermediate node and the ground. Directly between the potential The second and third second conductivity type transistors connected to each other, the fourth first conductivity type transistor connected between the power supply potential and the output node, the output node and the ground potential. A fourth and fifth second conductivity type transistor connected in series between each other; a fifth first conductivity type transistor connected between the second intermediate node and the third intermediate node; A sixth second conductivity type transistor connected between a third intermediate node and the ground potential, wherein each of the first conductivity type transistors has the data signal at a first potential level. When the data signal is at the first potential level, each of the second conductivity type transistors is in a non-conduction state when the data signal is at the first potential level. When at potential level It is turned on.

  Preferably, the first first conductivity type transistor becomes conductive when the data signal is at a first potential level, and becomes non-conductive when the data signal is at a second potential level. The second conductivity type transistor is non-conductive when the data signal is at the first potential level, and is conductive when the data signal is at the second potential level. The second and third first conductivity type transistors are When the synchronizing signal is at the first potential level, the conducting state is established, and when the synchronizing signal is at the second potential level, the conducting state is established, and the third and fourth second conductivity type transistors have the synchronizing signal When it is at the first potential level, it is in a non-conductive state, and when it is at the second potential level, it is in a conductive state, and the second second conductivity type transistor has the first intermediate node at the first potential level. And the fourth first conductivity type transistor is conductive when the third intermediate node is at the first potential level. And when the second potential level is at a second potential level, the fifth second-conductivity type transistor is non-conductive when the third intermediate node is at the first potential level, and the second potential level is The fifth first conductivity type transistor is conductive when the reset signal is at the first potential level, and is non-conductive when the reset signal is at the second potential level. The sixth second conductivity type transistor is in a non-conductive state when the reset signal is at a first potential level, and is in a conductive state when the reset signal is at a second potential level. That.

  Preferably, the first conductivity type transistor is a P-channel transistor, and the second conductivity type transistor is an N-channel transistor.

  Preferably, the first potential level is a ground potential level, and the second potential level is a power supply potential level.

  A flip-flop circuit according to a second aspect of the invention includes a data signal input terminal for inputting a data signal, a synchronization signal input terminal for inputting a synchronization signal, an inverting output terminal, and a non-inverting output terminal that performs an output opposite to the inverting output terminal. An output node connected to the inverting output terminal; a reset terminal for inputting a reset signal; a first intermediate node; a second intermediate node; a third intermediate node; a power supply potential; First and second first conductivity type transistors connected in series and sequentially between the first intermediate node and first second conductivity connected between the first intermediate node and the ground potential. Type transistor, fifth and third first conductivity type transistors connected in series and sequentially between the power supply potential and the second intermediate node, and between the second intermediate node and the ground potential Connected in series Second and third second conductivity type transistors, a fourth first conductivity type transistor connected between the power supply potential and the output node, and in series between the output node and the ground potential. Fourth and fifth second conductivity type transistors connected to each other, and a sixth second conductivity type transistor connected between the third intermediate node and the ground potential, and The one conductivity type transistor is conductive when the data signal is at the first potential level, and is non-conductive when the data signal is at the second potential level. When it is at the first potential level, it is non-conductive, and when it is at the second potential level, it is conductive.

  Preferably, the first first conductivity type transistor becomes conductive when the data signal is at a first potential level, and becomes non-conductive when the data signal is at a second potential level. The second conductivity type transistor is non-conductive when the data signal is at the first potential level, and is conductive when the data signal is at the second potential level. The second and third first conductivity type transistors are When the synchronizing signal is at the first potential level, the conducting state is established, and when the synchronizing signal is at the second potential level, the conducting state is established, and the third and fourth second conductivity type transistors have the synchronizing signal When it is at the first potential level, it is in a non-conductive state, and when it is at the second potential level, it is in a conductive state, and the second second conductivity type transistor has the first intermediate node at the first potential level. And the fourth first conductivity type transistor is conductive when the third intermediate node is at the first potential level. And when the second potential level is at a second potential level, the fifth second-conductivity type transistor is non-conductive when the third intermediate node is at the first potential level, and the second potential level is The fifth first conductivity type transistor is conductive when the reset signal is at the first potential level, and is non-conductive when the reset signal is at the second potential level. The sixth second conductivity type transistor is in a non-conductive state when the reset signal is at a first potential level, and is in a conductive state when the reset signal is at a second potential level. That.

  A flip-flop circuit according to a third aspect of the invention is a data signal input terminal for inputting a data signal, a synchronization signal input terminal for inputting a synchronization signal, an inverting output terminal, and a non-inverting output terminal for performing an output opposite to the inverting output terminal. An output node connected to the inverting output terminal; a reset terminal for inputting a reset signal; a first intermediate node; a second intermediate node; a third intermediate node; a power supply potential; First and second first conductivity type transistors connected in series and sequentially between the first intermediate node and first second conductivity connected between the first intermediate node and the ground potential. And a third first-conductivity-type transistor connected between the power supply potential and the second intermediate node, and connected in series between the second intermediate node and the ground potential. Second and third second A fourth transistor connected in series between the output node and the ground potential; a fourth transistor connected between the output node and the ground potential; a fourth transistor connected between the power supply potential and the output node; A second conductivity type transistor, and a fifth first conductivity type transistor connected between the power supply potential and the output node. When the potential level is 1, it becomes conductive, when it is the second potential level, it becomes non-conductive, and each of the second conductivity type transistors is non-conductive when the data signal is at the first potential level. When it is in the second potential level, it becomes conductive.

  Preferably, the first first conductivity type transistor becomes conductive when the data signal is at a first potential level, and becomes non-conductive when the data signal is at a second potential level. The second conductivity type transistor is non-conductive when the data signal is at the first potential level, and is conductive when the data signal is at the second potential level. The second and third first conductivity type transistors are When the synchronizing signal is at the first potential level, the conducting state is established, and when the synchronizing signal is at the second potential level, the conducting state is established, and the third and fourth second conductivity type transistors have the synchronizing signal When it is at the first potential level, it is in a non-conductive state, and when it is at the second potential level, it is in a conductive state, and the second second conductivity type transistor has the first intermediate node at the first potential level. And the fourth first conductivity type transistor is conductive when the third intermediate node is at the first potential level. And when the second potential level is at a second potential level, the fifth second-conductivity type transistor is non-conductive when the third intermediate node is at the first potential level, and the second potential level is The fifth first conductivity type transistor is conductive when the reset signal is at the first potential level, and is non-conductive when the reset signal is at the second potential level. Become.

  According to the present invention, it is possible to provide a flip-flop circuit that has a reset function and does not generate a leak path.

  Hereinafter, a flip-flop circuit according to an embodiment of the present invention will be described.

FIG. 1 is a circuit diagram showing a flip-flop circuit 1 of the first embodiment.
As shown in FIG. 1, the flip-flop circuit 1 of this embodiment includes a data input terminal D to which a data signal is input, a clock input terminal (synchronization signal input terminal) CLK to which a clock signal (synchronization signal) is input, and a reset. A reset terminal R to which a signal is input, first to fifth PMOS transistors PT1 to PT5, first to sixth NMOS transistors NT1 to NT6, an inverting output terminal XQ, an inverter circuit INV, a non-inverting output terminal Q, and a node N1 ~ N3.

As shown in FIG. 1, the sources of the PMOS transistors PT1, PT3, and PT4 are connected to the power supply potential Vdd.
The sources of the NMOS transistors NT1, NT3, NT5 and NT6 are connected to the ground potential GND.
The gates of the PMOS transistor PT1 and the NMOS transistor NT1 are connected to the data input terminal D.
The gates of the PMOS transistors PT2 and PT3 and the NMOS transistors NT3 and NT4 are connected to the clock input terminal.
The gates of the PMOS transistor PT5 and the NMOS transistor NT6 are connected to the reset terminal R.

The drain of the PMOS transistor PT1 is connected to the source of the PMOS transistor PT2, and the drain of the PMOS transistor PT2 and the drain of the NMOS transistor NT1 are connected to the gate of the NMOS transistor NT2 via the node N1.
The source of the NMOS transistor NT2 is connected to the drain of the NMOS transistor NT3, and the drain of the PMOS transistor PT3 and the drain of the NMOS transistor NT2 are connected to the source of the PMOS transistor PT5 via the node N2.

  The drain of the PMOS transistor PT5 and the drain of the NMOS transistor NT6 are connected to the gates of the PMOS transistor PT4 and the NMOS transistor NT5 via the node N3. The source of the NMOS transistor NT4 is connected to the drain of the NMOS transistor NT5, and the drain of the PMOS transistor PT4 and the drain of the NMOS transistor NT4 are connected to the inverting output terminal XQ and the non-inverting output terminal Q via the inverting circuit.

  Next, the operation of the flip-flop circuit 1 will be described with reference to the timing chart shown in FIG. In the following description, the power supply potential level is referred to as a high level, and the ground potential (ground) level is referred to as a low level.

When the clock signal is at a low level, the PMOS transistors PT2 and PT3 are turned on, and the NMOS transistors NT3 and NT4 are cut off. When the data signal is at a low level, the PMOS transistor PT1 is turned on and the NMOS transistor NT1 is cut off. When the reset signal is at a low level, the PMOS transistor PT5 is turned on and the NMOS transistor NT6 is cut off.
Therefore, during a period in which the clock signal, the data signal, and the reset signal are at a low level, the nodes N1 and N3 illustrated in FIG. 1 are precharged to a high level as illustrated in FIG.

  Next, when the clock signal becomes high level, the PMOS transistors PT2 and PT3 are cut off and the NMOS transistors NT3 and NT4 are turned on, respectively. For this reason, the node N3 is discharged through the PMOS transistor PT5 and the NMOS transistors NT2 and NT3 and becomes low level. Further, since the node N3 is discharged, the PMOS transistor PT4 is turned on and the NMOS transistor NT5 is cut off, so that the output signal of the inverting output terminal XQ becomes high level.

  Next, when the data signal becomes high level, the PMOS transistor PT1 is cut off and the NMOS transistor NT1 is turned on. Therefore, the node N1 is discharged through the NMOS transistor NT1, and the node N1 becomes a low level. For this reason, the NMOS transistor NT2 is cut off.

  Next, when the clock signal goes low, the PMOS transistors PT2 and PT3 are turned on, and the NMOS transistors NT3 and NT4 are cut off. For this reason, the node N3 is charged through the PMOS transistors PT3 and PT5 and becomes high level. Therefore, the PMOS transistor PT4 is cut off and the NMOS transistor NT5 is turned on. However, since the NMOS transistor NT4 is cut off, the signal at the inverting output terminal XQ does not change.

  Next, when the clock signal becomes high level, the PMOS transistors PT2 and PT3 are cut off and the NMOS transistors NT3 and NT4 are turned on, respectively. For this reason, charges are discharged through the NMOS transistors NT4 and NT5, and the inverted output terminal XQ becomes low level.

  Next, when the data signal goes low, the PMOS transistor PT1 is turned on and the NMOS transistor NT1 is cut off, but the charges at the nodes N1 and N3 and the inverted output terminal XQ do not change.

  Next, when the clock signal goes low, the PMOS transistors PT2 and PT3 are turned on, and the NMOS transistors NT3 and NT4 are cut off. Therefore, charging is performed through the PMOS transistors PT1 and PT2, and the node N1 becomes high level.

  Next, when the clock signal becomes high level, the PMOS transistors PT2 and PT3 are cut off and the NMOS transistors NT3 and NT4 are turned on, respectively. Accordingly, the charge of the PMOS transistor PT5 and the node N2 is discharged through the NMOS transistors NT2 and NT3 and goes to the low level. Therefore, the PMOS transistor PT4 is turned on and the NMOS transistor NT5 is cut off, so that the inverting output terminal XQ is charged and becomes high level.

  Next, when the data signal becomes high level, the PMOS transistor PT1 is cut off and the NMOS transistor NT1 is turned on. For this reason, the node N1 is discharged through the NMOS transistor NT1, and the node N1 becomes low level. For this reason, the NMOS transistor NT2 is cut off.

The flip-flop circuit 1 performs the above-described operation while a clock signal that is always toggled is input.
However, as shown in FIG. 2, when a long time elapses in the standby state, for example, when both the clock signal and the data signal are fixed at a high level, a leak path occurs, and the node N2 becomes an intermediate voltage (high level). And the voltage at the node N3 and the inverting output terminal XQ are also intermediate voltages.

At this time, in the flip-flop circuit 1, as shown in FIG. 4, reset is performed by inputting a high level reset signal, and the output signal from the inverting output terminal XQ can be determined.
The operation of the flip-flop circuit 1 when a high level reset signal is input will be described below.

  When the reset signal becomes high level, the PMOS transistor PT5 is cut off and the NMOS transistor NT6 is turned on. For this reason, the node N2 and the node N3 are disconnected by the PMOS transistor PT5, and the node N3 is discharged through the NMOS transistor NT6 and goes to the low level, so that the PMOS transistor PT4 is turned on and the NMOS transistor NT5 is cut off. , The output signal of the inverting output terminal XQ is fixed at a high level.

As described above, according to the flip-flop circuit 1 of the present embodiment, even if the node N2 that becomes an intermediate voltage in the standby state where both the clock signal and the data signal are fixed at the high level exists, the high level By inputting the reset signal, the node N2 can be disconnected from the circuit and the output can be determined. At this time, since no leak path exists in the circuit, the current consumption of the entire circuit can be greatly reduced.
Furthermore, in the above embodiment, the standby state in which both the clock signal and the data signal are at the high level has been described. However, since the leak path does not exist in the circuit even in the standby state of other combinations of the clock signal and the data signal, this embodiment is implemented. The flip-flop circuit 1 can be reset with a consumption current amount of approximately 0 by inputting a reset signal.

Second Embodiment
In the second embodiment, a flip-flop circuit 1a that can be operated at higher speed by changing the configuration of the flip-flop circuit 1 of the first embodiment will be described.
FIG. 4 is a circuit diagram showing the flip-flop circuit 1a of the second embodiment.

As shown in FIG. 4, in the flip-flop circuit 1a of the second embodiment, a data input terminal D to which a data signal is input, a clock input terminal (synchronization signal input terminal) CLK to which a clock signal is input, and a reset signal are input. Reset terminal R, first to fourth PMOS transistors PT1 to PT4 and fifth PMOS transistor PT5a, first to sixth NMOS transistors NT1 to NT6, inverting output terminal XQ, inverter circuit INV, non-inverting output terminal Q and nodes N1 to N3.
As shown in FIG. 4, the flip-flop circuit 1a of the second embodiment has a configuration in which the PMOS transistor PT5 is removed from the flip-flop circuit 1 of the first embodiment and a PMOS transistor PT5a is added.

As shown in FIG. 4, the sources of the PMOS transistors PT1, PT4, and PT5a are connected to the power supply potential Vdd.
The sources of the NMOS transistors NT1, NT3, NT5 and NT6 are connected to the ground potential GND.
The gates of the PMOS transistor PT1 and the NMOS transistor NT1 are connected to the data input terminal D.
The gates of the PMOS transistors PT2 and PT3 and the NMOS transistors NT3 and NT4 are connected to the clock input terminal.
The gates of the PMOS transistor PT5a and the NMOS transistor NT6 are connected to the reset terminal R.

The drain of the PMOS transistor PT1 is connected to the source of the PMOS transistor PT2, and the drain of the PMOS transistor PT2 and the drain of the NMOS transistor NT1 are connected to the gate of the NMOS transistor NT2.
The drain of the PMOS transistor PT5a is connected to the source of the PMOS transistor PT3. The source of the NMOS transistor NT2 is connected to the drain of the NMOS transistor NT3, and the drain of the PMOS transistor PT3, the drain of the NMOS transistor NT2, and the drain of the NMOS transistor NT6 are connected to the gates of the PMOS transistor PT4 and the NMOS transistor NT5.

  The source of the NMOS transistor NT4 is connected to the drain of the NMOS transistor NT5, and the drain of the PMOS transistor PT4 and the drain of the NMOS transistor NT4 are connected to the inverting output terminal XQ and the non-inverting output terminal Q via the inverting circuit.

  Hereinafter, an operation example of the flip-flop circuit 1a will be described. However, since the operation until the reset signal is input is the same as that of the flip-flop circuit 1, the operation when the reset signal is input in the standby state where both the clock signal and the data signal are at the high level will be described.

  When the reset signal becomes high level, the PMOS transistor PT5a is cut off and the NMOS transistor NT6 is turned on. Therefore, the node N2 and the node N3 are discharged through the NMOS transistor NT6 and become low level, the PMOS transistor PT4 is turned on, the NMOS transistor NT5 is cut off, and the output signal of the inverting output terminal XQ is determined to be high level.

As described above, according to the flip-flop circuit 1a of the second embodiment, even if there is a node N2 that becomes an intermediate voltage during standby in which both the clock signal and the data signal are fixed at a high level, By inputting a level reset signal, the node N2 can be disconnected from the circuit to determine the output. At this time, since no leak path exists in the circuit, the current consumption of the entire circuit can be greatly reduced.
Furthermore, in the second embodiment, the standby state in which both the clock signal and the data signal are at the high level has been described. However, since there is no leak path in the circuit even in the standby state of other combinations of the clock signal and the data signal, The flip-flop circuit 1a of the embodiment can be reset with a consumption current amount of almost zero by inputting a reset signal.

  Further, in the flip-flop circuit 1a of the second embodiment, the capacity of the drain terminal of the NMOS transistor NT5 can be reduced, so that a higher speed operation than the flip-flop circuit 1 of the first embodiment is possible.

<Third Embodiment>
In the third embodiment, a flip-flop circuit 1b having a reset function will be described.
FIG. 5 is a circuit diagram showing the flip-flop circuit 1b of the third embodiment.
As shown in FIG. 5, the flip-flop circuit 1b includes a data input terminal D to which a data signal is input, a clock input terminal CLK to which a clock signal is input, an inverting reset terminal XR to which an inverting reset signal is input, It has fourth PMOS transistors PT1 to PT4 and fifth transistor PT5b, first to fifth NMOS transistors NT1 to NT5, an inverting output terminal XQ, an inverter circuit INV, a non-inverting output terminal Q, and nodes N1 to N3.

  As shown in FIG. 5, the flip-flop circuit 1b has a configuration in which the PMOS transistor PT5 and the NMOS transistor NT6 are removed from the flip-flop circuit 1 of the first embodiment and a PMOS transistor PT5b is added.

As shown in FIG. 5, the sources of the PMOS transistors PT1, PT4 and PT5b are connected to the power supply potential Vdd.
The sources of the NMOS transistors NT1, NT3, and NT5 are connected to the ground potential GND.
The gates of the PMOS transistor PT1 and the NMOS transistor NT1 are connected to the data input terminal D.
The gates of the PMOS transistors PT2 and PT3 and the NMOS transistors NT3 and NT4 are connected to the clock input terminal.
The gate of the PMOS transistor PT5b is connected to the reset terminal R.

The drain of the PMOS transistor PT1 is connected to the source of the PMOS transistor PT2, and the drain of the PMOS transistor PT2 and the drain of the NMOS transistor NT1 are connected to the gate of the NMOS transistor NT2.
The source of the NMOS transistor NT2 is connected to the drain of the NMOS transistor NT3, and the drain of the PMOS transistor PT3 and the drain of the NMOS transistor NT2 are connected to the gates of the PMOS transistor PT4 and the NMOS transistor NT5.

  The source of the NMOS transistor NT4 is connected to the drain of the NMOS transistor NT5, and the drain of the PMOS transistor PT4, the drain of the NMOS transistor NT4, and the drain of the PMOS transistor PT5b are connected to the inverting output terminal XQ and the non-inverting output terminal Q via the inverting circuit. It is connected to the.

In the flip-flop circuit 1b, when a reset is performed in the standby state, a reset signal of a low level is input, so that the reset can be performed and the output of the inverting output terminal XQ can be determined.
For example, when a clock signal and a data signal are both fixed at a high level and a long time has elapsed, a leak path occurs in the flip-flop circuit 1b, and the node N3 and the inverted output terminal XQ shown in FIG. 5 become an intermediate voltage. .

  In the state described above, when a low level reset signal is input, the PMOS transistor PT5b is turned on, and the output signal of the inverting output terminal XQ can be determined at a high level.

  As described above, according to the flip-flop circuit 1b of the third embodiment, when a low level reset signal is input in the standby state, the PMOS transistor PT5b is turned on and the output signal of the inverting output terminal XQ is high level. Can be confirmed. That is, the reset function can be exhibited.

The present invention is not limited to the embodiment described above.
That is, those skilled in the art may make various modifications, combinations, subcombinations, and alternatives regarding the components of the above-described embodiments within the technical scope of the present invention or an equivalent scope thereof.

FIG. 1 is a circuit diagram showing a flip-flop circuit 1 of the first embodiment. FIG. 2 is a timing chart for explaining the operation of the flip-flop circuit. FIG. 3 is a timing chart including a reset signal for explaining the operation of the flip-flop circuit. FIG. 4 is a circuit diagram showing the flip-flop circuit 1a of the second embodiment. FIG. 5 is a circuit diagram showing the flip-flop circuit 1b of the third embodiment. FIG. 6 is a circuit diagram showing an example of the flip-flop circuit described in Non-Patent Document 1.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1a, 1b ... Flip-flop circuit, CLK ... Clock input terminal, D ... Data input terminal, Vdd ... Power supply potential, GND ... Ground potential, INV ... Inverter circuit, PT1, PT2, PT3, PT4, PT5, PT5a, PT5b ... PMOS transistor, NT1, NT2, NT3, NT4, NT5, NT6 ... NMOS transistor, Q ... Non-inverted output terminal, ... Reset terminal, XQ ... Inverted output terminal, N1, N2, N3 ... Node

Claims (8)

A data signal input terminal for inputting a data signal;
A synchronization signal input terminal for inputting a synchronization signal;
An output node formed to connect to an inverting output terminal and a non-inverting output terminal that performs an output opposite to the inverting output terminal;
A reset terminal for inputting a reset signal;
A first intermediate node;
A second intermediate node;
A third intermediate node;
First and second first conductivity type transistors connected in series and sequentially between a power supply potential and the first intermediate node;
A first second conductivity type transistor connected between the first intermediate node and a ground potential;
A third first conductivity type transistor connected between the power supply potential and the second intermediate node;
Second and third second conductivity type transistors connected in series between the second intermediate node and the ground potential;
A fourth first conductivity type transistor connected between the power supply potential and the output node, and fourth and fifth second conductivity types connected in series between the output node and the ground potential. A transistor,
A fifth first conductivity type transistor connected between the second intermediate node and the third intermediate node;
A sixth second conductivity type transistor connected between the third intermediate node and the ground potential;
Have
Each of the first conductivity type transistors becomes conductive when the data signal is at a first potential level, and becomes non-conductive when the data signal is at a second potential level,
Each of the second conductivity type transistors is in a non-conductive state when the data signal is at a first potential level, and is in a conductive state when the data signal is at a second potential level. The first first conductivity type transistor is turned on when the data signal is at a first potential level, and is turned off when the data signal is at a second potential level,
The first second conductivity type transistor is non-conductive when the data signal is at a first potential level, and is conductive when the data signal is at a second potential level;
The second and third first conductivity type transistors are conductive when the synchronization signal is at a first potential level, and are non-conductive when the synchronization signal is at a second potential level,
The third and fourth second conductivity type transistors are non-conductive when the synchronization signal is at the first potential level, and are conductive when the synchronization signal is at the second potential level.
The second second conductivity type transistor is non-conductive when the first intermediate node is at the first potential level, and is conductive when the second intermediate node is at the second potential level.
The fourth first conductivity type transistor is conductive when the third intermediate node is at the first potential level, and is non-conductive when the second intermediate node is at the second potential level,
The fifth second conductivity type transistor is non-conductive when the third intermediate node is at the first potential level, and is conductive when the third intermediate node is at the second potential level.
The fifth first conductivity type transistor is conductive when the reset signal is at the first potential level, and is non-conductive when the reset signal is at the second potential level.
2. The flip-flop circuit according to claim 1, wherein the sixth second conductivity type transistor is in a non-conductive state when the reset signal is at a first potential level, and is in a conductive state when the reset signal is at a second potential level. . The first conductivity type transistor is a P-channel transistor,
The flip-flop circuit according to claim 2, wherein the second conductivity type transistor is an N-channel transistor. The first potential level is a ground potential level;
The flip-flop circuit according to claim 3, wherein the second potential level is a power supply potential level. A data signal input terminal for inputting a data signal;
A synchronization signal input terminal for inputting a synchronization signal;
An output node formed to connect to an inverting output terminal and a non-inverting output terminal that performs an output opposite to the inverting output terminal;
A reset terminal for inputting a reset signal;
A first intermediate node;
A second intermediate node;
A third intermediate node;
First and second first conductivity type transistors connected in series and sequentially between a power supply potential and the first intermediate node;
A first second conductivity type transistor connected between the first intermediate node and a ground potential;
Fifth and third first conductivity type transistors connected in series and sequentially between the power supply potential and the second intermediate node;
Second and third second conductivity type transistors connected in series between the second intermediate node and the ground potential;
A fourth first conductivity type transistor connected between the power supply potential and the output node;
Fourth and fifth second conductivity type transistors connected in series between the output node and the ground potential;
A sixth second conductivity type transistor connected between the third intermediate node and the ground potential;
Have
Each of the first conductivity type transistors becomes conductive when the data signal is at a first potential level, and becomes non-conductive when the data signal is at a second potential level,
Each of the second conductivity type transistors is in a non-conductive state when the data signal is at a first potential level, and is in a conductive state when the data signal is at a second potential level. The first first conductivity type transistor is turned on when the data signal is at a first potential level, and is turned off when the data signal is at a second potential level,
The first second conductivity type transistor is non-conductive when the data signal is at a first potential level, and is conductive when the data signal is at a second potential level;
The second and third first conductivity type transistors are conductive when the synchronization signal is at a first potential level, and are non-conductive when the synchronization signal is at a second potential level,
The third and fourth second conductivity type transistors are non-conductive when the synchronization signal is at the first potential level, and are conductive when the synchronization signal is at the second potential level.
The second second conductivity type transistor is non-conductive when the first intermediate node is at the first potential level, and is conductive when the second intermediate node is at the second potential level.
The fourth first conductivity type transistor is conductive when the third intermediate node is at the first potential level, and is non-conductive when the second intermediate node is at the second potential level,
The fifth second conductivity type transistor is non-conductive when the third intermediate node is at the first potential level, and is conductive when the third intermediate node is at the second potential level.
The fifth first conductivity type transistor is conductive when the reset signal is at the first potential level, and is non-conductive when the reset signal is at the second potential level.
6. The flip-flop circuit according to claim 5, wherein the sixth second conductivity type transistor is in a non-conductive state when the reset signal is at a first potential level, and is in a conductive state when the reset signal is at a second potential level. . A data signal input terminal for inputting a data signal;
A synchronization signal input terminal for inputting a synchronization signal;
An output node formed to connect to an inverting output terminal and a non-inverting output terminal that performs an output opposite to the inverting output terminal;
A reset terminal for inputting a reset signal;
A first intermediate node;
A second intermediate node;
A third intermediate node;
First and second first conductivity type transistors connected in series and sequentially between a power supply potential and the first intermediate node;
A first second conductivity type transistor connected between the first intermediate node and a ground potential;
A third first conductivity type transistor connected between the power supply potential and the second intermediate node;
Second and third second conductivity type transistors connected in series between the second intermediate node and the ground potential;
A fourth first conductivity type transistor connected between the power supply potential and the output node;
Fourth and fifth second conductivity type transistors connected in series between the output node and the ground potential;
A fifth first conductivity type transistor connected between the power supply potential and the output node;
Have
Each of the first conductivity type transistors becomes conductive when the data signal is at a first potential level, and becomes non-conductive when the data signal is at a second potential level,
Each of the second conductivity type transistors is in a non-conductive state when the data signal is at a first potential level, and is in a conductive state when the data signal is at a second potential level. The first first conductivity type transistor is turned on when the data signal is at a first potential level, and is turned off when the data signal is at a second potential level,
The first second conductivity type transistor is non-conductive when the data signal is at a first potential level, and is conductive when the data signal is at a second potential level;
The second and third first conductivity type transistors are conductive when the synchronization signal is at a first potential level, and are non-conductive when the synchronization signal is at a second potential level,
The third and fourth second conductivity type transistors are non-conductive when the synchronization signal is at the first potential level, and are conductive when the synchronization signal is at the second potential level.
The second second conductivity type transistor is non-conductive when the first intermediate node is at the first potential level, and is conductive when the second intermediate node is at the second potential level.
The fourth first conductivity type transistor is conductive when the third intermediate node is at the first potential level, and is non-conductive when the second intermediate node is at the second potential level,
The fifth second conductivity type transistor is non-conductive when the third intermediate node is at the first potential level, and is conductive when the third intermediate node is at the second potential level.
8. The flip-flop circuit according to claim 7, wherein the fifth first conductivity type transistor is conductive when the reset signal is at a first potential level, and is non-conductive when the reset signal is at a second potential level. .

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