JP2007213641A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory capable of input/output of arbitrary parallel data of word width N and input/output of arbitrary serial data of digit width Nd. <P>SOLUTION: A memory cell comprising a parallel wordline, a serial wordline, a parallel bit line and serial bit line is arranged in a shape of a matrix and an address of the memory cell is assigned so as to be able to access a plurality of lines of memory cells by selecting one serial wordline. Thereby, a plurality of digit serial data can be inputted or outputted simultaneously to one memory. Also a plurality of data of arbitrary digit widths can be simultaneously processed by setting up a plurality of memories and arranging wiring of digit serial data in order. Consequently the memory capable of conversion of the digit width and input/output of parallel data and serial data can be provided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that performs conversion with a high data transfer bandwidth and can input and output parallel data and serial data.

  In current computer systems, the method of performing operations in units of words using parallel data is the mainstream. However, in the current state of semiconductor technology, it is expected that a method of performing arithmetic processing and data transfer in digit units smaller than word units will become the mainstream in the future due to the influence of wiring delay and delay difference between transistors.

  When data is transferred in units of words to such a system that processes in units of digits, a digit width conversion circuit (parallel-converts the word width into a certain digit width (or converts the digit width into a word width) in the prior art. A serial data conversion circuit) (see, for example, FIG. 4 of Japanese Patent Laid-Open No. 2000-82287).

  FIG. 16 is a diagram illustrating a configuration example of a system that handles different digit widths using a digit width conversion circuit.

  16A includes a memory 201 having a word width N, a digit serial arithmetic unit (or a system using the same) 202, a digit width conversion circuit 203 for converting a certain word width into a predetermined digit width, a buffer 204, A digit width conversion circuit 205 converts the digit width into a predetermined word width, and arrows indicate data.

  The memory 201 stores parallel data having a word width N, and the digit serial arithmetic unit in the arithmetic unit 202 handles the digit width Nd (N> = Nd). The buffer 204 is used in the digit width conversion circuit 203, and the buffer 206 is used in the digit width conversion circuit 205.

  The data 207 supplied from the memory 201 is output as data 208 having a digit width Nd by the digit width conversion circuit 203 and processed by the computing unit 202. The data 209 after processing by the computing unit 202 is converted to the original word width by the digit width conversion circuit 205 and output.

  In such a system, the memory 201 handles data in units of words, and the computing unit 202 performs processing in units of digits. Therefore, a digit width conversion circuit 203 is required between the memory 201 and the arithmetic unit 202 so that the arithmetic unit 202 can perform processing.

A system as shown in FIG. 16B is also known. This system is a case where the bandwidth of the data 207 entering the digit width conversion circuit 203 is equal to the ability to be processed by the arithmetic unit 202 or the like in order to prevent a decrease in throughput. When the processing capability of the arithmetic unit 202 is increased and a plurality of pieces of data are requested at the same time, the bandwidth of the data 207 from the memory 201 and the bandwidth of the data 208 after the digit width conversion circuit 203 can be made equal.
JP2004-110421

  In the prior art, a system that handles different digit widths using a digit width conversion circuit has been developed. However, there are problems that cannot be compatible with a decrease in throughput and an increase in circuit scale associated with data conversion.

  For example, in the system as shown in FIG. 16A, the bandwidths of the data 207 and 208 and the data 209 and 210 differ depending on the input / output of the digit width conversion circuits 203 and 205 for enabling the processing by the arithmetic unit 202. For this reason, the throughputs before and after the digit width conversion circuits 203 and 205 are not equal. In other words, even if the bandwidth output from the memory 201 is large, all the supplied data is not processed at a time, resulting in waste, and the throughput between the memory 201 and the computing unit 202 is reduced. .

  In the case of FIG. 16B, in order to supply a plurality of data at the same time, a buffer 204 for storing all the data 207 from the memory 201 is required. Therefore, there is a problem that the amount of hardware increases.

  Further, when the supply amount from the memory 201 is increased, the number of data 209 output from the computing unit 202 also increases, and a buffer 206 for storing all the data 209 is required. For this reason, the amount of hardware also increases in this case.

  For example, in the case of the system shown in FIG. 16A using the 1-port memory 201 having the word width N = 32 bits and the arithmetic unit 202 having the digit width Nd = 2, the throughput between the memory 201 and the arithmetic unit 202 is reduced. As a result of the calculation, data with a word width N = 32 bits is converted into data (2 bits × 16 pieces) each having a width of Nd = 2 bits, so that the throughput is simply 1/16. Accordingly, the throughput decreases before and after the digit width is converted.

  On the other hand, in the case of increasing the buffer in FIG. 16B, since one word of data sent from the memory 201 is 32 bits, a buffer for storing 32 data is necessary to hold the data. If the memory bandwidth is equal to the processing capacity of the computing unit, the number of data to be supplied is 16, so 512 [32 bits × 16 (pieces)] buffers are required, increasing the amount of hardware. End up.

  As described above, the technique using the conventional digit width conversion circuits 203 and 205 has a problem that it is impossible to simultaneously solve both a decrease in throughput and an increase in circuit scale.

  The present invention has been made in view of the above problems, and firstly, a plurality of parallel data word lines, a plurality of parallel data bit lines orthogonal to the parallel data word lines, and the parallel data word lines and parallel data bit lines. A plurality of serial data word lines and a plurality of serial data bit lines orthogonal to each other, and arranged at the intersections of the parallel data word lines and the parallel data bit lines, the parallel data word lines and the parallel data bit lines, and the serial data A memory cell connected to each of a word line and a serial data bit line; a memory cell array in which the memory cells are arranged in a matrix; first data line selection means connected to the parallel data word line; and Select second data line to connect A stage, third data line selection means connected to the serial data word line, fourth data line selection means connected to the serial data bit line, a parallel data input / output circuit, and a serial data input / output circuit. And when the third data line selection unit selects one serial data word line, the fourth data line selection unit selects the serial data bit line connected to at least one row of the memory cells. This is solved by transmitting at least one digit serial data.

  Second, a plurality of parallel data word lines, a plurality of parallel data bit lines orthogonal to the parallel data word lines, a plurality of serial data word lines orthogonal to the parallel data word lines and the parallel data bit lines, and A plurality of serial data bit lines are arranged at intersections of the parallel data word line and the parallel data bit line, and are connected to the parallel data word line and the parallel data bit line, and the serial data word line and the serial data bit line, respectively. A memory cell, a memory cell array in which the memory cells are arranged in a matrix, first data line selection means connected to the parallel data word line, second data line selection means connected to the parallel data bit line, Serial data word line Common to the third data line selection means to be connected, the fourth data line selection means to be connected to the serial data bit line, the parallel data input / output circuit, the serial data input / output circuit, and the memory cells in a plurality of consecutive rows. A bit line selector connected to the serial data bit line of the memory cell and selecting the memory cell of one row of the plurality of rows, and the memory cell of the memory cell common to the memory cells of other consecutive rows Another bit line selector that is connected to a first serial data bit line and selects one of the memory cells in the other plurality of rows, and the third data line selection means converts the memory cells to one column. When selecting the serial data word line to be connected, the bit line selector and the other bit line selector connect to the memory cells in a plurality of rows. Select serial serial data bit lines, it solves by performing transmission of a plurality of digit serial data.

  According to the present invention, a memory capable of inputting / outputting parallel data having an arbitrary word width N and serial data having an arbitrary digit width Nd can be provided.

  For example, in the case of a system that handles different digit widths, the memory of this embodiment is used instead of using the conventional digit width conversion circuit. As a result, it is possible to solve both of a decrease in throughput and an increase in circuit scale, which are problems in the conventional technology. Furthermore, the throughput can be easily adjusted.

  Specifically, in the conventional memory, it was necessary to provide a digit width conversion circuit for input / output, but in this embodiment, paying attention to the affinity between the memory and the circuit, the digit width is obtained by inputting / outputting data to / from the memory. Can be converted. As a result, it is not necessary to separately provide a digit width conversion circuit, and the circuit scale can be reduced. Thereby, the following effects are acquired.

  First, when data is written to or read from the memory, it is possible to change whether the data is read from the most significant bit or the least significant bit without reducing the throughput. Conventionally, since it is necessary to store data once in a buffer, there is a problem that the amount of hardware increases and throughput decreases. However, since this embodiment does not require a buffer, this problem can be solved.

  Second, the configuration of the required digit width can be easily designed. In the present embodiment, when the serial data input / output is set to the digit width Nd, there are the following two methods. That is, when one memory is used, the memory cell array is divided into Nd, and wirings are respectively connected to the same corresponding row of the divided memory cell array. When Nd memories are used, wiring is connected to the same corresponding row of each memory. Thus, a memory corresponding to serial data having an arbitrary digit width Nd can be easily designed.

  By using the memory of this embodiment in a system that handles devices having different digit widths, a system that does not require a digit width conversion circuit can be constructed.

  Third, a plurality of serial data can be input / output to / from the memory simultaneously in digit units. That is, a plurality of rows of memory cells are set as one set, and a bit line selector for selecting a serial data bit line connected to the memory cell is connected to each set. The number of serial data that can be input / output simultaneously is the same as the number of bit line selectors. Therefore, the memory configuration itself is not changed, and it is designed to have an arbitrary memory bandwidth by appropriately selecting the digit width Nd by changing the number of bit line selectors, the number and wiring of memories used, and the address for serial data. Conversion can be performed with a high data transfer bandwidth.

  Fourth, by designating the data read start position, it becomes possible to shift or rotate the data. Therefore, it is possible to prevent an increase in the amount of hardware that occurs when these functions are realized in the system or the like.

  Fifth, by extending the serial data word line stepwise, it is possible to perform pipeline processing of writing parallel data and reading serial data, or writing serial data and reading parallel data.

  Sixth, data written in parallel data can be read out as either serial data or parallel data. Further, data written as serial data can be read out as either serial data or parallel data. Furthermore, writing / reading with parallel data and writing / reading with serial data can be performed simultaneously.

  An embodiment of the present invention will be described with reference to FIGS. In this embodiment, a semiconductor memory device will be described by taking as an example a memory 100 in which each memory cell is composed of an SRAM (Static Random Access Memory).

  First, a first embodiment will be described with reference to FIGS.

  FIG. 1 is a schematic diagram showing the memory of this embodiment. The memory 100 of this embodiment includes a parallel data word line wl, a parallel data bit line bl, a serial data word line wl_s and a plurality of serial data bit lines bl_s, a memory cell 400, a memory cell array 4, and a first data Line selection means 1, second data line selection means 5, third data line selection means 3, fourth data line selection means 8, serial data input / output control circuit 2, parallel data input / output circuit 6, And a serial data input / output circuit 9.

  A parallel data word line (hereinafter referred to as parallel word line) wl and a parallel data bit line (hereinafter referred to as parallel bit line) bl are data lines through which parallel data P is transmitted. A plurality of these are provided, and are arranged orthogonal to each other.

  A memory cell 400 is arranged at the intersection of the parallel word line wl and the parallel bit line bl. That is, the memory cells 400 are arranged in a matrix of m rows × n columns and constitute one memory cell array 4.

  A serial data word line (hereinafter referred to as serial word line) wl_s and a serial data bit line (hereinafter referred to as serial bit line) bl_s are data lines through which serial data S is transmitted. A plurality of these are provided, and are arranged orthogonal to each other.

  The parallel data P is input / output to / from the memory cell 400 selected by the parallel data designation address P_Addr. The parallel data designation address P_Addr includes a parallel data row designation address Addr_0 and a parallel data column designation address Addr_1.

  The serial data S is input / output to / from the memory cell 400 selected by the serial data designation address S_Addr. The serial data designation address S_Addr includes a serial data row designation address Addr_3 and a serial data column designation address Addr_2.

  Although details of the memory cell 400 will be described later, the serial bit line bl_s is provided in parallel with the parallel word line wl and is orthogonal to the parallel bit line bl. The serial word line wl_s is provided in parallel with the parallel bit line bl and is orthogonal to the parallel word line wl.

  The parallel word line wl is connected to a parallel data row address decoder (hereinafter referred to as a parallel row decoder) 1 which is a first data line selection means. The parallel row decoder 1 receives a parallel data row designation address Addr_0. The parallel data row designation address Addr_0 is, for example, 4 bits.

  On the other hand, the parallel bit line bl is connected to the second data line selection means 5. The second data line selection means 5 includes a parallel data column address decoder (hereinafter referred to as parallel column decoder) 50 and a plurality of parallel data bit line selectors (hereinafter referred to as parallel bit line selectors) 51. Specifically, the parallel bit lines bl are connected to one parallel bit line selector 51 as a set of a plurality of columns. The second data line selection means 5 receives the parallel data column designation address Addr_1. The column designation address Addr_1 for parallel data is input in 2 bits, for example, and is converted into 4 bits by the parallel column decoder 50.

  The serial word line wl_s is connected to the third data line selection unit 3. The third data line selection means 3 includes a serial data column address decoder (hereinafter referred to as serial column decoder) 30 and a plurality of serial data word line selectors (hereinafter referred to as serial word line selectors) 31. Specifically, the serial word line wl_s is connected to one serial word line selector 31 as a set of a plurality of columns. The third data line selection means 3 is supplied with a serial data column designation address Addr_2. The column designation address Addr_2 for serial data is 2 bits, for example.

  The serial bit line bl_s is connected to the fourth data line selection unit 8. The fourth data line selection means 8 includes a serial data row address decoder (hereinafter referred to as serial row decoder) 80 and a plurality of serial data bit line selectors (hereinafter referred to as serial bit line selectors) 81. Specifically, the serial bit line bl_s is connected to one serial bit line selector 81 as a set of a plurality of rows. The fourth data line selection means 8 receives the serial data row designation address Addr_3. The serial data row designation address Addr_3 is, for example, 2 bits.

  The serial data input / output control circuit 2 is connected to the third data line selection means 3 and receives a read / write bit start position designation signal Act_set and an LSB / MSB selection signal LM_SEL for designating the data read direction.

  The parallel data input / output circuit 6 is connected to the second data line selection means 5 and receives parallel data write enable P_WE and parallel data read enable P_RE for controlling writing and reading.

  The serial data input / output circuit 9 is connected to the fourth data line selection means 8 and receives serial data write enable S_WE and serial data read enable S_RE for controlling writing and reading.

  A parallel data transmission line 11 is connected to the parallel bit line selector 51 via the parallel data input / output circuit 6. The parallel data transmission lines 11 correspond to the parallel bit line selector 51 and are provided in the same number.

  A serial data transmission line 12 is connected to the serial bit line selector 81 via a serial data input / output circuit 9. The serial data transmission wirings 12 correspond to the serial bit line selectors 81 and are provided in the same number.

  With reference to FIG. 2, the memory cell 400 of the present embodiment will be described. FIG. 2A is a circuit diagram illustrating an outline of a plurality of memory cells 400 included in the memory cell array 4, and FIG. 2B is a circuit diagram illustrating an example of one memory cell 400.

  The parallel word line wl and the parallel bit line bl extend orthogonally, the serial word line wl_s extends orthogonally to the parallel word line wl, and the serial bit line bl_s extends orthogonally to the parallel bit line bl. .

  The memory cell 400 is arranged at the intersection of the parallel word line wl and the parallel bit line bl, and connects the pass transistors Tr3 and Tr4 in addition to the transistors Tr1 and Tr2 constituting the flip-flop circuit. Transistors Tr1 and Tr2 have gates connected to parallel word line wl, and sources (or drains) connected to two parallel bit lines bl, respectively. The pass transistors Tr3 and Tr4 have gates connected to the serial word line wl_s and respective sources (or drains) connected to the two serial bit lines bl_s. The drains (or sources) of the pass transistors Tr3 and Tr4 are connected to the drains (or sources) of the transistors Tr1 and Tr2 of the flip-flop circuit.

  Referring to FIG. 2B, parallel data is transmitted to parallel bit line bl when parallel word line wl is at the H level. As a result, one bit can be written to or read from the memory cell 400. The serial data is transmitted to the serial bit line bl_s when the serial word line wl_s is at the H level. As a result, one bit can be written to or read from the memory cell 400.

  When the memory cell array 4 is configured by the memory cells 400, the memory cells 400 arranged in the row direction share the parallel word line wl, and the memory cells 400 arranged in the column direction share the serial word line wl_s. Accordingly, data can be read and written in the memory cell 400 arranged in a matrix in two types of directions, the row direction and the column direction.

  For example, when data for one word is stored in the row direction, one bit of parallel data can be read by reading the data in the column direction.

  Here, since SRAM is shown as an example, two parallel bit lines bl and two serial bit lines bl_s are arranged for one memory cell 400.

  As described above, in this embodiment, each memory cell 400 can be accessed in the row direction and the column direction, and both parallel data and serial data (digit serial data) can be read and written. Further, by devising the address assignment of each memory cell 400, a plurality of memory cells 400 can be accessed simultaneously. Thereby, a plurality of digit serial data can be simultaneously input or output to one memory cell array 4. This will be described below.

  3 to 5 are diagrams showing an example of an address assigned to the memory cell 400 according to the present embodiment and an access method thereof. 3 and 4 are diagrams for explaining addresses assigned to the memory cell 400, and FIG. 5 shows a method of referring to the parallel data and serial data memory cell 400. FIG. Assume that memory cells 400 are arranged in 16 rows and 16 columns.

  As shown in FIG. 3, in the case of this embodiment, the memory cell 400 is assigned a 6-bit address.

  Although the same memory cell 400 is used, the addresses (bit positions) referred to by the parallel data and the serial data are different. That is, when referring to parallel data, it is a 6-bit designated address for parallel data P_Addr. The upper 2 bits of the parallel data designation address P_Addr are a parallel data column designation address Addr_1 used when a parallel data column is selected. The lower 4 bits are a parallel data row designation address Addr_0 which is used when a parallel data row is selected.

  On the other hand, when referring to serial data, a 4-bit serial data designation address S_Addr is used. That is, the upper 2 bits of the serial data specification address S_Addr are the serial data column specification address Addr_2 used when selecting the serial data column, and the third and fourth bits select the serial data row. This is the row designation address Addr_3 for serial data used in the process.

  That is, in this embodiment, the upper bits of the row address assigned for parallel data and the row address assigned for serial data are the same, and the serial data row designation address Addr_3 is higher than the parallel data row designation address Addr_0. The same address as 2 bits is used.

  Further, the column address assigned for serial data is the same as the column address assigned for parallel data, and the same address is used for the serial data column designation address Addr_2 and the parallel data column designation address Addr_1.

  As shown in FIG. 4, the memory cells 400 are arranged in 16 rows × 16 columns, for example. In the figure, the dotted line, the thin line, the alternate long and short dash line, and the alternate long and two short dashes line coincide with the frame in FIG.

  In the present embodiment, when processing is performed with serial data, it is necessary to enable processing with continuous data, and therefore address allocation is devised.

  Addresses are assigned to the rows of parallel data so that they can be selected by a group (one-dot chain line frame) in which a plurality of rows (for example, four rows) are a set and a thin line frame indicating each memory cell 400. That is, the address is assigned so that the upper 2 bits of the 4-bit parallel data row designation address Addr_0 can refer to the address of the thin line frame, and the lower 2 bits can refer to the address of the alternate long and short dash line.

  The parallel data column is assigned an address so that it can be selected by a dotted frame. That is, the address is assigned so that the address of the dotted frame can be referred to by the parallel data column designation address Addr_1. As will be described later, the parallel data columns are grouped into a set of a plurality of columns (for example, four columns) by the second data line selection means 5, and a plurality of dotted frames are formed by one parallel data column designation address Addr_1. A column (one column for each group) can be selected.

  Note that the change in the arrangement of the addresses allocated for parallel data changes the parallel data transmission wiring (not shown here).

  On the other hand, the serial data row is assigned an address so that it can be selected by a two-dot chain line, that is, the serial data row designation address Addr_3 can refer to the address of the two-dot chain line. The column is assigned an address so that it can be selected by a dotted frame, that is, the address of the dotted frame can be referred to by the serial data column designation address Addr_2.

  As will be described later, the serial data rows are grouped into a set of a plurality of rows (for example, 4 rows) by the fourth data line selection means 8, and each serial data row designation address Addr_3 is used for each set. One row is selected. The serial data row designation address Addr_3 is decoded into a signal indicating which row of each set is selected.

  Similarly, the rows of serial data are grouped into a set of a plurality of columns (for example, 4 columns) by the third data line selection means 3, and one column is selected by the serial data column designation address Addr_2. Thereby, a plurality of memory cells 400 arranged in the same row of each set of the selected columns can be accessed simultaneously.

  FIG. 5 shows a memory cell 400 and an access method with parallel data and serial data. The address assignment is the same as in FIG.

  FIG. 5A shows the case of parallel data. For example, the parallel data row designation address Addr_0 is set to “0000” and the parallel data column designation address Addr_1 is set to “00”.

  A set of four rows surrounded by a one-dot chain line is a set in which the addresses referred to by the lower 2 bits of the row designation address Addr_0 for parallel data match. That is, one set (four rows) surrounded by a one-dot chain line with the parallel data row designation address Addr_0 and the first and second bits of the assigned address being “00” is selected (a). After that, among the memory cells 400 surrounded by a dotted frame by the parallel data column designation address Addr_1, a plurality of columns in which the fifth bit and the sixth bit of the assigned address are the same address “00” are selected. Specifically, since the memory cells 400 are grouped in one set of four columns, the first column is selected for each set.

  As a result, 4 × multiple columns of memory cells 400 surrounded by a thick solid frame are selected (b). Further, a plurality (one set each) of which the third bit and the fourth bit of the address assigned to each of the memory cells 400 within the bold line frame by the upper 2 bits of the parallel data row designation address Addr_0 are “00”. ) Memory cell 400 is selected. As a result, the memory cell 400 indicated by hatching is selected (c), and parallel data is read or written.

  That is, when writing parallel data having a predetermined word width, one word is distributed and stored in a plurality of hatched memory cells 400. In the case of reading, the memory cell 400 with hatching is accessed, and the bits of each memory cell 400 are combined to read one word of data. Details of this will be described later.

  On the other hand, FIG. 5B shows a case where serial data is accessed. For example, the serial data row designation address Addr_3 (same as the upper 2 bits of the parallel data row designation address Addr_0) is set to “00” for serial data use. The column designation address Addr_2 is set to “01”. These are also decoded into signals indicating which row or column is selected for each group.

  The first column is selected for each set (four columns and one set) of memory cells 400 surrounded by a dotted frame by the serial data column designation address Addr_2. As a result, a plurality of columns of memory cells in which the fifth and sixth bits of the assigned address are the same (“00”) are selected (a). Next, the second row surrounded by a two-dot chain line is selected for each of the four rows and one set by the row designation address Addr_3 for serial data. As a result, the memory cells 400 in a plurality of rows having the same address (“01”) in the third and fourth bits of the allocated address are selected (b). In this manner, as indicated by hatching, a plurality of memory cells 400 (thick line: c) are selected by one serial data row designation address Addr_3 per column.

  That is, by connecting serial data transmission lines to each of them, a plurality (four in this case) of digit serial data can be read or written simultaneously from one memory cell array 4 for each column.

  The operation of the memory 100 of this embodiment will be described with reference to FIGS.

  The memory 100 is the same as that shown in FIG. 1, but the memory cell array 4 has 16 rows × 16 columns as an example. The bit width of 1-word data is 4 bits, and the number of data output is 1 entry for parallel data. Although the number of serial data outputs can be changed in this embodiment, the operation will be described first with four entries.

  Referring to FIG. 1, one row of parallel data P is selected by a parallel row decoder 1, and four columns (one column in each set) are selected by second data line selection means (parallel column decoder 50, parallel bit line selectors 51a to 51d). Is selected, and the four memory cells 400 can be accessed (see FIG. 5A). This will be described in detail below.

  The parallel row decoder 1 receives a 4-bit parallel data row designation address Addr_0. The parallel row decoder 1 selects one of the 16 rows based on the parallel data row designation address Addr_0.

  FIG. 6 is an enlarged view of the second data line selection means 5.

  As shown in FIG. 6A, the parallel column decoder 50 receives the parallel data column designation address Addr_1. The parallel data column designation address Addr_1 is 2 bits, but is decoded by the parallel column decoder 50 into 4 bits. This 4-bit signal controls which column of a set of four columns is selected and connected to the parallel data input / output circuit 6.

  The second data line selection means 5 has a plurality (here, four) of parallel bit line selectors 51a to 51d. The parallel bit line selectors 51a to 51d are provided for each set of four columns of memory cells 400 as one set. The four address signal lines 13 are connected to the parallel bit line selectors 51a to 51d.

  Addresses are assigned to the memory cells 400 as shown in FIG. 3, and a part of the addresses can be shared for each group in the column selection. That is, the same column can be selected by the parallel bit line selectors 51a to 51d by the same parallel data column designation address Addr_1. For example, when the parallel data column designation address Addr_1 is “01”, it is decoded to “0100” by the parallel column decoder 50 and inputted to the four address signal lines 13 respectively. Then, the second column of each set is selected. At this time, the third bit and the fourth bit of the selected memory cell 400 in the second column are assigned to the same address “01” (FIG. 4: thin line). Can be processed.

  By making parallel data access multiple ports, data of 1 entry × number of ports can be processed. Further, the word width can be changed by changing the number of columns in one set.

  FIG. 6B shows a case where two rows are set as one set. In this case, since it is sufficient to control which of the two columns is selected, the number of the address signal lines 13 may be two, and the parallel data column designation address Addr_1 is 1 bit. One word = 8 bits can be processed with one entry of data.

  That is, the amount of data that can be processed at one time is (number of columns of memory cells 400 / number of columns allocated to one set) bits.

  Referring to FIG. 1, parallel data input / output circuit 6 designates the direction of data. The second data line selection means 5 (parallel bit line selectors 51a to 51d) controls which column the data is transmitted for each group, and the parallel data input / output circuit 6 determines the data direction (reading or writing). Control. The parallel data input / output circuit 6 determines the value of the memory cell 400 from the 2-bit potential difference information by a sense amplifier and converts it to 0 or 1. Here, the 2-bit potential difference information is 2 bits transmitted to the two parallel bit lines bl connected to each memory cell 400 (see FIG. 2B).

  The direction of data is controlled by a parallel data write enable P_WE and a parallel data read enable P_RE. When the parallel data write enable P_WE = 1, the data is transmitted to the two parallel bit lines bl and the data is stored in one memory cell 400. When the parallel data read enable P_RE = 1, data is read from the two parallel bit lines bl of the memory cell 400 specified by the address.

  For serial data input / output, the serial input / output control circuit 2 determines the serial data read start position, the third data line selection means 3 selects one column, and the fourth data line selection means 8 selects a plurality of rows (each 1 set). Thus, serial data can be input / output for a plurality of memory cells. This will be described in detail below.

  FIG. 7 is an enlarged view showing the serial input / output control circuit 2 and the third data line selection means 3.

  The serial input / output control circuit 2 of the present embodiment determines the start position for reading (writing: the same applies hereinafter) serial data by decoding the read or write bit start position designation signal Act_set. The LSB / MSB selection signal LM_SEL specifies the direction in which data is read.

  The bit start position designation signal Act_set is input as 2 bits, and any one bit is decoded into a 4-bit signal of “1”. For example, the input “00” is decoded to “1000”, “01” is decoded to “0100”, “10” is decoded to “0010”, and “11” is decoded to “0001”.

  The third data line selection means 3 is supplied with a 2-bit serial data column designation address Addr_2. The serial data column designation address Addr_2 is 2 bits, but is decoded by the serial column decoder 30 into 4 bits in the same manner as the bit start position designation signal Act_set. This 4-bit signal controls which column is selected and connected to the serial input / output control circuit 2.

  The third data line selection means 3 has a plurality (four in this case) of serial word line selectors 31a to 31d. The serial word line selectors 31a to 31d are provided for each set of four columns of memory cells 400 as one set. The four address signal lines 14 through which the decoded 4-bit signal is transmitted are connected to the serial word line selectors 31a to 31d.

  The memory cell 400 is assigned an address as shown in FIG. 3, and a part of the address can be shared for each group. That is, the same column can be selected by the serial word line selectors 31a to 31d by the same serial data column designation address Addr_2. For example, when the column designation address Addr_2 for serial data is “01”, it is decoded to “0100” by the serial column decoder 30 and inputted to the four address signal lines 14 respectively. The second column from the right in this case is selected. This selected column is a column (FIG. 4: dotted line frame) in which the same address is assigned to the fifth and sixth bits. Here, the 5th and 6th bits of the selected memory cells 400 in the second column are assigned to the same address “10”. Although only one row of memory cells 401, 402, 403, 404 is shown in the figure, all of the memory cells 400 in the same column as these are selected.

  In a state where the serial word line selectors 31a to 31d have selected the second column, a plurality of rows (one set of four rows and one row) are selected by the fourth data line selection means 8 described later. For example, when the first row of each group is selected, memory cells 401, 402, 403, and 404 with thick frames are selected. The selected row is a row surrounded by a two-dot chain line in FIG. 4B. Although illustration is omitted here, the first row of another set is also selected in the same manner.

  In this state, the serial input / output control circuit 2 selects one of the serial word line selectors 31a to 31d (one set and one column). That is, when the bit start position designation signal Act_set is, for example, “00”, it is decoded to “1000” and the first set of serial word line selectors 31a is selected. As a result, the memory cell 401 in the second column selected by the serial word line selector 31a is selected. At this time, the memory cells in the second column selected by the serial word line selector 31a are selected in the first row for each set of four rows (see the thick frame in FIG. 4B). Therefore, by connecting four serial data transmission lines to the serial data input / output circuit 9, a plurality (four) of digit serial data can be input / output simultaneously from one memory cell array 4.

  The control signal output from the serial input / output control circuit 2 is every cycle. Therefore, in the next cycle, a signal for selecting the second set of serial word line selectors 31b is generated in the serial input / output control circuit 2 without changing the selection of the second column of each set and the first row of each set. For each set, the memory cell 402 in the first row and the second column selected by the serial word line selector 31b is selected.

  When all the serial word line selectors 31a to 31d are sequentially selected by designating the bit start position designation signal Act_set once, one column is selected from each set by the new serial data column designation address Addr_2. One row is selected from each set by the serial data row designation address Addr_3.

  Although not described, the serial input / output control circuit 2 is synchronized with the clock, and therefore requires a system clock and a system reset.

  As described above, serial data read / write is controlled by sequentially activating the serial word line wl_s every cycle. Therefore, if the direction in which the serial word line wl_s is activated is controlled, the serial data is read / written. You can specify the direction.

  In order to specify the direction in which data is read and written, a signal (LSB, MSB selection signal LM_SEL) is input to the serial input / output control circuit 2 to specify from which direction processing is to be performed. Thereby, the direction in which serial data is read and written can be arbitrarily designated. That is, reading / writing can be performed from either the LSB (Least Significant bit) and the MSB (Most Significant bit).

In addition, after the reading start position is designated and reading is completed up to the end of the data, the data is shifted or rotated by reading from the head of the data that has not been read yet. The read data is shifted by using the serial data read enable signal S_RE.
The data shift method designates the read start position, and the data is read only when the serial data read enable signal S_RE is “1” (H level). When the serial data signal is “0” (L level), the determination can be made by a system or device outside the memory 100, and the output from the memory 100 can be realized as 0.

  FIG. 8 is an enlarged view of the fourth data line selection means 8.

  As shown in FIG. 8A, the serial row decoder 80 receives the serial data row designation address Addr_3. The serial data row designation address Addr_3 is 2 bits, but is decoded by the serial row decoder 80 into 4 bits. This 4-bit signal controls which column is selected and connected to the serial data input / output circuit 9.

  The fourth data line selection means 5 has a plurality (four in this case) of serial bit line selectors 81a to 81d. The serial bit line selectors 81a to 81d are provided for each set of four rows of the memory cells 400 as one set. The four address signal lines 15 are connected to the serial bit line selectors 81a to 81d.

  The memory cell 400 is assigned an address as shown in FIG. 3, and a part of the address can be shared for each group. That is, the same column can be selected by the serial bit line selectors 81a to 81d by the same serial data row designation address Addr_3. For example, when the row designation address Addr_3 for serial data is “01”, it is decoded to “0100” by the serial row decoder 80 and input to the four address signal lines 15 respectively. Then, the second row of each set is selected. At this time, the third bit and the fourth bit of the selected memory cells 400 in the second row are assigned to the same address (a frame indicated by a two-dot chain line in FIG. 4B). That is, as shown in FIG. 8, when one column is selected by the serial data input / output control circuit 2 and the third data line selection means 3, it becomes possible to access four memory cells at the intersecting positions. Serial data can be processed simultaneously.

  That is, the number of serial data to be processed at the same time can be changed by changing the configuration of the serial bit line selectors 81a to 81d (one set of rows).

  FIG. 8B shows a case where two rows are taken as one set. In this case, since it is sufficient to control which of the two rows is selected, one address signal line 15 is sufficient, and the serial data row designation address Addr_3 is 1 bit. Thereby, the number of serial data processed at a time can be changed to 8 (8 bits), and the bandwidth can be easily adjusted.

  That is, the number of serial data that can be processed at one time is (number of memory cell rows / number of rows allocated to one set) (bits), and the number of rows in the memory cell array is maximum.

  The operation of the serial data input / output circuit 9 is the same as that of the parallel data input / output circuit 6. That is, the serial data input / output circuit 9 is connected to the fourth data line selection means 8 (serial bit line selectors 81a to 81d), and controls the data direction by the serial data write enable S_WE and the serial data read enable S_RE. . Further, the value of the memory cell 400 is judged from the 2-bit potential difference information by the sense amplifier and converted to 0 or 1. Here, the 2-bit potential difference information is 2 bits transmitted to the two serial bit lines bl_s connected to each memory cell 400 (see FIG. 2B). The rest of the configuration is the same as that of the parallel data input / output circuit 6, and thus the description thereof is omitted.

  As described above, the memory 100 according to this embodiment uses the parallel data column designation address Addr_1 and the serial data column designation address Addr_2 as the same address, and the serial data row designation address Addr_3 is higher than the parallel data row designation address Addr_0. By making it the same as 2 bits, it is possible to input / output parallel data and input / output serial data in one memory cell array 4. In addition, stored parallel data can be read out as serial data, and vice versa. Furthermore, a plurality of (bit) digit serial data can be processed simultaneously in one memory cell array 4.

  That is, by arranging a plurality of memory cell arrays 4, a plurality of serial data having an arbitrary digit width Nd can be processed simultaneously. This will be described below.

  9 to 12 show a second embodiment. The second embodiment is a case where a plurality of serial data having a digit width Nd is simultaneously processed. As an example, a case where parallel data of 1 word N bits is stored in the memory 100 and output with a digit width Nd will be described. To do.

  When processing serial data having a digit width Nd, Nd memories 100 of the first embodiment are used. One word of parallel data is distributed and stored in Nd memories 100.

  FIG. 9 shows a method of distributing and storing 1-word parallel data in Nd memories 100.

  Nd memory memories 100_i (i = 1, 2,... Nd) are arranged, and only a predetermined bit position of one word is stored in the first memory 100_1. Here, in the case of the first memory 100_1, the predetermined bit position is obtained by a calculation result obtained by substituting a natural number starting from 0 for i in a sequence formula of Nd × i. That is, only the bit position Nd × i bits of one word is stored in the memory 100_1.

  Similarly, only the bit position Nd × i + 1 bit of the same 1 word is stored in the second memory 100_2, only the bit position Nd × i + 2 bit is stored in the third memory 100_3,... Stores only bit position Nd × i + (Nd−1)) bits.

  For example, when serial data having a digit width Nd = 4 is output, four memories 100_1 to 100_4 are used. In this case, since the first memory 100_1 is 4i, the data at the bit position {0, 4, 8, 12...} Of one word is stored in the memory cell 400. Since the second memory 100_2 is 4i + 1, the bit position {1, 5, 9, 13...} Is stored, and the third memory 100_3 is 4i + 2, so the bit position {2, 6, 10 , 14...} Bits and 4i + 3 in the fourth memory 100_4, so that bit positions {3, 7, 11, 15. Such distribution is performed by the parallel data transmission wiring 11.

  When the memories 100_1 to 100_Nd stored by such a method are referred from the column direction as indicated by arrows, the bit positions are continuous. That is, referring to the column in which the bit position 0 bit is stored in the first memory 100_1, the second memory 100_2 stores the bit position 1 bit in the same column, and the third memory 100_3 stores the bit position 2 bits. Is stored. The bit position (Nd−1) bits are stored in the Nd-th memory 100_Nd.

  That is, when one digit serial data is read from each memory 100, it is possible to simultaneously read from bit position 0 bit to bit position (Nd-1) bits. Therefore, serial data having a digit width Nd can be read by arranging serial data transmission wirings connected to each memory 100.

  In addition, a single memory 100 can process a plurality of digit serial data by sharing a part of an address as in the first embodiment. For example, as shown in the figure, the hatched memory cells 400 can be simultaneously accessed for each memory 100, so that a plurality of digit serial data can be simultaneously output from one memory 100. Accordingly, by connecting a plurality of serial data transmission lines to the memories 100_1 to 100_Nd and arranging the serial data transmission lines so that Nd digit serial data output from the memories 100_1 to 100_Nd are continuous, the digit width Nd It is possible to process a plurality of serial data simultaneously.

  This will be described more specifically with reference to FIG. In this example, parallel data of 32 bits per word is stored in the memory 100 and output with a digit width Nd = 2. The memory cell array 4 is assumed to be composed of 16 rows × 16 columns. The memory 100 is the same as in the first embodiment, and addresses are assigned to the memory cells 400 as shown in FIG. Although not shown, the parallel bit lines bl are connected to, for example, four parallel bit line selectors 51a to 51d in a set of four columns. The serial bit line bl_s is connected to each of the four serial bit line selectors 81a to 81d in a set of four rows, and the serial word line wl_s is connected to each of the four serial word line selectors 31a to 31d in a set of four columns. (See FIG. 1).

  Since the digit width Nd = 2, two memories 100_1 and 100_2 are used. The number in each memory cell 400 indicates the bit position of one word. That is, the even bits of one word are distributed and stored in the memory 100_1, and the odd bits of one word are distributed and stored in the memory 100_2. Similarly, the other one word data is distributed and stored in the same row and the same column position of each of the memories 100_1 and 100_2.

  The method for storing 400 in each memory cell is the same as in the first embodiment. The data is stored in the memory cell 400 at the intersection of the parallel word line wl selected by the parallel row decoder and the parallel bit line bl selected by the parallel bit line selectors 51a to 51d.

  For example, when serial data is read from the memory 100_1, the serial word line selectors 31a to 31d use the input serial data column designation address Addr_2 to select one column (× 4 sets) from each of four columns and one set of memory cells. Is selected (dotted line in FIG. 4B). The serial bit line selectors 81a to 81d select one row from a set of four rows and one memory cell by the row designation address Addr_3 for serial data (FIG. 4 (B) two-dot chain line). At this time, the address of the memory cell referred to by the serial data row designation address Addr_3 is shared by each row of the serial bit line selectors 81a to 81d, so that one row × 4 for all the serial bit line selectors 81a to 81d. A set (for example, the top row of four rows and one set) is selected at the same time.

  In this state, one of the serial word line selectors 31a to 31d is selected under the control of the serial input / output control circuit 2 based on the bit start position designation signal Act_set, and 1 column × 4 rows (1 column × (1 row × 4 sets). )) Memory cell 400 becomes accessible. The serial data input / output circuit 9 is connected to serial data transmission wirings 12 corresponding to the serial bit line selectors 81a to 81d, respectively, so that four (1 bit × 4 rows) digit serial data are stored in the memory 100_1. Is output.

  The memory 100_2 has the same configuration as the memory 100_1, and is processed simultaneously with the memory 100_1, and four (1 bit × 4 rows) digit serial data is also output to the memory 100_2. Therefore, by arranging the serial data transmission lines so that the digit serial data of the memory 100_1 and the memory 100_2 are continuous, four serial data having a digit width Nd = 2 can be output simultaneously.

  Specifically, referring to the memory cells from the column direction in the figure, the data is continuous as {0, 1}, {2, 3}, {4, 5},. Therefore, by reading serial data from the column direction and arranging the two serial data transmission wirings 12, 2-bit data can be output simultaneously.

  When serial data is processed with a digit width Nd = 4, four memories 100 are used so that when the serial word line of one column becomes active, data from the 0th bit to the 3rd bit is read simultaneously. Store data in. That is, the memory 100 capable of processing an arbitrary digit width Nd can be provided by changing the number of the memories 100. Further, the number of digit serial data simultaneously output from one memory 100 can be easily changed by changing the configuration of the serial bit line selectors 81a to 81d (the number of rows assigned to one set).

  In this way, by reading data in the same column, continuous data in digit units can be read at a time, so that the digit width can be converted. Further, when processing is performed in units of digits as described above, since a plurality of serial data can be processed simultaneously, the bandwidth at the input and output of the memory 100 can be easily adjusted. Therefore, it is possible to supply data without reducing the throughput before and after converting the digit width Nd of the data and without increasing the circuit scale.

  FIG. 11 shows another form of the memory 100 that outputs data with the digit width Nd = 2 shown in FIG.

  When serial data having a digit width Nd is processed, the memory cell array 4 may be divided into Nd by one memory 100. FIG. 13 shows a case of dividing into two.

  The upper memory cell array 4_1 stores even-numbered bits of one word, and the lower memory cell array 4_2 stores odd-numbered bits of one word.

  In this case, there are the following methods for selecting the memory cells 400 in the same row and column for the upper and lower memory cell arrays 4_1 and 4_2. First, as shown in the figure, the second data line selection means 5 is provided in each of the memory cell arrays 4_1 and 4_2, and both the divided memory cell arrays 4_1 and 4_2 share the serial word line. Then, the address (parallel data column designation address Addr_1) input to the second data line selection means 5 of the two memory cell arrays 4_1 and 4_2 is set to the same address. Since data writing is performed separately and simultaneously, two second data line selection means 5 are required, but only one third data line selection means 3 is required.

  Although the illustration of other methods is omitted, the second is to share the parallel word line used in the first data line selection means (parallel row decoder) 1 and the serial word line used in the second data line selection means 5. It is a method to do.

  Third, although the number of the fourth data line selection means 8 is one, the same address (serial data row designation address Addr_3) is input to the bit line selectors 81_1 and 81_2 of the respective memory cell arrays 4_1 and 4_2. is there.

  The rest is the same as in FIG. When changing the digit width Nd, the number of divisions of the memory cell array 4 is changed.

  In FIGS. 10 and 11, the case where parallel data is written and serial data is read has been described as an example. However, as shown in FIG. 2B, the memory cell 400 of this embodiment can be stored in the memory cell 400 using the serial bit line bl_s and can be output from the memory cell 400 using the parallel word line wl. is there. That is, bi-directional transmission (input / output) of parallel data is possible, and bi-directional transmission (input / output) of serial data is possible.

  FIG. 12 shows an application example of the memory 100 of the second embodiment.

For example, when data communication is performed using different digit widths, the digit width Nd1 and the digit width Nd2 (Nd1 ≠ Nd2) can be converted using the memory 100 of the second embodiment. That is, the memory 100_1 that converts the digit width Nd1 to the word width N and the memory 100_2 that converts the same word width N to the digit width Nd2 are used.
The serial data S11 is written in the memory 100_1 by Nd1 bits. Then, the parallel data P10 is read from the memory 100_1 with a predetermined word width N and written into the memory 100_2. By outputting serial data S12 by Nd2 bits from the memory 100_2, the digit width Nd1 can be converted to the digit width Nd2. The reverse conversion can be similarly performed.

  13 and 14 show a third embodiment. The third embodiment is a case where the wiring pattern of the serial word line wl_s is changed to enable pipelining by writing data with word width N and reading serial data.

  First, FIG. 13 is a circuit diagram showing the memory cell 410. In the fourth embodiment, the serial data word line wl_s is bent and extended.

  That is, one serial word line wl_s bends in the direction in which rows are arranged (row direction) and in the direction in which columns are arranged (column direction), and is arranged in a staircase pattern. The serial word line wl_s extends in parallel with the parallel word line in the row direction, and extends in parallel with the serial bit line bl_s and the parallel word line wl in the column direction. It is orthogonal to the serial bit line bl_s and the parallel bit line bl. Accordingly, the memory cells 400 connected to one serial word line wl_s are arranged in an oblique direction. Since the other configuration is the same as that of the first embodiment (FIG. 2B), description thereof is omitted.

  Next, the operation of the third embodiment will be described with reference to FIG.

  In FIG. 14, memory cells 400 are arranged in 6 rows and 5 columns, arrows indicate writing of parallel data P1 to P9 in units of words, and hatched memory cells 400 indicate reading of serial data S1 to S10. .

  Since the configuration of the memory 100 (address allocation method) and the operation of the memory (memory cell access method) are the same as those in the first embodiment, description thereof will be omitted.

  By bending the serial word wl_s and wiring it in a staircase pattern, serial data can be read while writing parallel data in units of words. In this case, the serial data is read out in a staircase pattern.

  In order to realize such processing, first, when writing parallel data P1 of one word into the memory cell 400, it is stored in the first row of the memory cell array 4 (1). After one piece of parallel data P1 is stored in word units, the next parallel data P2 in word units is stored in the second row. Here, reading of the serial data S1 is started. When reading the serial data S1, only the most significant bit (here, the right end) of the parallel data P1 stored in units of words is read (2). When the next parallel data P3 is stored in the third row, reading of the serial data S2 is started. The read position of the serial data S2 is the serial data S2 of the memory cell 400 in the second row located at the same place as the column of the serial data S1 read first. At that time, the data in the first row is also read out. The position where this data is read is set to 1 bit adjacent to the memory cell 400 read first (3). Similarly, serial data S3 is read after storing parallel data P4 in the fourth row, and serial data S4 is read after storing parallel data P5 in the fifth row. Further, after storing the parallel data P6 in the sixth line, the serial data S5 is read (4 to 6).

  In this way, when writing parallel data and reading serial data, the serial word line wl_s and the parallel word line wl of the same memory cell 400 are not simultaneously turned on. However, it can be read with serial data.

  When the reading of the serial data S5 is completed, all the data in the first row is read as serial data, so that one word of parallel data P7 can be written again (7). At this time, the parallel data P7 is written in a situation where reading of the serial data S6 is not completed. That is, after writing the parallel data P8, it is necessary to read two rows of serial data S8 and serial data S7 in an oblique direction. For this reason, two serial word lines s_wl are activated. This can be realized by connecting two serial word lines s_wl to one.

  A fourth embodiment will be described with reference to FIG. The fourth embodiment is a memory 100 that simultaneously processes reading and writing of parallel data having a word width N and reading and writing of serial data. The configuration of the memory 100 and the memory cell address assignment method are the same as those in the first embodiment, and a description thereof will be omitted.

  In order to simultaneously process parallel data and serial data read / write, if the memory cell selected by parallel data read / write and the memory cell 400 selected by serial data read / write cannot overlap, read / write processing cannot be performed. 400 selections should always be exclusive.

  In the first embodiment, the addresses (parallel data column designation address Addr_1 and serial data column designation address Addr_2) for selecting the column of the memory cell 400 by serial data and parallel data can be made common. On the other hand, in the fourth embodiment, an address for designating a row and a column is required for both parallel data access and serial data access. That is, when parallel data and serial data are simultaneously processed, addresses for selecting columns of the memory cell array 4 (parallel data column designation address Addr_1 and serial data row designation address Addr_2) must be different. As long as the address for selecting this column is different, parallel data and serial data can be read and written simultaneously. This is because if the same column is selected, the memory cells 400 to be processed with serial data and parallel data will be duplicated, so that they will not operate normally.

  FIG. 15 shows an example of a memory cell selected by parallel data and serial data. For example, when selecting memory cells 400 hatched with parallel data (the third row from the top, the second column for each group), the serial data is the column selected by the parallel data (the column marked with an x). Select a column other than. Note that there is no problem even if the intersecting serial data word line and parallel data word line are both activated.

  By this method, for example, serial data can be read during parallel data writing processing, which greatly contributes to an improvement in throughput.

  By using the memory 100 of the present embodiment described above in a system that handles devices having different digit widths, a system that does not require a digit width conversion circuit can be constructed. An example of the system is a system using circuits and devices having different digit widths, such as a digit serial arithmetic unit system such as an integer arithmetic unit and a floating point arithmetic unit.

  For example, the digit width Nd is converted by writing and reading data with the word width N in the memory 100 of the present embodiment. The data is arithmetically processed by a digit serial arithmetic unit, and the result is directly written in the memory 100 (without converting the digit width). Data can be transferred in units of words to an internal or external device.

  The memory cell 400 according to the present embodiment has been described by taking an SRAM as an example. However, the present invention is not limited to this. And can be implemented in all memories using word lines.

The present invention can be applied, for example, to a digit width conversion device of a system in which bandwidth is important and circuits that perform data communication of words with different digit widths transmit data. In addition, in a system that performs operations between words, the present invention can be applied to a buffer memory or the like having a digit width conversion function that enables conversion of the operation results processed by the digit serial arithmetic unit and the parallel arithmetic unit.

1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 3 is a circuit diagram illustrating a memory cell of the present invention. FIG. It is a figure explaining the address allocated to the memory cell of this invention. It is a figure explaining the address of the memory cell array of this invention. It is a figure explaining the access method of the memory cell of this invention. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 3 is a circuit diagram illustrating a memory cell of the present invention. FIG. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. 1 is a schematic diagram illustrating a semiconductor memory device of the present invention. It is a figure explaining a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st data line selection means 2 Serial data input / output control circuit 3 3rd data line selection means 4 Memory cell array 4
5 Second data line selection means 6 Parallel data input / output circuit 8 Fourth data line selection means 9 Serial data input / output circuit 30 Serial data column address decoder (serial column decoder)
31 Word line selector for serial data (serial word line selector)
50 Column address decoder for parallel data (parallel column decoder)
51 Bit line selector for parallel data (parallel bit line selector)
80 Row address decoder for serial data (serial row decoder)
81 Bit line selector for serial data (serial bit line selector)
400 memory cell 400
wl Parallel data word line bl Parallel data bit line wl_s Serial data word line bl_s Serial data bit line Addr_0 Parallel data row designation address Addr_1 Parallel data column designation address Addr_2 Serial data column designation address Addr_3 Serial data row designation address

Claims (15)

A plurality of parallel data word lines;
A plurality of parallel data bit lines orthogonal to the parallel data word lines;
A plurality of serial data word lines and a plurality of serial data bit lines orthogonal to the parallel data word lines and the parallel data bit lines, respectively;
A memory cell disposed at an intersection of the parallel data word line and the parallel data bit line, and connected to the parallel data word line and the parallel data bit line; and the serial data word line and the serial data bit line;
A memory cell array in which the memory cells are arranged in a matrix;
First data line selection means connected to the parallel data word line;
Second data line selection means connected to the parallel data bit lines;
Third data line selection means connected to the serial data word line;
Fourth data line selection means connected to the serial data bit line;
A parallel data input / output circuit;
A serial data input / output circuit;
When one serial data word line is selected by the third data line selection means, the serial data bit line connected to at least one row of the memory cells is selected by the fourth data line selection means, and at least 1 A semiconductor memory device that transmits one digit serial data.   The serial data bit line connected to at least two rows of the memory cells is selected, and at least two of the memory cells connected to the serial data bit line and the selected serial data word line are assigned one of the assigned addresses. A semiconductor memory device having the same portion and transmitting digit serial data to each of the memory cells.   2. The semiconductor memory device according to claim 1, wherein at least one serial data transmission wiring for transmitting the digit serial data is connected to the serial data input / output circuit. A plurality of parallel data word lines;
A plurality of parallel data bit lines orthogonal to the parallel data word lines;
A plurality of serial data word lines and a plurality of serial data bit lines orthogonal to the parallel data word lines and the parallel data bit lines, respectively;
A memory cell disposed at an intersection of the parallel data word line and the parallel data bit line, and connected to the parallel data word line and the parallel data bit line; and the serial data word line and the serial data bit line;
A memory cell array in which the memory cells are arranged in a matrix;
First data line selection means connected to the parallel data word line;
Second data line selection means connected to the parallel data bit lines;
Third data line selection means connected to the serial data word line;
Fourth data line selection means connected to the serial data bit line;
A parallel data input / output circuit;
A serial data input / output circuit;
A bit line selector that is common to the memory cells in a plurality of consecutive rows and is connected to the serial data bit line of the memory cells and selects the memory cells in one row of the plurality of rows;
Another bit line selector that is connected to the memory cell of the other plurality of consecutive rows and is connected to the serial data bit line of the memory cell and selects the memory cell of one row of the other plurality of rows; Equipped,
When the serial data word line connected to the memory cells in one column is selected by the third data line selection means, the serial connected to the memory cells in a plurality of rows by the bit line selector and the other bit line selector. A semiconductor memory device characterized by selecting a data bit line and transmitting a plurality of digit serial data.   The memory cells in the plurality of rows selected by the bit line selector and the other bit line selectors have the same part of the assigned address, and digit serial data is transmitted to each of the memory cells. The semiconductor memory device according to claim 4.   5. The semiconductor memory device according to claim 4, wherein one serial data transmission line is connected to each of the bit line selector and the other bit line selector.   5. The memory cell according to claim 1, wherein an upper bit of a row address assigned for input / output of parallel data is the same as a row address assigned for input / output of serial data. The semiconductor memory device described in 1.   Another memory cell array equivalent to the memory cell array, and serial data wiring for transmitting digit serial data input / output to / from the memory cell array and the other memory cell arrays, respectively, by coupling or distribution of the serial data wiring 5. The semiconductor memory device according to claim 1, wherein serial data having a plurality of digit widths is input and / or output.   5. The other memory cell array equivalent to the memory cell array, and one parallel data input and / or output to the memory cell array and another memory cell array. Semiconductor memory device.   A parallel data line connected to each of the memory cell array and the other memory cell array, wherein the parallel data line is distributed and / or coupled to input and / or output the one parallel data; The semiconductor memory device according to claim 9.   The serial data word line is bent to extend perpendicular to the parallel data bit line, and a plurality of the memory cells arranged in an oblique direction are connected to the serial data word line. 5. The semiconductor memory device according to claim 1 or 4.   2. A serial data input / output control circuit connected to the third data line selection means, wherein a read position designation signal for the serial data word line is input to the serial data input / output control circuit. The semiconductor memory device according to claim 4.   5. The memory cell according to claim 1, wherein a column address assigned for input / output of parallel data is the same as a column address assigned for input / output of serial data. 6. Semiconductor memory device.   5. The semiconductor according to claim 1, wherein the column of the memory cells selected by parallel data is the same as the column of the memory cells selected by serial data, and parallel data and serial data are converted. Storage device. 2. The parallel data input / output and the serial data input / output are simultaneously processed by differentiating the memory cell column selected by parallel data and the memory cell column selected by serial data. Item 5. The semiconductor memory device according to Item 4.

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