JP2007212279A - Timing calibration method and its device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a timing error caused by waveform deterioration resulting from the difference of a stray capacitance or the like cannot be corrected. <P>SOLUTION: A difference of the inverting time of a comparator is measured by changing a comparison voltage of the comparator relative to each reference waveform propagating along two signal routes, and a timing error caused by the difference of a rising time is calculated from the difference of a time difference of each reference waveform propagating along the two signal routes, and a timing is calibrated by using the timing error. Hereby, the timing error caused by the difference of the rising time can be calibrated simply. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method and apparatus for calibrating electric signal timing, and more particularly to a timing calibration method and apparatus suitable for use in a semiconductor inspection apparatus.

  In the semiconductor inspection apparatus, it is necessary to measure the signal of each pin of the semiconductor to be measured with high precision timing. However, paying attention to the signal transmission path from the semiconductor inspection apparatus to each pin of the semiconductor to be measured, there is a variation in the length of the signal transmission path, resulting in a timing shift.

  Therefore, conventionally, a timing calibration jig is connected in place of the semiconductor to be measured, a reference waveform is input to each pin, and each pin of the semiconductor to be measured is included in the variation between the transmission path lengths of these semiconductor inspection devices. The timing correction circuit individually corrects the timing for each of the input pin and the output pin so that the timings at these positions are equal.

  FIG. 4 shows a conceptual diagram of such a conventional timing calibration. This timing calibration method is the premise of Patent Document 1 and Patent Document 2.

  In FIG. 4, the timing calibration jig 1 is connected to a semiconductor inspection apparatus instead of the semiconductor to be measured for timing calibration. The reference waveform input to the timing calibration jig 1 has a guaranteed timing at each output point of the timing calibration jig 1.

  The reference waveform output from each output point of the timing calibration jig 1 is input to one input terminal of the comparators 3A to 3C via the transmission lines 2A to 2C having delay amounts tdA to tdC, respectively. The comparison voltage VREF is input to the other input terminals of the comparators 3A to 3C. The outputs of these comparators 3A-3C are input to determination circuits 4A-4C.

  Strobe signals are input to the determination circuits 4A to 4C via the individual timing correction circuits 5A to 5C, respectively. The timing correction circuits 5A to 5C each have a variable delay element, and output the input strobe signal with a predetermined delay. The determination circuits 4A to 4C compare the expected time with the time when the outputs of the comparators 3A to 3C actually change, and adjust the delay amount of the variable delay element based on the comparison result. In this way, the difference in delay amount between the transmission lines 2A to 2C is corrected.

  The comparators 3A to 3C receive the output of the semiconductor to be measured. During timing calibration, the performance board on which the semiconductor to be measured is mounted is replaced with a calibration performance board. Although omitted in FIG. 4, a calibration performance board is actually arranged in the middle of the transmission paths 2A to 2C.

  Next, the timing calibration procedure in the configuration of FIG. 4 will be described with reference to the waveform diagram of FIG. FIG. 5A is a reference waveform input to the timing calibration jig 1. (2) is an output point of the timing calibration jig 1, that is, a waveform at a timing guarantee point, (3) is a waveform at an input point of the comparators 3A and 3B, and a dotted line wA is an input of the comparator 3A propagated through the transmission line 2A. A waveform, a solid line wB, is an input waveform of the comparator 3B propagated through the transmission line 2B. It is assumed that the delay amount tdA of the transmission line 2A is larger than the delay amount tdB of the transmission line 2B.

  At time T3, the waveform wB passes the comparison voltage VREF of the comparator 3B, and at time T4, the waveform wA passes the comparison voltage VREF of the comparator 3A. The reason why they do not pass simultaneously is that the delay amounts of the transmission lines 2A and 2B are different.

Since the waveforms wA and wB pass through the timing guarantee points at the same time, they must reach the comparators 3A and 3B at the same time. Therefore, the delay amount of the variable delay element incorporated in the timing correction circuit 5 is adjusted to delay the strobe signal A input to the determination circuit 4A by (T4-T3) time from the strobe signal B. Thereby, the difference in the delay amount of the transmission path can be corrected. Note that the difference in delay amount of each transmission path is made as small as possible.
JP 7-55882 A JP 2001-208802 A

  However, in the timing calibration method of FIG. 4, it is assumed that the rise time of the reference waveform at the output point of the timing calibration jig 1 is constant. Depends on the rise time. FIG. 4 shows an example in which the parasitic capacitance CC greatly affects the output point A.

  Therefore, the timing at which the comparison voltage VREF is reached at the output point (timing guarantee point) of the timing calibration jig 1 is not the same, and an error of the timing calibration jig of tdE = T2-T1 occurs. This timing calibration jig error has a problem that it cannot be removed by the calibration method described in FIG.

  In recent years, with the increase in the speed of semiconductors to be measured, the timing accuracy required for semiconductor inspection apparatuses has dramatically increased. For this reason, deterioration of timing calibration due to deterioration of the output waveform due to parasitic capacitance, which has been considered to be negligible in practice in the past, has come to be regarded as a problem.

  Accordingly, an object of the present invention is to provide a timing calibration method and apparatus capable of correcting deterioration of timing calibration caused by waveform deterioration by a simple method.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
Measuring the time difference between the time when the reference waveform propagated through the signal path by changing the comparison voltage between the first level and the second level reaches each level of the comparison voltage;
Calculating a timing error between signals propagated through the two paths based on a difference in time difference between the two different paths;
Calibrating the timing between the two paths based on the timing error;
Is provided.
Thereby, the timing error resulting from the signal rise time can be corrected.

The invention according to claim 2 is the invention according to claim 1,
The timing error tdE is calculated based on the following equation. A timing error can be easily obtained.
tdE = (trA−trB) · (VREF−VL) / (VREF1−VREF2)
However,
trA: Time difference of the reference waveform passing through the signal path A when the comparison voltage is changed trB: Time difference of the reference waveform passing through the signal path B when the comparison voltage is changed VREF: Reference voltage VL: Reference waveform Low-level voltage VREF1, VREF2: Comparison voltage when measuring the time difference

The invention described in claim 3
A comparison voltage generator for outputting comparison voltages of different levels;
A comparator to which a reference waveform propagated through the output and signal path of the comparison voltage generator is input;
A timing error calculation unit that calculates a timing error between signals propagated through two different signal paths from the output of the comparator at a comparison voltage having a different level when the output of the comparator is input;
And a timing correction circuit that receives a timing error calculated by the timing error calculation unit, adjusts the delay amount, and outputs a strobe signal.
Thereby, the timing error resulting from the signal rise time can be corrected.

The invention according to claim 4 is the invention according to claim 3,
The timing error calculation unit calculates a timing error tdE based on the following equation. A timing error can be easily obtained.
tdE = (trA−trB) · (VREF−VL) / (VREF1−VREF2)
However,
trA: time difference of the reference waveform passing through the signal path A when the comparison voltage is changed trB: time difference of the reference waveform passing through the signal path B when the comparison voltage is changed VREF: voltage serving as a reference VL: signal A , B low-level voltage VREF1, VREF2: Comparison voltage when measuring the time difference

  As is apparent from the above description, the present invention measures the time difference between the time when the reference waveform propagated through the signal path by changing the comparison voltage reaches the comparison voltage, and propagates two different signal paths from this time difference. A timing error due to the difference in signal rise time is obtained, and the timing between signals propagating through the two signal paths is calibrated by this timing error.

  There is an effect that it is possible to correct a timing error caused by a difference between the rise time and the fall time by a relatively simple method of changing the comparison voltage of the comparator. Further, since no special hardware is required, there is an effect that the timing error can be calibrated at low cost.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a flowchart showing an embodiment of the timing calibration method according to the present invention. In this embodiment, the method of calibrating the waveforms propagating through the two signal paths A and B shown in FIG. 4 is shown, but it can be easily extended to a timing calibration method of three or more waveforms.

  In FIG. 1, for the reference waveform propagating in the signal path A in step (A-1), the comparator comparison voltage is set to the first level VREF1 and the second level VREF2, and the output of the comparator at that time is inverted. The time difference is measured, and this time difference is defined as trA. Next, for the reference waveform propagating in the signal path B in step (A-2), the comparator comparison voltage is similarly changed to the first level VREF1 and the second level VREF2, and the output of the comparator at that time is inverted. The time difference is measured, and this time difference is defined as trB. Here, the first level VREF1 is, for example, 90% of the reference waveform amplitude, and the second level VREF2 is, for example, 10% of the reference waveform amplitude.

Next, in step (A-3), based on the measured time difference, a timing error tdE due to the difference in the rise time of the reference waveforms propagated through the paths A and B is calculated using the following equation (1).
tdE = (trA−trB) · (VREF−VL) / (VREF1−VREF2)
(1)
Note that VREF1 and VREF2 are the comparison voltages set in steps (A-1) and (A-2), VREF is the comparison voltage in FIG. 4, and VL is the low-level voltage of the reference waveform. Here, VREF is, for example, 50% of the reference waveform amplitude.

  Next, in step (A-4), the delay amount of the variable delay element in the timing correction circuit 5 is adjusted, and this timing error tdE is corrected.

  In the configuration of FIG. 4, since the parasitic capacitance CC greatly affects the output point A, the rise time of the input waveform A is longer than that of the input waveform B. Therefore, the input waveform A is delayed from the input waveform B at the output point of the timing calibration jig 1 whose timing is originally guaranteed. Accordingly, the time difference when the comparison voltage of the comparator is changed is measured, the timing error tdE is calculated using the equation (1), and the strobe signal input to the determination circuits 4A to 4C using the tdE is calculated. Correct the timing.

  Next, the present embodiment will be described in detail with reference to the waveform diagram of FIG. The same elements as those in FIG. 5 are denoted by the same reference numerals and description thereof is omitted. In FIG. 2, (1) is a reference waveform, (2) is a waveform at the timing calibration jig 1 exit which is a timing guarantee point, (3) is an input waveform of the comparators 3A and 3B, and (4) is input to the determination circuit 4B. The waveform of the calibrated strobe signal B is shown, and (5) is the waveform of the calibrated strobe signal A inputted to the determination circuit 4A.

  As shown in (2), the rise times of the waveforms wA and wB differ due to the influence of the stray capacitance CC. Therefore, the waveform wB reaches the comparison voltage VREF at time T1, and the waveform wA reaches the comparison voltage VREF at time T2. This time difference T2-T1 is a timing error caused by the difference in the rise time of the waveform, and cannot be removed by the conventional method described with reference to FIG.

In order to correct the timing error tdE inherent to the timing calibration jig 1, the timing error tdE must be measured. Therefore, the comparison voltage of the comparator 3B to which the waveform wB is input is set to the second level VREF2, and the time T5 when the output of the comparator 3B is inverted is measured. Next, the comparison voltage is set to the first level VREF1, and similarly, the time T6 at which the output of the comparator 3B is inverted is measured, and the difference is set to trB.
trB = T6-T5

Next, the comparison voltage of the comparator 3A to which the waveform wA is input is set to the second level VREF2, and the time T7 when the output of the comparator 3A is inverted is measured. Next, the comparison voltage is first
Similarly, the time T8 when the output of the comparator 3A is inverted is measured, and the difference between them is trA.
trA = T8-T7

  Then, from the trA and trB, the timing error tdE is calculated using the equation (1), and the strobe signal is corrected using the tdE. In the example of FIG. 2, since the waveform wA has a later rise time than the waveform wB, the waveform wA is delayed by tdE with respect to wB at the output point of the timing calibration jig 1, which is the timing guarantee point. Since the timing of the two waveforms is essentially the same at the timing guarantee point, this timing error is adjusted by adjusting the variable delay element in the timing correction circuit 5 so as to output the strobe signal of the signal A by tdE earlier than FIG. tdE is corrected.

  FIG. 3 shows the configuration of the timing calibration apparatus. The same elements as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 3, reference numeral 6 denotes a comparison voltage generator, which outputs comparison voltages VREF1 and VREF2 having different levels. Reference numeral 7 denotes a comparator, to which an output of the comparison voltage generator 6 and a reference waveform propagated through the signal path are input.

  Reference numeral 8 denotes a timing error calculation unit to which the output of the comparator 7 is input. The timing error calculation unit 8 calculates the timing error tdE by the above equation (1) from the inversion times of the comparators in the comparison voltages VREF1 and VREF2 having different levels for the reference waveforms propagated through two different signal paths. This timing error tdE is input to the timing correction circuit 5. The timing correction circuit 5 adjusts the delay amount of the variable delay element and outputs a strobe signal for correcting the timing error tdE.

  In these embodiments, the method of calibrating the timing of two different paths has been described. However, the timing of signals propagating through three or more paths can also be corrected. In this case, it is only necessary to determine a reference route, set a plurality of sets of two routes of this route and other routes, and calibrate the timing within these sets.

  The timing calibration method and apparatus can be applied not only to general timing correction of a semiconductor inspection apparatus but also to other apparatuses.

  In the above embodiment, the rise time is focused. However, the rise time can be applied.

It is a flowchart which shows one Example of this invention. It is a wave form diagram for demonstrating operation | movement of one Example of this invention. It is a block diagram which shows the other Example of this invention. It is a schematic diagram of timing calibration. It is a wave form diagram for demonstrating the conventional timing calibration method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Timing calibration jig 2A-2C Transmission path 3A-3C, 7 Comparator 4A-4C Judgment circuit 5 Timing correction circuit 6 Comparison voltage generation part 8 Timing error calculation part tdA-tdC Delay amount tdE Timing error VREF, VREF1, VREF2 comparison Voltage

Claims (4)

Measuring the time difference between the time when the reference waveform propagated through the signal path by changing the comparison voltage between the first level and the second level reaches each level of the comparison voltage;
Calculating a timing error between signals propagated through the two paths based on a difference in time difference between the two different paths;
Calibrating the timing between the two paths based on the timing error;
A timing calibration method comprising: 2. The timing calibration method according to claim 1, wherein the timing error tdE is calculated based on the following equation.
tdE = (trA−trB) · (VREF−VL) / (VREF1−VREF2)
However,
trA: time difference of the reference waveform passing through the signal path A when the comparison voltage is changed trB: time difference of the reference waveform passing through the signal path B when the comparison voltage is changed VREF: reference voltage to be used as reference VL: reference waveform Low-level voltage VREF1, VREF2: Comparison voltage when measuring the time difference A comparison voltage generator for outputting comparison voltages of different levels;
A comparator to which a reference waveform propagated through the output and signal path of the comparison voltage generator is input;
A timing error calculation unit that calculates a timing error between signals propagated through two different signal paths from the output of the comparator at a comparison voltage having a different level when the output of the comparator is input;
A timing error that is input by the timing error calculated by the timing error calculator, adjusts the delay amount, and outputs a strobe signal; and
A timing calibration apparatus comprising: 4. The timing calibration apparatus according to claim 3, wherein the timing error calculation unit calculates a timing error tdE based on the following equation.
tdE = (trA−trB) · (VREF−VL) / (VREF1−VREF2)
However,
trA: time difference of the reference waveform passing through the signal path A when the comparison voltage is changed trB: time difference of the reference waveform passing through the signal path B when the comparison voltage is changed VREF: reference voltage to be used as reference VL: signal A, B low-level voltage VREF1, VREF2: Comparison voltage when measuring the time difference

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