JP2004219097A - Semiconductor testing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus that reduces errors caused by the variation of delay time that is generated while the amount of delay in a delay circuit is being calibrated for achieving a method for calibrating the delay circuit precisely, and achieves a test by a test waveform and judgment timing using an edge clock that is generated precisely. <P>SOLUTION: A timing circuit 100 is used for the semiconductor testing apparatus. The semiconductor testing apparatus comprises a variation ratio computing circuit 53 for measuring/calculating the variation ratio of the delay time of the delay circuit 12 to be calibrated by providing a ring oscillator 51 for detecting delay time variation incorporating internal delay time variation being calibrated in the delay circuit 12; and a circuit 6 for calibrating the amount of delay for performing correction computing processing with the variation ratio to a measured period by measuring the oscillation period that is oscillated by an oscillation path including the delay circuit 12 to be calibrated in a system. The amount-of-delay setting data obtained by the circuit 6 for calibrating the amount of delay are set to be true calibration amount-of-delay setting data. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor test apparatus, and particularly to a method for calibrating a variable delay circuit used in a semiconductor test apparatus, a semiconductor test apparatus using the calibrated delay circuit, and a semiconductor test method and a semiconductor manufacturing method. Technology.
[0002]
[Prior art]
In general, in a functional test of an IC under test, various test signals are applied to the IC under test from an IC test apparatus within each basic (test) cycle, and various response signals from the IC under test are applied. Are taken into an IC test apparatus, and the quality of each is determined at the timing of each determination, thereby testing whether or not the function as an IC is normal.
[0003]
By the way, in recent years, with the speeding-up of general ICs, in a semiconductor test apparatus for testing those ICs, the accuracy of the generation time (timing) of a test waveform affects the test performance. In particular, an edge clock generated by a timing circuit provided in a semiconductor test apparatus requires extremely high time accuracy. For this reason, when a device such as a CMOS, whose edge generation timing changes due to fluctuations in temperature and power supply voltage, is used in the timing circuit, the conventional technology provides a mechanism for detecting and correcting the delay fluctuation to reduce timing accuracy deterioration. are doing.
[0004]
Here, the present inventor studied as a premise of the present invention, the outline of the timing circuit of the semiconductor test device, the operation of the edge generation circuit, the calibration method of the delay circuit used in the edge generation circuit, the storage example of the table memory, respectively, This will be described with reference to FIGS. 9, 10, 11, and 12.
[0005]
As shown in FIG. 9, the timing circuit 100 studied as a premise of the present invention includes an edge generation circuit 1, a waveform generation circuit 2, a determination circuit 3, a selection circuit 4, a variation calculation circuit 5, and a delay calibration circuit 8. Prepare. The edge generation circuit 1 includes a counter 11, a data operation circuit 13, a correction operation circuit 14, and a delay circuit 15, and is composed of n pieces.
[0006]
The waveform generation circuit 2 generates a test waveform 110 based on waveform generation data 112 from a pattern generation circuit (not shown). The determination circuit 3 determines whether the response signal 111 from the LSI under test is good or bad. The fluctuation amount calculation circuit 5 includes a period measurement circuit 52 for detecting the delay time fluctuation of the edge clock generated by the edge generation circuit 1 from the fluctuation amount of the oscillation period of the built-in ring oscillator 51, and the measurement of the oscillation period. A fluctuation ratio calculation circuit 53 for calculating the fluctuation ratio (k), which always calculates the fluctuation ratio of the delay time fluctuation of the delay circuit 15 from a predetermined reference state.
[0007]
Next, the edge generation circuit 1 calculates the generation time (Tc ′, Td ′) of the edge clock by the data operation circuit 13 using the timing control data from the pattern generation circuit (not shown), and converts the data to the correction operation circuit. After calculating the timing data (Tc, Td) in which the time fluctuated with the fluctuation ratio (k) from the fluctuation amount calculation circuit 5 at 14, the counter 11 that delays by more than the original clock (master clock) and the original data An edge clock is generated by setting the delay circuit 15 for delaying less than the oscillation cycle. The selection circuit 4 has a function of selecting an edge clock output from the plurality of edge generation circuits 1. In this example, the calibration of the delay amount by the delay amount calibration circuit 8 is performed by a desired delay circuit 15 The calibration was performed sequentially.
[0008]
Here, as an example of the calculation of the variation ratio (k), the oscillation cycle of the ring oscillator 51 (here, REFROSC) measured at a desired time is measured, and then the oscillation cycle of the ring oscillator 51 at the present time is measured. (Here, MEROSOC) is measured, and then (MEROSC-REFROSC) / REFROSC is calculated from the measured REFROSC and MEROSOC. In this example, this calculation result is set as a variation ratio k.
[0009]
In the example of the timing chart in the operation of the edge generating circuit 1 shown in FIG. 10, the output 101out of the source 101 having a period of 2 ns, and the delay for delaying 5 ns as the setting data (Tc, Td) to the counter 11 and the delay circuit 15 are set. Examples of data and output timings of the counter 11 and the delay circuit 15 are shown. The output 15out of the delay circuit 15 shows three examples (cases 1 to 3). Case 1 shows a case where no delay variation has occurred after the delay amount calibration of the delay circuit 15, case 2 shows a case where delay variation has occurred, and case 3 shows a case where the delay variation has been corrected by the correction operation circuit 14.
[0010]
The delay circuit output 15out in case 1 is obtained by delaying the counter 11 for two counts of the original 2 ns period, that is, delaying the delay circuit 15 for 1 ns after delaying 4 ns.
[0011]
Next, in case 2, an example is given in which there is a delay fluctuation in the delay circuit 15. Here, the fluctuation period arithmetic circuit 5 simultaneously measures the oscillation cycle of the ring oscillator 51, and obtains the fluctuation ratio of the result. k has been calculated. For this reason, this is an example in which the delay amount of the delay circuit 15 has a delay variation of Td × k.
[0012]
In case 3, an edge clock output by setting a delay set value (Tc, Td) obtained by correcting the delay fluctuation (Td × k) by the correction operation circuit 14 for the delay fluctuation is set. As described above, the edge clock is generated by the technique studied as a premise of the present invention as described above.
[0013]
Next, a method of calibrating the delay circuit used in the above-described edge generation circuit will be described. FIG. 11 shows a configuration example of one delay circuit 15 and a delay amount calibration circuit 8 for calibrating the delay amount of the delay circuit 15.
[0014]
The delay circuit 15 shown in FIG. 11 includes a delay element 151, a table memory 155, a selector 152 for switching a pulse input path from the counter 11 to a path of the oscillation control circuit 154, and data from the table memory 155 and data from the register 156. It comprises a selector 153 for switching, and an oscillation control circuit 154 for performing control for starting oscillation in accordance with a command from a CPU (not shown). The delay amount calibration circuit 8 includes an oscillation period measurement circuit 81 that measures the oscillation period of the oscillation signal output from the delay circuit 15, and a calibration control circuit 82 that determines whether the oscillation period measurement circuit 81 has a predetermined period. Consists of
[0015]
The delay element 151 of the delay circuit 15 delays the input pulse by a predetermined delay amount in accordance with the delay data from the table memory 155, and furthermore, the table memory 155 sets the delay time of only the delay data Td by the delay element 151. This is a conversion memory for converting the setting data to be delayed.
[0016]
The storage example of the table memory 155 shown in FIG. 12 shows a case where the variable width of the delay circuit 15 is 1968.75 ns and the delay resolution is 31.25 ps. Addresses of the table memory 155 are 0 to 127, address “0” is assigned 0 ps, address “1” is assigned 31.25 ps,..., Address “63” is assigned 1968.75 ps, and data stored in each address is assigned. This is the data that creates the delay time. The delay amount correction circuit 8 is used to acquire data set in the table memory 155.
[0017]
Next, a calibration procedure using the delay amount calibration circuit 8 will be described. First, an oscillation path including the delay circuit 15 to be calibrated is formed, "0" is set in the delay circuit 15, and the oscillation cycle is measured. This is the oscillation period (tref) when the delay amount is 0 ps.
[0018]
Next, when detecting a delay set value that results in a delay amount of 31.25 ps of the address “1”, the expected value of the oscillation cycle at this time is tref + 31.25 ps, and the delay set value closest to the expected value is delayed. The amount is detected by the quantity control circuit 82.
[0019]
Similarly, the delay set value up to the address “63” is acquired, and after the acquisition is completed, the delay set value is set in the table memory, and the delay amount calibration of the delay circuit 15 is completed. Further, a plurality of (n) delay circuits 15 are calibrated by this procedure.
[0020]
The technology relating to the semiconductor test device studied as a premise of the present invention as described above is described in, for example, Patent Document 1. That is, Patent Literature 1 discloses a method of measuring and calculating the rate of change of a delay circuit during a test of a semiconductor device, thereby correcting the changed delay time.
[0021]
Further, as a technique similar to such a semiconductor test apparatus, a method of calibrating a delay amount of a delay circuit that includes a delay circuit to be calibrated in a system during a test of a semiconductor device and oscillates and measures an oscillation cycle is adopted. Further, a technology including a heat insulation circuit or the like for reducing a delay amount variation due to a temperature variation or the like (for example, see Patent Documents 2 and 3) and a technology for correcting a delay time variation during a test of a semiconductor device (for example, see Patent Document 4) A technique for making the power consumption of the delay circuit the same at the time of calibration and at the time of test (for example, see Patent Documents 5 and 6), a variable delay using two types of high-speed and low-speed reference clocks and a clock cycle as a variable unit A technology of a delay circuit in which a circuit is formed so as to be hardly affected by temperature fluctuation and voltage fluctuation (for example, see Patent Document 7) is disclosed.
[0022]
[Patent Document 1]
JP-A-6-51027 (Abstract on page 1 etc.)
[0023]
[Patent Document 2]
Japanese Patent Application Laid-Open No. 9-304488 (abstract on page 1)
[0024]
[Patent Document 3]
JP-A-10-197911 (abstract on page 1)
[0025]
[Patent Document 4]
JP-A-8-226957 (abstract of the first page, etc.)
[0026]
[Patent Document 5]
JP-A-8-292242 (Abstract on page 1 etc.)
[0027]
[Patent Document 6]
Japanese Patent Application Laid-Open No. 9-203772 (abstract on page 1)
[0028]
[Patent Document 7]
Japanese Patent Application Laid-Open No. 2000-249747 (Summary on page 1)
[0029]
[Problems to be solved by the invention]
By the way, as a result of the present inventor's study on the technology of the semiconductor test apparatus as described above, the following has become clear. Here, a problem in the above-described delay amount calibration method will be described.
[0030]
For example, in the above-described timing circuit shown in FIG. 9 and the like, when the delay circuit 15 is calibrated, the delay time of the delay circuit to be calibrated varies due to fluctuations in ambient conditions and the like during the calibration. More specifically, the variation occurs during the acquisition of the delay set value up to the address “63” of the table memory 155 described above, which causes an error in the set delay amount of the edge clock after calibration.
[0031]
FIG. 13 shows the result of measuring the delay amount setting error after the delay amount calibration in the technique studied as the premise of the present invention. The horizontal axis in FIG. 13 shows the delay setting value, and the vertical axis shows the error with respect to the delay setting value. The measurement is the result of performing the measurement in 62.5 ps steps. As shown in FIG. 13, the delay characteristic after calibration has a tendency that the delay error gradually increases in the + direction. The reason for this is that when CMOS is applied to this delay circuit, the oscillation cycle gradually increases during calibration, so that the power consumption gradually decreases and the amount of self-heating also decreases, so that tref becomes smaller than the measurement start point. Therefore, it is easily presumed that the acquired delay setting value gradually causes a larger error.
[0032]
In recent years, in a semiconductor test apparatus, it has become common to use a CMOS device having a large delay variation with respect to temperature and power supply voltage variations in a timing circuit. Accordingly, since the test waveform generation accuracy affects the test performance, very high accuracy is required for the edge clock generation accuracy of the edge generation circuit.
[0033]
However, in the related art (including the techniques of Patent Documents 1 to 7), there is disclosed a method of reducing a delay amount variation of a delay circuit to be calibrated during calibration, but a means for correcting an error when the variation occurs. However, there is a problem that all errors related to the fluctuation of the delay amount during the calibration are set errors of the edge clock. In order to suppress this problem, in the related art, in order to keep the ambient environment (temperature, power supply voltage) during calibration as small as possible, a circuit that keeps the delay circuit in a constant temperature state, or the temperature of the entire semiconductor test apparatus, Circuits and equipment for keeping the power supply voltage constant are provided, and there has been a problem that the apparatus cost increases.
[0034]
Therefore, the present invention enables a highly accurate delay circuit calibration method by reducing errors due to delay amount variations during calibration without using an expensive constant temperature circuit or the like for stabilizing ambient conditions of the delay circuit. It is an object of the present invention to provide a semiconductor test apparatus that realizes a test based on a test waveform using an edge clock generated with high accuracy and a judgment timing.
[0035]
Further, it is possible to provide a semiconductor inspection method and a semiconductor manufacturing method for inspecting a semiconductor device (LSI) using a test waveform whose timing (time) is controlled with high precision.
[0036]
[Means for Solving the Problems]
The outline of a typical one of the inventions disclosed in the present application will be described as follows.
[0037]
In order to achieve the above object, the present invention provides means for calculating a variation ratio of a propagation delay time through which a pulse of a calibration path passes during calibration in a delay amount calibration of a delay circuit which requires calibration of the delay amount. Calculate new delay amount setting data obtained by performing an arithmetic process between the delay amount setting data obtained during the calibration and the variation ratio, and obtain the data obtained from the calculation result as regular delay amount setting data. The method is characterized by a method of acquiring delay amount setting data of a delay circuit.
[0038]
Specifically, as a first delay circuit calibration method, in a delay amount calibration of a delay circuit that requires calibration of a delay amount, a detection circuit that detects a delay variation of the delay circuit is provided, and a delay circuit to be calibrated is provided. Measure the delay amount setting data to obtain the desired delay time, obtain the delay time fluctuation from the predetermined reference state every time the setting data is measured, and use the data to calibrate the delay amount Is performed.
[0039]
In addition, as a second method of calibrating the delay circuit, in the delay amount calibration of the delay circuit that requires the calibration of the delay amount, there is provided a detection circuit that detects a delay variation of the delay circuit. The delay amount setting data for obtaining a desired delay time is measured, and each time the delay amount setting data is measured, the variation ratio of the delay time from a predetermined reference state is calculated, and the delay amount setting data is corrected. Is performed.
[0040]
In addition, as a third method of calibrating the delay circuit, in the delay amount calibration of the delay circuit that requires the calibration of the delay amount, there is provided a detection circuit that detects a delay variation of the delay circuit. The delay amount setting data for obtaining the desired delay time is measured, and each time the delay amount setting data is measured, the variation ratio of the delay time from the reference state at the start of the calibration is calculated, and the delay amount setting data of the delay amount setting data is calculated. The correction is performed.
[0041]
In order to realize the above-described first to third delay circuit calibration methods, in the present invention, a delay time variation detection circuit (ring oscillator) incorporating internal delay time variation during delay circuit calibration is provided, and calibration is performed. Means for measuring and calculating the variation ratio of the delay time of the target delay circuit (variation ratio calculation circuit); oscillation control means for forming an oscillation path including the delay circuit to be calibrated in the system (oscillation control circuit); Measuring means (cycle measuring circuit) for measuring an oscillation cycle oscillated by the oscillation control means, and correcting means (correction calculating circuit) for performing a correction calculation process between the cycle measured by the measuring means and the variation ratio. And the delay amount setting data obtained by the correction means is used as true delay amount setting data for calibration.
[0042]
Further, in the present invention, the first timing circuit using any one of the first to third delay circuit calibration methods includes a master clock (master clock), a counter for generating a delay at each master oscillation cycle, and a counter. A delay circuit that generates a delay equal to or less than the original oscillation, a data calculation circuit that calculates the amount of delay in the counter and the delay circuit, and a waveform generation circuit that generates a test waveform based on the timing of the edge clock output from the delay circuit. And a judgment circuit for judging a response signal from the device under test based on the edge clock.
[0043]
The second timing circuit using any one of the first to third delay circuit calibration methods includes a master clock (master clock), a counter that generates a delay at every master oscillation cycle, A delay circuit for generating a delay of the delay circuit, a data calculation circuit for calculating the amount of delay in the counter and the delay circuit, a change ratio calculation circuit for detecting a delay change of the delay circuit and calculating a change ratio from a predetermined reference state. A correction operation circuit that performs an operation process on only the delay amount setting data that causes a delay fluctuation among the data calculated by the data operation circuit according to a change ratio, and sets the obtained delay time in a counter and a delay circuit; A waveform generation circuit that generates a test waveform based on the timing of an edge clock output from the circuit; and a determination circuit that determines a response signal from the device under test using the edge clock. Is shall.
[0044]
Further, according to the present invention, the semiconductor test apparatus provided with any one of the first and second timing circuits includes a source generator (master clock), and a pattern generation circuit that generates pattern data including information on a test waveform. , A timing circuit that receives the original vibration and pattern data, generates a test waveform and determines a response waveform from the device under test, a driver that applies the test waveform to the device under test, and a predetermined response waveform from the device under test. And a fail memory for storing the result determined by the determination circuit in the timing circuit.
[0045]
Further, the semiconductor inspection method according to the present invention uses a test waveform and a determination timing generated by an edge clock generated using a delay circuit configured by any one of the first to third delay circuit calibration methods. And inspecting the semiconductor device.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.
[0047]
(Embodiment 1)
First, an example of the configuration of a timing circuit used in the semiconductor test device according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a configuration diagram of the timing circuit.
[0048]
In the timing circuit 100 according to the present embodiment, the waveform generation circuit 2, the determination circuit 3, and the variation calculation circuit 5 have the same functions as the respective circuits shown in FIG. The circuit 1 and the delay amount calibration circuit 6 have a new function in the embodiment of the present invention. However, in the edge generation circuit 1, only the delay circuit 12 has a new function.
[0049]
That is, the timing circuit 100 according to the present embodiment includes the edge generation circuit 1, the waveform generation circuit 2, the determination circuit 3, the selection circuit 4, the variation calculation circuit 5, and the delay calibration circuit 6. The edge generation circuit 1 includes a counter 11, a delay circuit 12, a timing data operation circuit 13, and a correction operation circuit 14, and is composed of n pieces. For example, as one example, six edge generation circuits 1 are provided, one to four clock edges are applied to the waveform generation circuit 2 for generating a test waveform, and five to six clock edges are applied to the determination circuit 3. On the other hand, it is applied for the determination timing of the response signal. The variation calculation circuit 5 includes a ring oscillator 51, a period measurement circuit 52, and a variation ratio calculation circuit 53.
[0050]
Next, an example of the configuration of the delay circuit and the delay amount calibration circuit shown in FIG. 1 will be described with reference to FIG. FIG. 2 shows a configuration diagram of the delay circuit and the delay amount calibration circuit.
[0051]
The delay circuit 12 further includes a delay element 122 for delaying a pulse delayed by a unit of the master clock 101 from the counter 11 with a predetermined delay resolution, and an oscillation path including the delay element in the system. Control circuit 121 for realizing the above, the table memory 124 described in the technique studied as a premise of the present invention, and the delay amount setting data to be set in the delay element 122, the delay amount from the table memory 124 and the delay amount calibration circuit 6. It comprises a selector 123 for selecting any of the quantity setting data.
[0052]
Further, the delay amount calibration circuit 6 includes a period measurement circuit 61 that measures the period of the oscillation path including the delay element 122 in the system, and a period measured by the period measurement circuit 61 and a variation measured and calculated by the variation amount calculation circuit 5. A correction operation circuit 62 for calculating the cycle data multiplied by the ratio ka; and a calibration control for determining whether the calculated cycle data matches the expected value within a predetermined range. It comprises a circuit 63.
[0053]
In calculating the variation ratio ka in the present embodiment, the oscillation period of the ring oscillator 51 (here, REFROSC) measured at a desired time is measured, and then the oscillation period of the ring oscillator 51 at the present time ( Here, MEROSOC) is measured, and then REFROSC / MEROSC is calculated by the fluctuation ratio calculation circuit 53 based on the measured REFROSC and MEROSC.
[0054]
Next, an example of the operation of the delay amount calibration method of FIG. 2 will be described with reference to the flowchart of FIG. FIG. 3 shows a flowchart of the operation of the delay amount calibration method.
[0055]
In the process of step S1, the variable A is the expected value of the delay time of the delay amount setting data set in the delay circuit 12, the variable B is the delay amount setting data, and the initial value is "0".
[0056]
In the process of step S2, the oscillation of the oscillation path including the ring oscillator 51 in the variation calculation circuit and the delay element 122 to be calibrated is started.
[0057]
In the process of step S3, the cycle measuring circuit 61 measures the oscillation cycle (tdt ') of the output signal from the delay circuit 12, and at the same time measures and calculates the variation ratio (ka) at that time.
[0058]
In the process of step S4, a correction calculation (tdt ′ × ka) of the measured oscillation period is performed to calculate tdt.
[0059]
In the process of step S5, it is determined whether B is "0". Since the value of the variable B is “0” in the first process of step S5 (YES), tdt is set to tref in the process of step S6 (tdt → tref). This is the oscillation cycle when the delay amount is 0 ps.
[0060]
In the next step S8, it is determined whether or not the acquisition has been completed. In the first process of step S8, the acquisition of the delay amount setting data is not completed (NO), so the process proceeds to step S9, and the variable A of the expected acquisition value is set to the next expected value of 31.25 ps. Perform processing.
[0061]
Next, in the process of step S10, the variable B, which is the delay amount setting data for the delay circuit 12, is also updated to the next value, and the next delay amount setting data is set in the delay circuit 12 in the process of step S11.
[0062]
Subsequently, the processing of steps S3 and S4 is performed to calculate the measured oscillation cycle (tdt). At this point, since the value of the variable B in the process of step S5 is "1" (NO), the process proceeds to step S7.
[0063]
In the process of step S7, it is determined whether the calculated value of tref + A (31.25 ps) previously obtained matches the obtained value (tdt) within a predetermined range. If they match (OK), the process proceeds to step S8, the variable A is updated, and the process proceeds to the acquisition of the next delay amount setting data. If they do not match (NG), only the delay amount setting data is updated, and measurement is performed with the next delay amount setting data (the processing in steps S3 and S4).
[0064]
In the same manner, the delay amount up to the variable width of the predetermined delay circuit (1966.85 ps in this example) is obtained.
[0065]
Also, the delay characteristics of the delay elements have been described by way of example in which the delay increases below a predetermined resolution as the set delay amount setting data increases.
[0066]
Here, a detailed concrete example of the relationship between the configuration diagram of FIG. 2 and the flowchart of FIG. 3 will be described. The processes of steps S1, S2, S10, and S11 are performed by the CPU, and the period of the process of step S3 is measured by the period measuring circuit 61. The variation ratio ka is measured by the variation amount calculation circuit 5. The processing of step S4 is performed by the correction operation circuit 62, and the processing of steps S5, S6, S7, S10, and S11 is performed by the calibration control circuit 63. This is because the acquisition of the delay amount setting data in one desired expected expected value is mainly measured by the calibration control circuit 63, and the initial setting of the expected expected value, the update thereof, and the end processing of the acquisition are performed. , Under the control of the CPU. The delay amount setting data acquired in this manner is set in the table memory 124 as described in the technique studied as the premise of the present invention.
[0067]
Next, a method of generating an edge clock at the time of an actual test of a semiconductor test apparatus based on the delay amount setting data set in the table memory 124 according to the above-described example will be described with reference to FIG.
[0068]
As described in the technique studied as a premise of the present invention, first, the counter 11 and the delay circuit 12 calculate data to be delayed according to the timing information indicated by the pattern data 112 in the timing data calculation circuit 13. At this time, the variation calculation circuit 5 always measures and calculates the variation ratio ka. The correction operation circuit 14 calculates a delay time (Td, Tc) obtained by correcting the fluctuated delay time, and sets the calculated delay time in the counter 11 and the delay circuit 12. The counter 11 and the delay circuit 12 generate an edge clock according to the set data.
[0069]
Next, FIG. 4 shows the effect of the present embodiment. The horizontal axis shows the delay set value for 1968.75 ps in 31.25 ps increments, and the vertical axis shows the delay amount error with respect to the delay setting. The range of the error in the measurement of the present embodiment is within ± 5 ps with respect to the expected delay value, and the error due to the delay variation during calibration, which was a problem in the technology studied as the premise of the present invention, was almost eliminated. .
[0070]
(Embodiment 2)
Next, an embodiment in which the correction operation circuit 14 in the edge generation circuit 1 described in the first embodiment with reference to FIG. 1 is not used will be described with reference to FIG. FIG. 5 shows a configuration diagram of the timing circuit.
[0071]
In the present embodiment, instead of performing a timing calculation to correct the delay variation during the execution of the test in the semiconductor test apparatus and correcting the variation, factors that cause the delay variation such as ambient temperature, self-heating, power supply voltage, and self-consumption current are considered. An example of a timing circuit that suppresses and reduces delay variation that causes a timing error during a test will be described.
[0072]
The timing circuit 100 shown in FIG. 5 has a configuration in which the correction arithmetic circuit 14 is removed from the configuration diagram of FIG. 1, and therefore, the setting data (Tc, Tc, Td) is set in the counter 11 and the delay circuit 12 as they are.
[0073]
The means for calibrating the delay circuit 12 in the present embodiment is performed using the delay circuit 12 and the delay amount calibration circuit 6 described with reference to FIG. However, since the operation method of each component at the time of delay circuit calibration is different, an operation flowchart of the delay amount calibration method is shown in FIG. 6, and the operation will be described below.
[0074]
The variable A in the process of step S21 is the expected value of the delay time of the delay amount setting data in the delay circuit 12, and the variable B is the delay amount setting data. The initial values are both "0".
[0075]
In the process of step S22, the oscillation of the oscillation path including the ring oscillator 51 in the variation calculation circuit and the delay element 122 to be calibrated is started.
[0076]
In the process of step S23, the cycle measuring circuit 61 measures the oscillation cycle (tref) of the output signal from the delay circuit, and at the same time, measures the oscillation cycle (REFROSC) of the ring oscillator 51. In this processing, the oscillation cycle (REFROSC) of the ring oscillator 51, which is a reference at the time of the delay time fluctuation correction calculation, is measured.
[0077]
Next, in the process of step S24, the variable A is set to 31.25 ps, which is the expected value of the next acquisition delay, and the variable B is also set to "1" which is the next delay amount setting data.
[0078]
In the process of step S25, the cycle measuring circuit 61 measures the oscillation cycle (tdt ') of the output signal from the delay circuit 12, and at the same time measures and calculates the variation ratio ka at that time. The variation ratio ka is a value obtained by calculating MEROSOC / REFROSC, and MEROSOC is an oscillation cycle of the ring oscillator 51 at that time.
[0079]
In the process of step S26, a correction operation (tdt ′ × ka) of the measured oscillation period is performed.
[0080]
In the process of step S27, it is determined whether or not the previously obtained value of tref + A matches the delay amount setting data tdt within a predetermined range. If they match (OK), the process proceeds to step S28, the variable A is updated, and the process proceeds to the acquisition of the next delay amount setting data. If they do not match (NG), the process proceeds to steps S30 and S31, and only the delay amount setting data is increased to acquire the oscillation cycle of the next delay amount setting data.
[0081]
In this way, the amount of delay up to the variable width (1968.75 ps in this example) of the predetermined delay circuit is obtained.
[0082]
Here, the relationship between the configuration diagram of FIG. 2 and the flowchart of FIG. 6 will be described in more detail. The processes of steps S21, S22, S24, and S29 are performed by the CPU, and the cycle measurement of the process of step S23 is performed by the cycle measurement circuit 61. The measurement of REFROSC is performed by the variation calculation circuit 5. The processes of steps S26, S27, S30, and S31 are performed by the calibration control circuit 63. This is because the acquisition of the delay amount setting data in one desired expected value is mainly measured by the calibration control circuit 63 controlling the delay amount setting data to be set in the delay element. The initial setting, the updating, and the end processing of the acquisition are performed under the control of the CPU. The delay amount setting data thus obtained is set in the table memory 124.
[0083]
When an edge clock is generated from the edge generation circuit 1 which is an operation in actual use of the semiconductor test apparatus, a means for setting the delay circuit 12 to a predetermined constant temperature state without using the variation calculation circuit is used. Suppress delay fluctuation of edge clock generation time.
[0084]
Also, the delay characteristics of the delay elements have been described by way of example in which the delay increases below a predetermined resolution as the set delay amount setting data increases.
[0085]
(Embodiment 3)
Next, an operation of the semiconductor test apparatus 108, that is, a method of testing (inspecting) a semiconductor device will be described as a third embodiment of the present invention with reference to FIG. FIG. 7 shows a configuration diagram of the semiconductor test apparatus.
[0086]
In the present embodiment, a semiconductor test apparatus 108 using the timing circuit 100 described in the first embodiment will be described.
[0087]
The semiconductor test apparatus 108 shown in FIG. 7 gives the test waveform 110 to the LSI under test 107, and compares the response waveform 111 returned from the LSI under test 107 with the expected value prepared in advance to determine the quality. This is an apparatus for performing an operation test of the LSI under test 107.
[0088]
The illustrated semiconductor test apparatus 108 mainly generates a pattern generation circuit 102 that generates test pattern data 112 of a test waveform and an expected value, and generates a timing of a test waveform 110 and a response signal 111 based on the test pattern data 112. A timing circuit 100, a driver 105 for applying a test waveform 110 to the LSI under test 107, and an analog comparison circuit 106 for comparing a response waveform 111 from the LSI under test 107 with a predetermined voltage to determine Low or High level The output signal of the analog comparison circuit 106 is determined by a determination circuit in the timing circuit 100 at a determination timing using a highly accurate edge clock, and is further determined by a pattern generation circuit. Judgment times for comparing the expected value with the logical value and judging pass / fail When a fail memory 103 for storing information relating to the determination result from the determination circuit, a CPU104 for controlling each of these circuits, and a source oscillation 101 as a time reference for the operation of the semiconductor testing device 108. With such a configuration, a semiconductor test apparatus using a delay circuit using the calibration method of the present invention can be easily realized.
[0089]
For example, in the semiconductor test apparatus 108, when skew adjustment between pins and edges of a tester is performed using the delay setting accuracy of the timing circuit 100 (timing adjustment in units of resolution of the timing circuit), a skew adjustment time reference is used. Since the edge clock setting accuracy is high, the skew adjustment accuracy of the tester is improved.
[0090]
Further, for example, as the semiconductor test apparatus 108, an edge clock capable of setting a highly accurate delay can be realized. Therefore, highly accurate time measurement in units of tens of ps can be performed by using the delay accuracy of the present delay circuit.
[0091]
As a typical example, it is possible to perform a timing test that uses the marginal performance of a semiconductor test apparatus to determine the speed grade of an LSI under test that requires high setting accuracy.
[0092]
(Embodiment 4)
Finally, a method for testing a semiconductor device using a test waveform from the semiconductor test device described in the third embodiment and a method for manufacturing the semiconductor device will be described with reference to FIG. FIG. 8 shows a flowchart of a method of manufacturing a semiconductor device to be inspected and shipped using the test waveform formed according to the third embodiment.
[0093]
In FIG. 8, the product wafer manufactured in the step S41 is subjected to an initial defect selection by a P inspection (Pellet inspection) in a step S42. Then, the selected non-defective wafer proceeds to step S43 or S45. Whether to proceed to step S43 or step S45 is selected based on the relationship between manufacturing facilities and the like.
[0094]
In step S43, the product wafer is diced, and only non-defective chips are individually packaged in step S44 in a CSP (Chip Size Package), a BGA (Ball Grid Array), or the like. Then, the process proceeds to step S47.
[0095]
Further, in step S45, the formation of a wiring pattern and a protective film on the wafer is further collectively performed, and further, the solder ball is attached. Subsequently, in step S46, the wafer on which the wiring pattern and the like are formed is individually divided by dicing. Then, the process proceeds to step S47.
[0096]
In step S47, a semiconductor device inspection method is performed. That is, the products of the final shape divided individually are subjected to a burn-in test and are finally sorted. Then, the finally good product is shipped in step S48.
[0097]
In the present embodiment, the inspection steps of steps S42 and S47 in FIG. 8 are performed using the test waveform from the semiconductor test apparatus described in the above embodiment. Thus, a high-performance (high-speed operation) semiconductor device (LSI) can be inspected using a test waveform whose timing (time) is controlled with high precision, and a semiconductor device can be manufactured.
[0098]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0099]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0100]
According to the present invention, even if a delay time variation occurs during the calibration of the delay amount of the delay circuit, an error during the calibration can be suppressed, so that a high delay amount setting accuracy of the delay circuit can be realized. .
[0101]
Further, by using a delay circuit calibrated by using the present invention, it is possible to provide a semiconductor test apparatus capable of realizing highly accurate application of a test waveform and highly accurate determination timing of a response signal from a device under test. it can.
[0102]
Furthermore, if a delay circuit calibrated by using the present invention is used, a semiconductor device inspected with a highly accurate test waveform and determination timing can be manufactured.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a timing circuit used in a semiconductor test device according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram showing a delay circuit and a delay amount calibration circuit of a timing circuit in the first embodiment of the present invention.
FIG. 3 is a flowchart illustrating an operation of a delay amount calibration method according to the first embodiment of the present invention.
FIG. 4 is a characteristic diagram showing an effect of a delay amount error on a delay set value in the first embodiment of the present invention.
FIG. 5 is a configuration diagram showing a timing circuit used in a semiconductor test device according to a second embodiment of the present invention.
FIG. 6 is a flowchart illustrating an operation of a delay amount calibration method according to the second embodiment of the present invention.
FIG. 7 is a configuration diagram illustrating a semiconductor test apparatus according to a third embodiment of the present invention.
FIG. 8 is a flowchart illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.
FIG. 9 is a configuration diagram showing a timing circuit used in a semiconductor test device studied as a premise of the present invention.
FIG. 10 is a timing chart showing an operation of generating an edge clock in a semiconductor test device studied as a premise of the present invention.
FIG. 11 is a configuration diagram showing a delay circuit and a calibration circuit of a timing circuit in a semiconductor test device studied as a premise of the present invention.
FIG. 12 is an explanatory diagram showing a table memory of a delay circuit in a semiconductor test device studied as a premise of the present invention.
FIG. 13 is a characteristic diagram showing a delay amount error with respect to a delay set value in a semiconductor test device studied as a premise of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Edge generation circuit, 11 ... Counter, 12 ... Delay circuit, 121 ... Oscillation control circuit, 122 ... Delay element, 123 ... Selector, 124 ... Table memory, 13 ... Data calculation circuit, 14 ... Correction calculation circuit, 15 ... Delay circuit, 151 delay element, 152, 153 selector, 154 oscillation control circuit, 155 table memory, 2 waveform generation circuit, 3 decision circuit, 4 selection circuit, 5 variation amount calculation circuit, 51 … Ring oscillator, 52… cycle measurement circuit, 53… fluctuation ratio calculation circuit, 6… delay amount calibration circuit, 61… cycle measurement circuit, 62… correction operation circuit, 63… calibration control circuit, 8… delay amount calibration circuit, 100 ... Timing circuit, 101: Original vibration, 102: Pattern generation circuit, 103: Fail memory, 104: CPU, 105: Driver, 106: Analog comparison circuit, 107 Tested LSI, 108 ... semiconductor testing device.

Claims (10)

A source circuit, a pattern generation circuit that generates pattern data including information on a test waveform, a timing circuit that receives the source vibration and the pattern data, generates a test waveform, and determines a response waveform from the device under test. A driver for applying the test waveform to the device under test, a comparison circuit for comparing a response waveform from the device under test with a predetermined voltage, and a result determined by a determination circuit in the timing circuit. A semiconductor memory device having a fail memory,
The timing circuit includes a counter that generates a delay at every cycle of the source, a delay circuit that generates a predetermined delay based on the source, and a data operation circuit that calculates a delay amount in the counter and the delay circuit. A waveform generation circuit that generates a test waveform based on the timing of the edge clock output from the delay circuit; a determination circuit that determines a response signal from the device under test based on the edge clock; A semiconductor test apparatus, comprising: a detection circuit for detecting a variation; and a delay amount calibration circuit for correcting the delay variation during calibration of the delay amount of the delay circuit. The semiconductor test apparatus according to claim 1,
The delay amount calibration circuit measures delay amount setting data for obtaining a desired delay time with respect to the delay circuit to be calibrated when the delay amount of the delay circuit is calibrated, and every time the delay amount setting data is measured. A semiconductor test apparatus having a function of acquiring delay time variation from a predetermined reference state, and calibrating the delay amount using the delay amount setting data and the acquired delay time variation data. The semiconductor test apparatus according to claim 1,
The delay amount calibration circuit measures delay amount setting data for obtaining a desired delay time with respect to the delay circuit to be calibrated when the delay amount of the delay circuit is calibrated, and every time the delay amount setting data is measured. A function of calculating a variation ratio of a delay time from a predetermined reference state and correcting the delay amount setting data. The semiconductor test apparatus according to claim 1,
The delay amount calibration circuit measures delay amount setting data for obtaining a desired delay time with respect to the delay circuit to be calibrated when the delay amount of the delay circuit is calibrated, and every time the delay amount setting data is measured. A semiconductor test apparatus having a function of calculating a variation ratio of a delay time from a reference state at the time of starting calibration and correcting the delay amount setting data. The semiconductor test apparatus according to claim 2, 3 or 4,
A semiconductor test apparatus for testing a semiconductor device using a test waveform generated by an edge clock generated using a delay circuit calibrated by the delay amount calibration circuit and a determination timing. A source circuit, a pattern generation circuit that generates pattern data including information on a test waveform, a timing circuit that receives the source vibration and the pattern data, generates a test waveform, and determines a response waveform from the device under test. A driver for applying the test waveform to the device under test, a comparison circuit for comparing a response waveform from the device under test with a predetermined voltage, and a result determined by a determination circuit in the timing circuit. A semiconductor memory device having a fail memory,
The timing circuit includes a counter that generates a delay at every cycle of the source, a delay circuit that generates a predetermined delay based on the source, and a data operation circuit that calculates a delay amount in the counter and the delay circuit. And a fluctuation ratio calculating circuit that detects a delay fluctuation of the delay circuit and calculates a fluctuation ratio from a predetermined reference state, and, among data calculated by the data calculation circuit, delay amount setting data that causes a delay fluctuation. And a correction operation circuit that sets the obtained delay time to the counter and the delay circuit, and a waveform that generates a test waveform based on the timing of the edge clock output from the delay circuit. A generation circuit, a determination circuit for determining a response signal from the device under test based on the edge clock, and detecting a delay variation of the delay circuit A circuit output, the semiconductor test apparatus characterized by and a delay calibration circuit for correcting the delay variation in the calibration of the delay amount of the delay circuit. The semiconductor test apparatus according to claim 6,
The delay amount calibration circuit measures delay amount setting data for obtaining a desired delay time with respect to the delay circuit to be calibrated when the delay amount of the delay circuit is calibrated, and every time the delay amount setting data is measured. A semiconductor test apparatus having a function of acquiring delay time variation from a predetermined reference state, and calibrating the delay amount using the delay amount setting data and the acquired delay time variation data. The semiconductor test apparatus according to claim 6,
The delay amount calibration circuit measures delay amount setting data for obtaining a desired delay time with respect to the delay circuit to be calibrated when the delay amount of the delay circuit is calibrated, and every time the delay amount setting data is measured. A function of calculating a variation ratio of a delay time from a predetermined reference state and correcting the delay amount setting data. The semiconductor test apparatus according to claim 6,
The delay amount calibration circuit measures delay amount setting data for obtaining a desired delay time with respect to the delay circuit to be calibrated when the delay amount of the delay circuit is calibrated, and every time the delay amount setting data is measured. A semiconductor test apparatus having a function of calculating a variation ratio of a delay time from a reference state at the time of starting calibration and correcting the delay amount setting data. The semiconductor test apparatus according to claim 7, 8 or 9,
A semiconductor test apparatus for testing a semiconductor device using a test waveform generated by an edge clock generated using a delay circuit calibrated by the delay amount calibration circuit and a determination timing.

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