JP2007208942A - Acc detecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ACC detecting circuit whose an ACC detection period is a period synchronized with a collar burst signal phase and which can perform an ACC detection stabilized without being influenced by a variance of a collar burst signal phase. <P>SOLUTION: The ACC detecting circuit has a burst origination detection period creation circuitry 3 which outputs a burst origination phase detection pulse c which determines an origination phase and an end phase for a horizontal synchronizing signal as a reference, a burst origination detection circuit 5 which outputs a timing to which a collar burst signal exceeds a predetermined level first as a color burst origination phase pulse d for a period of the burst origination phase detection pulse c, a burst detection period creation circuitry 6 which outputs a first burst gate pulse e which determines the origination phase and the end phase for the color burst origination phase pulse d as the reference, and means 11 and 12 which perform the ACC detection of the collar burst signal inputted into the period of the first burst gate pulse e. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an ACC detection circuit used for amplitude control of a carrier color signal of a color television signal.

  Conventionally, in a circuit for detecting the amplitude of a color burst signal (hereinafter referred to as an ACC detection circuit) in an auto color control circuit (referred to as an ACC circuit) that keeps the carrier color signal amplitude of a color television signal constant, the amplitude of the color burst signal The period (ACC detection period) for detecting the color burst signal is a period determined by a burst gate pulse created with reference to the horizontal synchronization signal, and the color burst signal is detected by detecting the color burst signal with the ACC detection level signal during that period. The amplitude is detected. That is, the conventional ACC detection period is set in synchronization with the horizontal synchronization signal.

  However, the color burst signal can take various phases with respect to the horizontal synchronization signal due to the variation of each channel or the device / transmission system. Further, for example, in the case of NTSC, the color burst signal has a signal width corresponding to nine periods of the color subcarrier, and the phase and amplitude may be distorted at both ends of the color burst signal, that is, at the beginning and end. is there.

  On the other hand, for example, in Patent Document 1, the burst amplitude of an input signal is calculated by a burst amplitude calculation circuit, and the burst amplitude before the color burst signal is calculated from the burst amplitude by the burst pre-edge detection circuit and the post-burst edge detection circuit. Edge and trailing edge are detected, and a variable width burst gate pulse (BGP) generation circuit generates a variable width burst gate pulse between the two edges, or a burst amplitude calculation circuit that calculates the burst amplitude of an input signal In the burst front edge detection circuit, the front edge of the color burst signal is detected from the burst amplitude, a triangular wave is generated starting from the edge position of the front edge pulse, and the burst amplitude and the triangular wave are added. By detecting the maximum amplitude position from the added signal, By generating burst gate pulses with a predetermined fixed width before and after, ACC circuit of the color saturation control is disclosed.

However, in Patent Document 1, in the ACC circuit constituted by an analog signal circuit, the leading edge at the rising edge of the color burst signal is detected from the detected burst amplitude, and the trailing edge at the falling edge of the color burst signal is further detected. Since the burst gate pulse between both edges is obtained, or the burst center is detected and the burst gate pulse having a predetermined width is obtained before and after the burst center, it is determined by both ends of the burst gate pulse. The period, that is, the ACC detection period is not necessarily a period synchronized with the phase of the color burst signal, and there is a problem that stable ACC detection cannot be performed due to the influence of the phase change of the color burst signal.
JP 2004-186767 A

  In view of the above-described problems, the present invention provides an ACC detection circuit in which the ACC detection period is a period synchronized with the color burst signal phase, and stable ACC detection can be performed without being affected by the change in the color burst signal phase. It is intended to do.

  According to one aspect of the present invention, means for outputting a burst start phase detection pulse with a start phase and an end phase determined with reference to a horizontal synchronization signal, and a color burst signal is predetermined during the pulse period of the burst start phase detection pulse. Means for outputting a timing at which the first level is exceeded as a color burst start phase pulse, means for outputting a first burst gate pulse with a start phase and an end phase defined with reference to the color burst start phase pulse, and the first Means for performing ACC detection of the color burst signal during a period defined by one burst gate pulse is provided.

  According to the present invention, by setting the ACC detection period to a period synchronized with the color burst signal phase, stable ACC detection can be performed without being affected by the change in the color burst signal phase.

Embodiments of the invention will be described with reference to the drawings.
Before describing the embodiment of the present invention with reference to FIGS. 1 to 5, a band amplification circuit and a composite color of a color television receiver in which the ACC detection circuit of the present invention is used with reference to FIGS. The signal component of the video signal will be described.

  FIG. 6 is a block diagram showing the configuration of the band amplifier circuit. In FIG. 6, the band amplification circuit 20 includes a first band amplification circuit 22, a color density adjustment circuit 23, a second band amplification circuit 24, an ACC detection circuit 25, and a color killer circuit 26. The input terminal 21 is supplied with a composite color video signal from a first video amplification circuit (not shown), and the input terminal 21 is connected to the first band amplification circuit 22. The first band amplification circuit 22 is connected to a color density adjustment circuit 23, a burst signal amplification circuit 27, and an ACC detection circuit 25. The burst signal amplification circuit 27 is connected to the ACC detection circuit 25, the color killer circuit 26, and the 3.58 MHz signal generation circuit 28. The color density adjustment circuit 23 is connected to the second band amplification circuit 24, and the color killer circuit 26 is connected to the burst signal amplification circuit 27, the 3.58 MHz signal generation circuit 28, and the second band amplification circuit 24. ing. The 3.58 MHz signal generation circuit 28 is connected to the burst signal amplification circuit 27, generates a reference subcarrier (3.58 MHz) based on the burst signal, and supplies the reference subcarrier (not shown) to the color demodulation circuit (not shown). A carrier wave (3.58 MHz) is transmitted. Further, the second band amplification circuit 24 sends the carrier color signal to a color demodulation circuit (not shown) in the next stage.

  The ACC detection circuit 25 in the band amplification circuit 20 detects the amplitude of the color burst signal from the burst signal amplification circuit 27 using the fact that the amplitude of the burst signal transmitted from the broadcasting station is always constant. As a result, a change in the amplitude of the carrier color signal that is not desired to occur due to a change in the reception channel, a fluctuation in the received radio wave, or an antenna system mismatch is detected, and the gain of the first band amplification circuit 22 is detected. By changing the above, control is performed so that the color density of the screen of the television receiver is always constant.

  FIG. 7 is a diagram in which the composite color video signal 31 is decomposed into signal components. The horizontal synchronization signal 32, the video (luminance) signal 33, the color burst signal 34, and the color burst obtained by decomposing the composite color video signal 31 are shown. A chrominance signal (hereinafter referred to as a chroma signal) 35 including a signal and a carrier color signal is shown.

[First Embodiment]
FIG. 1 shows a block diagram of an ACC detection circuit according to the first embodiment of the present invention. 1 correspond to the signals (a) to (e) in FIG. 2, respectively. The signal f in FIG. 1 corresponds to the signal (f) in FIG.

  The ACC detection circuit shown in FIG. 1 has an input terminal 1 to which a composite video signal including horizontal and vertical synchronization signals is input, a synchronization separation circuit 2 that separates a horizontal synchronization signal from the composite video signal, and a horizontal synchronization signal as a reference. A burst start detection period creating circuit 3 for outputting a burst start phase detection pulse c in which a start phase and an end phase of a period slightly larger than the color burst signal period are output to indicate a color burst signal period, and a burst start detection level signal an input terminal 4 for inputting g, and a burst start detection circuit 5 for outputting a color burst start phase pulse d indicating the timing at which the color burst signal first exceeds a predetermined level during the pulse period of the burst start phase detection pulse c; First phase and end phase are defined with reference to the color burst start phase pulse d. The amplification factor (gain) can be controlled by a burst detection period generating circuit 6 for outputting a burst gate pulse e, an input terminal 7 for receiving a chroma signal b including a color burst signal and a carrier color signal, and a control signal. The ACC amplifier circuit 8 that inputs and amplifies the chroma signal b, the full-wave rectifier circuit 9 that outputs the chroma rectified signal f by full-wave rectifying the amplified chroma signal, and the input that receives the ACC detection level signal h A comparison circuit 11 that performs level detection of the color burst signal portion of the chroma rectification signal f using the ACC detection level signal h during a period determined by the terminal 10 and the first burst gate pulse e to obtain an ACC detection output. And a detection means constituted by a sample / hold circuit 12.

The synchronization separation circuit 2 separates and extracts the horizontal synchronization signal (Hsync) a from the composite video signal (including the synchronization signal) input from the input terminal 1.
The burst start detection period creation circuit 3 creates a burst start phase detection pulse c that defines a start phase and an end phase of a period that includes the color burst signal period and is slightly larger than the color burst signal period with the horizontal synchronization signal a as a reference.
The chroma signal b input from the input terminal 7 is amplitude-controlled by the ACC amplifier circuit 8, and then is output as a chroma rectified signal f that has been rectified to one polarity by the full-wave rectifier circuit 9. For the burst signal portion of the chroma rectification signal f, see (f) of FIGS. 3 [A] and [B].

  The burst start detection circuit 5 receives a burst start phase detection pulse c and a chroma rectification signal f, and also receives a burst start detection level signal g that determines the detection level of the start phase of the color burst signal. The detection circuit 5 detects the timing at which the chroma rectification signal f first exceeds the level of the burst start detection level signal g in the period determined by the burst start phase detection pulse c, and transmits the detection timing to the color burst start phase pulse d. Is output.

  The burst detection period creation circuit 6 creates and outputs a first burst gate pulse e that defines a period (that is, an ACC detection period) for detecting the amplitude of the color burst signal with reference to the color burst start phase pulse d. That is, the burst detection period creating circuit 6 outputs the first burst gate pulse e that determines the start phase and end phase of a stable predetermined period of the color burst signal period with reference to the color burst start phase pulse d. Therefore, the first burst gate pulse e provides ACC detection that is accurately synchronized with the color burst signal phase.

The comparison circuit 11 is supplied with the chroma rectification signal f and the first burst gate pulse e and the ACC detection level signal h that determines the ACC detection level from the input terminal 10.
The detection means of the comparison circuit 11 and the sample / hold circuit 12 performs level detection of the burst signal portion of the chroma rectification signal f and the ACC detection level signal h during the period determined by the first burst gate pulse e, and chroma rectification. The area S1 of the portion where the burst signal portion of the signal f is larger than the ACC detection level signal h and the area S2 of the small portion are calculated, and the area ratio between the areas S1 and S2 is held by the sample / hold circuit 12 and ACC detection is performed. Output as a signal.

  The ACC detection signal is input to the ACC amplifier circuit 8 as an ACC amplifier control signal. The ACC amplifier circuit 8 controls the amplification factor (gain) and performs feedback control so that the area ratio is constant.

FIG. 2 shows a timing chart of signals at various parts in FIG. 2A to 2E correspond to the signals a to e of the respective parts in FIG.
2A is a horizontal synchronization signal Hsync separated from the composite video signal by the synchronization separation circuit, and FIG. 2B is a chroma signal including a color burst signal and a carrier color signal, which is the same as described in FIG. It is. FIG. 2 (c) shows a burst start detection period generation circuit 3 which counts the number of clocks corresponding to the time t1 with a counter (not shown) based on the horizontal synchronization signal Hsync to determine the rising timing, that is, the start phase, and the clock for the time t2. Is a burst start phase detection pulse in which the falling timing, that is, the end phase is determined by counting the number corresponding to the above, and includes all the pulse periods of the color burst signal CB of the chroma signal shown in FIG. It has a pulse width.
FIG. 2D shows a color burst start phase pulse indicating the rising edge (start phase) of the color burst signal generated by the burst start detection circuit 5 using the level of the burst start detection level signal g.

FIG. 2 (e) shows a burst detection period generation circuit 6 which uses a counter to count the number of clocks corresponding to the time t3 based on the rising edge of the color burst start phase pulse shown in (d), determines the start phase, and further sets the clock to time. This is a first burst gate pulse that is counted by a number corresponding to t4 to determine the end phase, and the burst signal is stable during the pulse period of the color burst signal CB of the chroma signal shown in (b) (ACC detection). (Period).
Note that the frequency of the counting clock used to determine the pulse period between the start phase and the end phase of the first burst gate pulse e needs to measure (count) the ACC detection period with high accuracy. Further, it is preferable that the frequency is higher than the frequency of the counting clock used to determine the pulse period between the start phase and the end phase of the burst start phase detection pulse c. The frequency of the counting clock used for determining the pulse period of the first burst gate pulse e is, for example, 108 MHz, and the frequency of the counting clock used for determining the pulse period of the burst start phase detection pulse c is, for example, 27 MHz. The frequency may be (= ¼ of the first burst gate pulse e). As described above, the reason why the clock frequency used for determining the pulse period of the burst start phase detection pulse c may be low is that the pulse period of the burst start phase detection pulse c includes a period longer than the color burst signal period. This is because the high measurement (counting) accuracy required to determine the pulse period of the first burst gate pulse e is not required.

  3A and 3B are diagrams for explaining the ACC detection operation with the above-described configuration. The full-wave rectifier circuit 9 rectifies the chroma signal shown in FIG. A waveform obtained by extracting and enlarging a burst signal period portion of the obtained chroma rectified signal is shown. FIG. 3B shows a state where the phase of the color burst signal is changed and delayed with respect to FIG. 3A. (A), (f), (c), (d), (e) in FIG. 3 [A] and [B] correspond to the signals a, f, c, d, e of the respective parts in FIG. Yes.

3A and 3B, the burst start phase detection pulse c is determined as the start phase when a predetermined number of clocks are counted by a counter (not shown) from the rising timing of the horizontal synchronization signal a and time t1 has elapsed. Further, the end phase is determined when the time t2 has elapsed.
The time t2 corresponding to the pulse width of the burst start phase detection pulse c is set to a predetermined time width that includes the period of the color burst signal and is larger than that.

FIG. 3F shows an enlarged color burst signal portion of the chroma rectified signal obtained by rectifying the chroma signal.
The color burst start phase pulse d is a pulse that is output when it is detected that the burst signal portion of the chroma rectification signal in (f) first exceeds a predetermined level, that is, the burst start detection level. The color burst start phase pulse d has a burst (start phase) burst even when the rise timing, that is, the start phase of the color burst signal changes from (f) in FIG. 3A to (f) in FIG. 3B. By detecting the start detection level and counting the clock from the detection timing, the first burst gate pulse e rises after time t3 and further counts the clock, and the first burst gate pulse e falls after time t4 elapses. This defines the ACC detection period.

  Then, in the period of the first burst gate pulse, the comparison circuit 11 and the sample / hold circuit 12 compare the area of the portion where the burst signal portion of the chroma rectified signal is larger and smaller than the ACC detection level. Is supplied to the ACC amplifier circuit 8 as a control signal and gain control is performed. As a result, feedback control is performed so that the ratio of the areas S1 and S2 becomes constant.

  Therefore, if the ACC detection level is set to a high level (however, it is necessary to set the ACC detection level higher than the burst start detection level), the amplitude of the burst signal, that is, the chroma signal to be compared with this, also becomes a high level. Thus, the gain of the ACC amplifier circuit 8 is controlled by the ACC detection signal. If the ACC detection level is set to a low level, the gain of the ACC amplifier circuit 8 is controlled by the ACC detection signal so that the amplitude of the burst signal, that is, the chroma signal is also low. It should be noted that in equipment equipped with an ACC detection circuit, such as a color television receiver, the input amplitude of the chroma signal is different for each receiver or the gain of the subsequent circuit is insufficient, so the ACC detection level is at the factory level. To adjust for each receiver. Note that the ACC detection level may be set to the same value as the burst start detection level.

  When the ACC detection circuit of the present invention is configured by a digital circuit, signal data is input to the ACC detection circuit digitally for each sampling clock. Therefore, the frequency of the counting clock used for determining the pulse period between the start phase and the end phase of the first burst gate pulse e is a multiplication (positive integer multiple) of the sampling frequency of the digital color burst signal. It is preferable. That is, the first burst gate that determines the ACC detection period by setting the frequency of the count clock used to determine the pulse period of the first burst gate pulse e to a multiple of the sampling frequency of the digital color burst signal The start phase of pulse e (intersection P1 between the full-wave rectification pulse and the ACC detection level in FIGS. 3A and 3B) and the end phase (full-wave rectification pulse and ACC detection in FIGS. 3A and 3B). The intersection P2) with the level can be accurately determined with reference to the color burst start phase pulse d which always indicates the rising edge of the color burst signal even if there is a burst phase change.

  With the above configuration, even if there is a phase change in the color burst signal CB, the color burst signal phase and the burst gate pulse phase coincide with each other before and after the burst phase changes. That is, the burst gate pulse e always has a phase synchronized with the color burst signal CB, and ACC detection can be performed without being affected by the change in the color burst signal phase.

  Further, when the ACC detection circuit is performed by digital signal processing, the first burst gate pulse rises (starts) from the time when a predetermined number of clocks are accurately counted by the counter from the rise of the color burst start phase pulse d, that is, the color burst signal. And a predetermined number of clocks are accurately counted so that the first burst gate pulse falls (ends) before the end of the period of the color burst signal. It is possible to perform ACC detection during the period.

[Second Embodiment]
FIG. 4 shows a block diagram of an ACC detection circuit according to the second embodiment of the present invention. The same parts as those shown in FIG.
In the second embodiment, a burst detection period creating circuit 13 and a switching circuit 14 are added to the first embodiment. That is, the first burst gate pulse e from the burst detection period creation circuit 6 and the second burst gate pulse i from the burst detection period creation circuit 13 are input to the switching circuit 14, and the first and second burst gate pulses are input. Either one of the burst gate pulses is switched to be output to the comparison circuit 11. Other configurations are the same as those of the embodiment of FIG.

The burst detection period creating circuit 13 creates a second burst gate pulse i that determines a period (that is, an ACC detection period) in which the amplitude of the color burst signal is detected based on the horizontal synchronization signal a extracted by the synchronization separation circuit 2. And output. That is, the second burst gate pulse is output at a timing synchronized with the horizontal synchronization signal.
The switching circuit 14 selects one of the second burst gate pulse i and the first burst gate pulse e shown in the first embodiment, and outputs it as a burst gate pulse j.
The ACC detection is performed by the comparison circuit 11 using the ACC detection level signal h as in the first embodiment, with the burst gate pulse j as the ACC detection period.

  Switching of the switching circuit 14 is controlled by the state of the chroma signal b input to the input terminal 7. That is, when the state of the input chroma signal b is normal, the first burst gate pulse e synchronized with the phase of the color burst signal (created with reference to the color burst start phase pulse d) is output. Is switched by the burst start detection circuit 5 for reasons such as when the input chroma signal is noisy, when there is no color burst signal, or when the signal level of the color burst signal is very low. When the color burst start phase pulse d cannot be accurately detected, switching is performed so as to output the second burst gate pulse i created with reference to the horizontal synchronization signal (Hsync) a.

  5A and 5B are timing charts for explaining the generation of the second burst gate pulse output from the burst detection period creating circuit 13 added in FIG. 4 in relation to the chroma rectification signal. That is, FIGS. 5A and 5B show the case where the switching circuit 14 bursts when the chroma signal input to the input terminal 7 of FIG. 4 is noisy, when there is no color burst signal, or when it is very small. 6 shows a timing chart for explaining the operation when the output of the detection period creation circuit 13 is selected. FIG. 5B shows a state where the phase of the color burst signal is changed and delayed with respect to FIG. 5A.

In FIG. 5A, (a) is a horizontal synchronizing signal Hsync that is synchronously separated from the composite video signal, and (f) is an enlarged view of the color burst signal portion of the chroma rectified signal obtained by rectifying the chroma signal. ing. (i) shows a second burst gate pulse created by the burst detection period creation circuit 13, and is not shown with reference to the horizontal synchronization signal Hsync of (a) (from the rising timing of the horizontal synchronization signal a). When a predetermined number of clocks are counted by the counter and the time t5 has elapsed, the start phase is determined, and when the time t6 has further elapsed, the end phase is determined. The frequency of the count clock used at this time is 27 MHz, for example.
However, as shown in FIG. 5B, when the color burst signal phase of the chroma signal changes from the state of FIG. 5A, the second burst gate pulse i is synchronized with the horizontal synchronization signal, but the chroma signal. Since the burst signal portion of the chroma rectified signal by the comparison circuit 11 and the sample / hold circuit 12 is compared with the area S1 which is larger than the ACC detection level and the area S2 which is smaller than the color burst signal of FIG. Before the change [A] and after [B], the area S1 of the portion larger than the ACC detection level and the area S2 of the smaller portion are different. Therefore, the ACC detection is easily affected by the burst phase change.

As described above, when the input chroma signal has a lot of noise, or when the color burst signal is absent or very small, the first burst gate pulse based on the color burst signal cannot be used. Switching to the burst detection period generation circuit 13 has a drawback that it is easily affected by a burst phase change, but it is possible to perform ACC detection using the second burst gate pulse that can be generated based on the horizontal synchronization signal as an ACC detection period. Therefore, if the ACC detection circuit of the second embodiment is mounted on a color television receiver, the functionality of the receiver can be expanded.
In the embodiment described above, sample / hold area comparison is used as means for detecting the level of the color burst amplitude, but peak detection may also be used.

The block diagram of the ACC detection circuit of the 1st Embodiment of this invention. The timing chart of the signal of each part of FIG. The timing chart explaining ACC detection operation. The block diagram of the ACC detection circuit of the 2nd Embodiment of this invention. 6 is a timing chart for explaining generation of a second burst gate pulse output from the burst detection period creating circuit provided in FIG. 4 in relation to a chroma signal. The block diagram which shows the structure of a band amplifier circuit. The figure which decomposed | disassembled the composite color video signal into the signal component.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Input terminal of composite video signal 2 ... Synchronization separation circuit 3 ... Burst start detection period creation circuit 4 ... Input terminal of burst start detection level signal 5 ... Burst start detection circuit 6, 13 ... Burst detection period creation circuit 7 ... Chroma signal Input terminal 11: Comparison circuit 12 ... Sample / hold circuit

Claims (5)

Means for outputting a burst start phase detection pulse in which a start phase and an end phase are determined based on a horizontal synchronization signal;
Means for outputting, as a color burst start phase pulse, a timing at which a color burst signal first exceeds a predetermined level during a pulse period of the burst start phase detection pulse;
Means for outputting a first burst gate pulse in which a start phase and an end phase are determined with reference to the color burst start phase pulse;
Means for performing ACC detection of the color burst signal during a period determined by the first burst gate pulse;
An ACC detection circuit comprising: Means for outputting a second burst gate pulse having a start phase and an end phase determined with reference to the horizontal synchronization signal;
Means for selecting and outputting either one of the first burst gate pulse and the second burst gate pulse; and
2. The means for performing ACC detection performs ACC detection of the color burst signal during a period determined by one burst gate pulse selected from the first and second burst gates. The ACC detection circuit according to 1.   The ACC detection circuit according to claim 1 or 2 is composed of a digital signal circuit, and a frequency of a clock for counting a pulse period between the start phase and the end phase of the first burst gate pulse is a digital color burst. The ACC detection circuit according to claim 1 or 2, wherein the sampling frequency of the signal is multiplied.   The frequency of the clock that counts the pulse period between the start phase and the end phase of the first burst gate pulse is higher than the frequency of the clock that counts the pulse period between the start phase and the end phase of the burst start phase detection pulse. The ACC detection circuit according to claim 1, wherein the ACC detection circuit is also high.   5. The period for performing the ACC detection is set to a period having a cycle number smaller than a color burst signal period having a predetermined cycle number in a predetermined color television signal system. The ACC detection circuit according to claim 1.

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