JP2006005447A - Television broadcasting receiver and agc circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a television broadcast receiver that attains a small scale by adopting a digital processing circuitry for a video detection section and an AGC circuit respectively and accommodating them integrally to a one-chip IC. <P>SOLUTION: The video detection section 14 for receiving a digital intermediate frequency signal IF adopts digital processing circuitry and a digital processing AGC circuit 16 is adopted for the AGC circuit, and the AGC circuit 16 is integrated into the video detection section 14 and they are integrated into a one-chip IC, and the AGC circuit 16 generates an AGC voltage Vagc on the basis of a difference between a prescribed threshold value and the level of a video composite signal outputted from the video detection section 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a television (hereinafter also abbreviated as TV) broadcast receiver, particularly an analog TV broadcast receiver, and an AGC (Automatic Gain Control) circuit used therefor.

  Digital TV broadcasting has already started in December 2003, while analog TV broadcasting is scheduled to stop in 2011.

  Under such circumstances, manufacturers are placing more emphasis on developing digital TV broadcast receivers. On the other hand, analog TV broadcasting will continue for a while, so the development of an analog TV broadcast receiver cannot be completely stopped.

  Therefore, as a measure for both, it is beneficial to develop an analog TV broadcast receiver directed to a digital TV broadcast receiver in the future development of the analog TV broadcast receiver.

  For example, when developing a tuner for an analog TV broadcast receiver, it is beneficial to develop it so that it can be shared with a tuner for a digital TV broadcast receiver.

  Also, when developing a video detector, AGC circuit, video amplifier, etc. in an analog TV broadcast receiver, the design should be adapted to digital processing as much as possible. As a result, when designing as an IC, it is beneficial to make the IC common between the analog TV broadcast receiver and the digital TV broadcast receiver.

  The present invention pays particular attention to the AGC circuit. Since this AGC circuit is based on voltage control related to gain adjustment in a tuner such as setting of contrast, there has been only an analog processing type so far. In the present invention, the AGC circuit is a digital processing AGC circuit, and the video detection unit is also a digital processing type. Ultimately, the AGC circuit is incorporated in the video detection unit.

  As known techniques related to the AGC circuit, there are the following [Patent Document 1] and [Patent Document 2]. [Patent Document 1] is a receiving apparatus that selects the best channel by comparing the reception status of teletext broadcasting of each channel when there are a plurality of channels. Among them, the AGC voltage is supplied to the AGC level detection unit. In other words, detection by channel is disclosed. [Patent Document 2] discloses an AGC circuit for a vertical ramp signal in which the response time of the AGC circuit can be shortened.

JP-A-5-219484 Japanese Patent Laid-Open No. 11-88797

  First, the inventor of this application digitalizes an analog TV broadcast receiver from a circuit at the next stage of the tuner unit, and first digitizes an intermediate frequency signal from the tuner unit via an AD conversion unit. As a result, the video detection unit, which is the next-stage circuit, is digitally processed, and an IC is realized.

  Next, the present inventor attempted to digitally process the AGC circuit. However, it was difficult to digitally process the AGC circuit because the tuner serving as an output port of the AGC circuit is an analog processing type.

  Here, the inventor of the present application has come up with the idea that the video detector and the AGC circuit can be easily combined through the video composite signal. Accordingly, an object of the present invention is to propose an AGC circuit integrated with a video detector and to propose an analog TV broadcast receiver that employs the AGC circuit.

  Before showing the basic configuration of the present invention, the configuration which is the premise of the present invention devised by the present inventor will be described.

  FIG. 6 is a basic configuration diagram of a TV broadcast receiver as a premise of the present invention. In particular, this figure is a prototype of an analog TV broadcast receiver aimed at digital processing. For this purpose, first, as described above, the AD conversion unit 3 for digitization is introduced from the next stage of the tuner unit 2. As is well known, the tuner unit 2 is an intermediate obtained by mixing an RF input, that is, a television (TV signal) with a high frequency amplification stage (RF AMP) for amplifying the input and a local oscillation output by a mixer (not shown). An intermediate frequency amplification stage (IF AMP) for amplifying the frequency signal.

  The intermediate frequency signal from the IF AMP is converted into a digital intermediate frequency signal by the AD (Analog to Digital) conversion unit 3 and input to the video detection unit 4. Therefore, the video detection unit 4 is a digital processing type video detection unit 4 and detects the digital intermediate frequency signal to extract a digital video composite signal (luminance signal and carrier color signal). This video composite signal Scp is converted into an analog video output by a DA (Digital to Analog) conversion unit 5, then sent to the video amplifier unit described above on one side and sent to the AGC circuit 6 on the other side. The AGC circuit 6 generates an analog AGC voltage and feeds it back to the tuner unit 2.

  The analog TV broadcast receiver 1 shown in this figure enables the video detection unit 4 to be integrated with an IC. However, the AGC circuit 6 is still an analog processing type and becomes an external circuit with respect to the IC. In order to return the video composite signal Scp (digital) to the analog processing AGC circuit 6, a branch structure from the output of the DA converter 5 is essential, which eventually increases the circuit scale.

  Therefore, according to the present invention, the AGC circuit 6 is configured as a digital processing type AGC circuit, and the digital processing type AGC circuit is integrally incorporated in the IC constituting the video detection unit 4.

  FIG. 1 is a basic configuration diagram of a TV broadcast receiver according to the present invention. Note that the same reference numerals or symbols are given to the same components throughout the drawings.

  The analog TV broadcast receiver 1 shown in this figure is different from the prototype of FIG. 6 described above in the following points.

  First, the analog processing type AGC circuit 6 described above is replaced with a digital processing type AGC circuit 16. The digital processing type AGC circuit 16 is integrated into the IC constituting the digital processing type video detection unit 4 to form the video detection unit 14 with an AGC circuit. In this case, the AGC voltage Vagc is generated based on the difference between the level of the luminance signal (Y) component forming the video composite signal Scp output from the video detection unit 14 and the threshold value, and is returned to the tuner unit 2.

  As described above, the analog TV broadcast receiver 1 according to the present invention includes a tuner unit 2 having a high frequency amplification stage (RF AMP) that receives a TV signal and an intermediate frequency amplification stage (IF AMP) that follows the high frequency amplification stage. An analog TV broadcast receiver comprising: a video detection unit that receives an intermediate frequency signal Sif from a frequency amplification stage; and an AGC circuit that feeds back an AGC voltage Vagc for gain adjustment to the tuner unit 2. A digital intermediate frequency signal obtained by AD-converting the intermediate frequency signal Sif is input to the above-described video detection unit as a digital processing type video detection unit 14 and the above AGC circuit as a digital processing type AGC circuit 16. The processing type AGC circuit 16 is configured to be incorporated in the digital processing type video detection unit 14, and the digital processing type AGC circuit 16 includes: The AGC voltage Vagc is generated based on the difference between the level of the luminance signal (Y) component forming the video composite signal Scp output from the digital processing video detector 14 and a predetermined threshold value.

  As a result, the AGC circuit 16 and the video detection unit 14 are configured by a one-chip IC, and the connection structure between the input of the AGC circuit 16 and the output of the DA conversion unit 5 becomes unnecessary, and reception is possible. The circuit scale of the machine 1 is reduced.

  As will be described later, (i) the level of the input TV signal is detected with the level of the synchronizing signal in the luminance signal component, thereby improving the detection accuracy. (Ii) A digital low-pass filter is used for detecting the level of the synchronization signal, thereby facilitating the implementation of an IC. (Iii) A threshold value is used for the level determination of the synchronization signal, and this threshold value is stored in the threshold value register so that it can be arbitrarily set from the outside. (Iv) The output from the AGC circuit 16 is a PWM conversion output, thereby enabling smooth coupling between the digital AGC circuit 16 and the analog tuner unit 2. (V) A calculation unit for increasing / decreasing the difference between the level of the synchronization signal and the threshold value is provided, and the convergence speed of the AGC voltage can be arbitrarily adjusted.

  FIG. 2 is a diagram showing a schematic functional block of the video detection unit 14.

  First, the functional blocks of the digital processing type video detection unit 14 itself will be described. The analog intermediate frequency signal Sif from the tuner unit 2 is converted into a digital intermediate frequency signal IF through the AD conversion unit 3 and then applied to the digital video detection unit 14. Is done.

  A BPF (Band Pass Filter) 21 is provided at the first stage of the video detection unit 14 and cuts out only the video carrier. Further, AM demodulation is performed on the cut video carrier by the AM demodulating circuit 22, and a video composite signal Scp is obtained through an LPF (Low Pass Filter) 23. The present invention directly applies this video composite signal Scp to the built-in digital processing AGC circuit 16 in the same IC chip.

  FIG. 3 is a waveform diagram showing an example of the video composite signal Scp.

  This figure illustrates the simplest waveform of the video composite signal Scp for one horizontal line (1H). This video composite signal Scp comprises a basic luminance signal (Y) component, and includes a synchronizing signal (horizontal synchronizing signal) SYC. The reception level of the input TV signal is substantially proportional to the amplitude of the video composite signal Scp, and the AGC voltage Vagc can be generated by detecting the amplitude and calculating the difference from the threshold value. In this case, the amplitude is unstable because it changes according to the change of the video signal. Therefore, the AGC circuit 16 preferably detects the level of the synchronizing signal SYC which is stable regardless of the video signal and which is the maximum value of the TV radio wave. Then, the increase / decrease of the AGC voltage Vagc is controlled according to the difference between the SYC level and the threshold value.

  FIG. 4 is a diagram showing a configuration example (No. 1) of the AGC circuit 16 according to the present invention.

  In this figure, the digital processing type AGC circuit 16 has a level detection unit 31 for detecting the level of the synchronization signal SYC in the luminance signal (Y) component at the first stage, and finally the level is detected according to the detected level of the synchronization signal SYC. AGC voltage Vagc is generated.

  In general, a so-called Y / C separator that extracts a Y signal can be used as the level detection unit 31. In the present invention, the level detection unit 31 is configured by a low-pass filter (LPF). Is desirable. As described above, the level of the input TV radio wave is detected with the maximum level of the synchronization signal SYC, but it is easily affected by noise and the like. Normally, a noise removal circuit by analog processing is used for this noise removal. However, in the present invention, since the digital processing AGC circuit 16 is constituted, the noise removal circuit is a digital filter (digital low-pass filter). ).

  The level of the synchronization signal obtained in this way is compared with a predetermined threshold value to perform final AGC. For this purpose, the digital processing type AGC circuit 16 in this figure sets the level of the synchronization signal SYC to the predetermined level. A comparison unit 34 for comparing with a threshold value is provided, and a final AGC voltage Vagc is generated according to the difference D obtained by the comparison.

  In this case, it is preferable to form a threshold value register 37 for arbitrarily setting the predetermined threshold value from the outside. In the case of a general analog processing type AGC circuit, the threshold value is set by changing the level of an analog voltage applied from the outside. However, in the present invention, the threshold value can be freely set as digital data from the outside. it can. The threshold value register 37 stores the digital data, and the value is given to one comparison input of the comparison unit 34.

  The other comparison input of the comparison unit 34 is given the level of the synchronization signal from the level detection unit 31. In this case, as shown in this figure, the average value is obtained every time a predetermined number of levels of the synchronization signal are sampled. And a maximum value holding unit 33 that selects the maximum value among these average values and holds it in one horizontal synchronization section and inputs it to the above-described comparison unit 34.

  The level of the synchronization signal SYC is detected by sampling during a period of 4.7 μs (see FIG. 3) under digital processing. If 1000 sampling is performed as an example during the 4.7 μs, the average value calculation unit 32 obtains an average value of sampling levels of 100 samplings. In this example, 10 (= 1000/100) average values are obtained. Thus, for example, taking the average value for every 100 samplings, although the level of the synchronization signal SYC is stable, actually it does not become an ideal flat waveform as shown in FIG. This is because the level varies considerably during the period of 4.7 μs due to various factors such as noise.

  In order to obtain the AGC voltage, in the above example, the maximum value among the ten average values is selected and used as the comparison input to the comparison unit 34. In this case, during one horizontal synchronization period, so-called 1H, the maximum value is continuously held and given to the comparison unit 34. The reason why the maximum value is held for 1H, that is, 63.5 μs, is that synchronization is performed until the next synchronization signal arrives and a new maximum value of the level is given to the comparison unit 34. This is to prevent the detection level from being influenced by signal components other than the signal. That is, the comparison with the threshold is executed when the level of the synchronization signal is detected one after another. The counter 36 sets the holding period of 63.5 μs at this time.

  In this way, the comparator 34 detects and outputs the difference D between the level of the input TV signal and the threshold value. The difference D is digital data, which is supplied to a PWM (Pulse Width Modulation) conversion unit 35, where a PWM signal having a pulse width that changes in accordance with the difference is generated. Return as voltage Vagc.

  It is easy to generate a PWM signal in digital processing, and it is also easy to return this PWM signal to an analog AGC voltage in the tuner unit 2 for analog processing. For example, if the PWM signal is passed through a pulse width / voltage conversion circuit (not shown), the pulse width signal can be easily converted into an analog AGC voltage signal. This pulse width / voltage conversion circuit can be constituted by, for example, a buffer that receives the PWM signal and a capacitor that accumulates the voltage of the buffered PWM signal.

  It is desired that the AGC voltage obtained in this way has a good response to the difference. This is a so-called convergence speed problem. FIG. 5 shows a configuration that copes with this problem.

  FIG. 5 is a diagram showing a configuration example (No. 2) of the AGC circuit 16 according to the present invention.

  The difference between FIG. 5 and FIG. 4 is that a calculation unit 38 that powers the difference D described above is introduced between the comparison unit 34 and the PWM conversion unit 35. Then, the PWM signal is changed according to the power difference. As the power, for example, square is appropriate.

  When the difference D is small, if the increase / decrease width of the difference D is relatively large, the AGC voltage hardly converges to a predetermined constant value, and in the worst case, the AGC voltage oscillates. For this reason, the small difference D is converted to a smaller difference by raising the power. On the other hand, when the difference D is large and the increase / decrease width of the difference D is relatively small, it takes time to converge the AGC voltage to an intended constant value. For this reason, in order to rapidly converge the AGC voltage to a predetermined constant value, the large difference D is converted to an even larger difference by raising it to a power. For example, if the small difference 0.5 is squared, the increase / decrease width of the control is suppressed to 0.25. Conversely, if the large difference 5 is squared, the increase / decrease width of the control is expanded to 25.

If it is desired to further finely adjust the power difference (squared) difference D as described above, the power difference D may be further multiplied by a predetermined coefficient. This predetermined coefficient is indicated by α in the figure, and becomes αD ² as a whole.

  As described above, the description has been given focusing on the configuration of the analog TV broadcast receiver as a whole receiver, but the present invention can also be understood from the viewpoint of a novel AGC circuit.

  That is, the new AGC circuit is first integrated with a video detection unit that receives the intermediate frequency signal Sif from the intermediate frequency amplification stage IF AMP, and an AGC voltage for gain adjustment is fed back to the intermediate frequency amplification stage. This is an AGC circuit.

  In this case, by inputting the digital intermediate frequency signal IF obtained by AD-converting the intermediate frequency signal Sif, the above-described video detection unit becomes the digital processing type video detection unit 14, and the above AGC circuit is converted into the digital processing type. AGC circuit 16 of FIG. Thereby, the digital processing type AGC circuit 16 is integrated with the digital processing type video detection unit 14 (integrated IC). Thus, the digital processing type AGC circuit 16 calculates the above-described AGC voltage (Vagc) based on the difference between the level of the luminance signal component forming the video composite signal Scp output from the digital processing type video detection unit 14 and the predetermined threshold value. It is generated and returned to the tuner unit 2.

  The present invention is a useful technique for partial integration of an analog TV broadcast receiver, which is required when an analog TV broadcast receiver is gradually brought closer to a digital TV broadcast receiver.

1 is a basic configuration diagram of a TV broadcast receiver according to the present invention. 3 is a configuration diagram showing a schematic functional block of a video detection unit 14. FIG. It is a figure which shows an example of the video composite signal Scp. It is a figure which shows one structural example (the 1) of the AGC circuit 16 which concerns on this invention. It is a figure which shows one structural example (the 2) of the AGC circuit 16 which concerns on this invention. 1 is a basic configuration diagram of a TV broadcast receiver as a premise of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Television (TV) broadcast receiver 2 Tuner part 3 AD conversion part 4 Image | video detection part 5 DA conversion part 6 AGC circuit Scp Image composite signal 14 Image | video detection part 16 AGC circuit 21 BPF
22 AM demodulation circuit 23 LPF
31 level detection unit 32 average value calculation unit 33 maximum value holding unit 34 comparison unit 35 PWM conversion unit 36 counter 37 threshold counter 38 calculation unit

Claims (10)

A tuner unit having a high-frequency amplification stage that receives a television signal and an intermediate-frequency amplification stage following the high-frequency amplification stage, a video detection unit that receives an intermediate-frequency signal from the intermediate-frequency amplification stage, and gain adjustment to the tuner part A television broadcast receiver comprising an AGC circuit for feeding back an AGC voltage for
With the digital intermediate frequency signal obtained by AD conversion of the intermediate frequency signal as an input, the video detection unit becomes a digital processing type video detection unit,
The AGC circuit is a digital processing type AGC circuit, and the digital processing type AGC circuit is configured to be incorporated in the digital processing type video detection unit,
Here, the digital processing type AGC circuit generates the AGC voltage based on a difference between a level of a luminance signal component forming a video composite signal output from the digital processing type video detection unit and a predetermined threshold value. A featured television broadcast receiver.   The digital processing AGC circuit includes a level detection unit that detects a level of a synchronization signal in the luminance signal component, and generates the AGC voltage according to the detected level of the synchronization signal. The television broadcast receiver according to 1.   The television broadcast receiver according to claim 2, wherein the level detection unit includes a digital low-pass filter.   2. The digital processing type AGC circuit includes a comparison unit that compares the level of the synchronization signal with the predetermined threshold value, and generates the AGC voltage according to a difference obtained by the comparison. The television broadcast receiver described in 1.   5. The television broadcast receiver according to claim 4, wherein the digital processing AGC circuit includes a threshold register for arbitrarily setting the threshold from the outside.   The digital processing-type AGC circuit selects an average value calculating unit that calculates an average value every time a predetermined number of levels of the synchronization signal are sampled, and selects a maximum value among these average values and selects this in one horizontal synchronization interval The television broadcast receiver according to claim 4, further comprising a maximum value holding unit that holds and inputs the maximum value to the comparison unit.   5. The television broadcast receiver according to claim 4, wherein the digital processing AGC circuit includes a PWM conversion unit that outputs a PWM signal having a pulse width that changes in accordance with the difference from the comparison unit. .   The calculation unit for raising the power to the difference is provided between the comparison unit and the PWM conversion unit, and the pulse width of the PWM signal is changed according to the power difference. Television broadcast receiver.   The television broadcast receiver according to claim 8, wherein the calculation unit further multiplies the power difference by a predetermined coefficient. An AGC circuit that is integrated with a video detection unit that receives an intermediate frequency signal from an intermediate frequency amplification stage and feeds back an AGC voltage for gain adjustment to the intermediate frequency amplification stage,
Using the digital intermediate frequency signal obtained by AD conversion of the intermediate frequency signal as an input, the video detection unit is a digital processing type video detection unit, the AGC circuit is a digital processing type AGC circuit, and the digital processing type AGC circuit is The digital processing type AGC circuit is integrated with the digital processing type video detection unit, wherein the digital processing type AGC circuit generates the AGC voltage based on a luminance signal component forming a video composite signal output from the digital processing type video detection unit. An AGC circuit generated.

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