JP2007208519A - Image processor and image processing method, and computer-readable recording medium with program for making computer perform image processing method recorded - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform high speed processing by efficiently using a halftone pattern for a plotting object being the same tone value, and to reduce the capacity of a halftone pattern memory by successively searching the shift value of the horizontal direction of the halftone pattern for every plotting word. <P>SOLUTION: This image processor is provided with a halftone threshold storage device 216 for storing the halftone threshold of halftone patten X width for Y width of the halftone pattern, a halftone pattern memory 227 for storing the halftone patten of plotting word X width for the Y width of the halftone pattern, a halftone pattern generating device 231 for performing gradation processing with the halftone threshold, a halftone pattern address generating device 221 for generating the halftone pattern address value from the Y value of a horizontal line, a halftone pattern shift value generating device 226 for generating the halftone pattern shift value from the X value of the horizontal line and a cyclic shift device 228 for performing the cyclic shift for the halftone pattern shift value with the halftone pattern. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image processing apparatus and an image processing method that can be mounted on an image forming apparatus such as a digital copying machine and a printer, and a computer-readable recording medium that records a program that causes a computer to execute the image processing method.

  Conventionally, in a page printer or the like, due to an increase in resolution and a high speed requirement, it has become difficult to satisfy this requirement only with the performance of the CPU. In particular, a color printer requires various processes such as various image processes, C, M, Y, and K image drawing processes, color conversion processes, and halftone processes.

  The flow of processing in a conventional printer is to analyze a PDL (page description language) received from a network, generate an intermediate language that can be executed by the drawing device, analyze the intermediate language by the drawing device, and convert the gradation to the band memory. Renders the processed image, encodes it with a binary image compression algorithm (such as JBIG), stores the code in the memory, and then reads the code data from the memory after each plate is delayed at the time of printout The data is decrypted by the above compression algorithm, and then transferred to a printer engine for data corresponding to each of the C, M, Y, and K plates and printed.

  As a compression method, JBIG (Joint Bi-level Image experts Group), which is an international standard of a binary image encoding method adopting an arithmetic encoding method, is known.

  In addition, a drawing apparatus that analyzes the intermediate language and draws an image after gradation processing in a band memory needs to perform halftone processing at high speed. Techniques have been disclosed for speeding up the halfton process or making the hardware scale relatively compact (see, for example, Patent Documents 1 and 2). Patent Document 1 uses a low-speed and inexpensive (small-scale) memory element to store the entire dither pattern, and temporarily stores only the data required during the binarization process in a high-speed (large-scale) rewritable memory. The threshold data is read out from the data and binarized. This is aimed at achieving both high speed and hardware scale. Patent Document 2 tries to realize high-speed processing by reading out Nx × Ny portion data from a Wy × Wx dither matrix and processing the Nx × Ny portion dots in parallel by hardware. It was something to do.

  By the way, the halftone processing apparatus can be roughly divided into two according to the image processing method for performing the halftone processing. First, as shown in FIG. 28, the intermediate language 1 is created by drawing multi-value image data by the multi-value drawing device 2 in band units or page units, and then the generated band unit or page This is a multi-valued image drawing method in which unit image data (CMYK band data 3) is read and halftone processing is performed by the halftone processing device 4 to obtain band data 5 after gradation processing. The other is a post-gradation processing image rendering method in which the intermediate language 1 is rendered directly after the gradation processing by the data rendering device 6 after the gradation processing in band units or page units as shown in FIG.

  As a multi-value image drawing method, the threshold data read from the threshold matrix memory is loaded into the register so that all threshold data applied to the process can be reused until the processing scan line is completed. Selectively output to a plurality of comparison means to execute parallel comparison processing. The threshold data set in the register is sequentially shifted and used repeatedly (see, for example, Patent Documents 3, 4, and 5). The configuration and operation of Patent Document 3 are disclosed in paragraph numbers 0036 to 0042 of this document. The configuration and operation of Patent Document 4 are disclosed in paragraph numbers 0026 and 0027 of this document. The configuration and operation of Patent Document 5 are disclosed in paragraph numbers 0043 to 0050 of this document.

  Further, as the same method, 256 binary matrix data obtained by binarizing the halftone threshold matrix data with 256 level gradation values without generating the halfton threshold matrix data are generated, One that sequentially selects and draws is disclosed (for example, see Patent Document 6). The configuration and operation of Patent Document 6 are disclosed in paragraph numbers 0025 to 0032 of this document.

  As the image rendering method after gradation processing, binary matrix data binarized by gradation values is created in advance from halftone threshold matrix data, and the least common multiple of the memory boundary width of the rendering unit and the width of the basic bit pattern It is known that an image after gradation processing is drawn at high speed by creating a halftone pattern and repeatedly drawing in the horizontal direction sequentially with a halftone repeat function (see, for example, Patent Document 7). The configuration and operation of Patent Document 7 are disclosed in paragraph numbers 0011 to 0021 of this document.

  Also, the halftone threshold value corresponding to at least the scan line period corresponding to the start point / end point of the scan line obtained by the edge calculation means is read, binarized by the gradation value, sequentially shifted, and repeatedly drawn. Thus, it is known that an image after gradation processing is drawn at high speed (see, for example, Patent Document 8). The configuration and operation of Patent Document 8 are disclosed in paragraph numbers 0013 to 0015 of this document.

  In addition, when information included in the intermediate data is analyzed to predict the degree of binarization speedup and the speedup can be expected, at least the scan corresponding to the start / end point of the scan line drawing obtained by the edge calculation means When the halftone threshold value for the line period is read, binarized by the gradation value, sequentially shifted, and repeatedly rendered, the image after gradation processing is rendered at high speed, and high speed cannot be expected. The binarization is performed on the color information of the intermediate data of the drawing object, and the binarized halftone pattern corresponding to the start / end points of the scan line drawing obtained by the edge calculating means is sequentially shifted and drawn repeatedly. Thus, it is known to draw an image after gradation processing at high speed (see, for example, Patent Document 9). The configuration and operation of Patent Document 9 are disclosed in paragraph numbers 0012 to 0016 of this document.

JP-A-1-256873 JP-A-7-203204 JP 2000-92321 A JP 2000-165672 A JP 2001-150739 A JP 2000-231632 A Japanese Patent No. 3446324 JP 2000-92315 A JP 2000-90259 A

  However, the conventional techniques as described above have the following problems. In the multi-value image drawing method, it is necessary to store multi-value data in band units or page units in advance by multi-value drawing processing, which requires a lot of memory. Further, when high-speed processing is required to perform halfton processing even on a portion where nothing is drawn, it has been necessary to perform a lot of parallel processing with large hardware.

  The methods disclosed in Patent Documents 3, 4, and 5 have a large logic hardware scale. However, the method disclosed in Patent Documents 3, 4, and 5 is high-speed for photographic image data in which the tone value of source image data to be halftoned changes sequentially. Although halftoning can be performed, the logic scale of the logic increases when a plurality of halftoning processes are performed simultaneously. In addition, the method disclosed in Patent Document 6 is a high-speed copy of image data after halfton processing with respect to a graphics image in which the logic hardware scale is small but the gradation value does not change much. However, in an image in which gradation values change sequentially, the number of images to be copied decreases, and the speed cannot be increased. In addition, since the binary matrix data after the halfton process must be stored in the memory for 256 levels, a large memory capacity is required.

  In addition, in the post-gradation image rendering method, it is necessary to have a multi-valued band or page memory, unlike the multi-value image rendering method described above, in order to render an image after gradation processing directly in band units or page units. There is no problem, and it is necessary to have a band or page memory after gradation processing, so the amount of memory to be used is basically small, but the processing is complicated because gradation processing is simultaneously performed at the time of drawing. was there.

  In the method of Patent Document 7, binary matrix data binarized by gradation values is created in advance from halftone threshold matrix data, and the memory boundary width of the rendering unit and the width of the basic bit pattern are created. A halftone pattern of the least common multiple of the base bit pattern is created, and the halftone repeat function repeatedly draws in the horizontal direction one after the other. After creating the halftone pattern, it is only necessary to repeatedly draw in the horizontal direction, and the hardware scale can be reduced and the speed can be increased. However, in recent years, the demand for high-speed memory has increased the drawing word X width. For example, when the drawing word X width is 128 bits and the halftone pattern X width is 20 bits, as shown in FIG. 640, 5 times the drawing word X width is required, and if the halftone pattern Y width is 16 bits, a large capacity memory of 80 × drawing word X width (128 bits) is required as shown in FIG. .

  In the method of Patent Document 8, a halftone threshold value corresponding to at least the scan line period corresponding to the start / end points of the scan line drawing obtained by the edge calculating means is read and binarized by a gradation value. The halftone threshold data is large data of 8 bits per pixel in order to draw an image after gradation processing at high speed by sequentially shifting and drawing repeatedly. However, it is necessary to read the halftone threshold value for each scan line and binarize it with the gradation value. Basically, the halftone threshold value sets the halftone pattern Y width in the Y direction. Repeatedly, the same data is read over and over, many memory accesses are required, the processing efficiency is poor, the processing becomes more complicated, the speed cannot be increased, and the gate scale is large. Become.

  In the method of Patent Document 9, when the information included in the intermediate data is analyzed to predict the degree of binarization speedup and the speedup can be expected, the scan line drawing obtained by the edge calculation means is drawn. The halftone threshold value corresponding to at least the scan line period corresponding to the start point / end point is read, binarized by the gradation value, sequentially shifted, and repeatedly drawn. Then, the image after gradation processing is drawn at high speed, the binarization is performed on the color information of the intermediate data of the drawing object which cannot be expected to increase in speed, and the scan line drawing start point / end point obtained by the edge calculation means is used. When the corresponding binary halftone pattern is sequentially shifted and repeatedly drawn, the image after gradation processing is drawn at high speed. Although the data is large data of 8 bits per pixel, it is necessary to read the halftone threshold value for each scan line and binarize the gradation value. In addition, since the halftone threshold basically repeats the halftone pattern Y width in the Y direction, the same data is read many times, requiring a lot of memory access, inefficient processing, and further processing. However, it has become complicated, the speed cannot be increased, and the system has a large gate scale.

  The present invention has been made in view of the above, and achieves high-speed processing by efficiently using a halftone pattern with respect to a drawing object having the same gradation value. The object is to reduce the capacity of the halftone pattern memory by sequentially obtaining the shift value for each drawing word for drawing.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 is an image processing apparatus for directly drawing an image after gradation processing in band units or page units, Halfton threshold storage means for storing at least half width of halftone pattern for Y width of halftone pattern, and halfton pattern storage for storing halftone pattern of drawing word X width for at least Y width of halftone pattern A halftone pattern generation unit that reads a halftone threshold value of the halftone threshold value storage unit, performs gradation processing, and transfers the halftone threshold value storage unit to the halftone pattern storage unit; Generating a halftone pattern address value of the halftone pattern storage means storing the halftone pattern to be stored A halftone pattern shift value generating means for generating a halftone pattern shift value of the halftone pattern from the X value of the horizontal line to be drawn, and the halfton pattern shift value in the halfton pattern. And a cyclic shift means for performing a cyclic shift of the minute.

  According to this invention, the halfton pattern storage means stores at least the halftone pattern of the drawing word X width for the Y width of the halfton pattern, and the halfton pattern address generating means corresponds to the halfton pattern address value. Ton pattern is sent to the cyclic shift means, and the cyclic shift means repeats the halftone pattern for the drawing object having the same gradation value by performing the cyclic shift processing for the halftone pattern shift value using the halftone pattern. It becomes possible to use.

  The invention according to claim 2 is characterized in that the halftone threshold value is set in the halftone pattern storage means by a threshold value table set command.

  According to the present invention, in claim 1, the halftone threshold value is set by the threshold value table set command in the halftone pattern storage means.

  According to a third aspect of the invention, the halftone pattern generation means reads the halftone threshold value reading means for reading the halftone threshold value stored in the halftone threshold value storage means designated by the drawing gradation value definition command. It is characterized by having.

  According to the present invention, in claim 1, the halftone threshold value reading means of the halftone pattern generation means reads the halftone threshold value stored in the halftone threshold value storage means specified by the drawing gradation value definition command. Thus, the halftone pattern of the drawing object having the same gradation value can be used.

  According to a fourth aspect of the present invention, the halftone pattern generation means performs halftone threshold parallel gradation processing means for performing gradation processing in parallel on the halfton threshold values read by the halfton threshold value reading means. It is characterized by having.

  According to the present invention, in claim 3, the halftone threshold parallel gradation processing means of the halftone pattern generation means performs gradation processing in parallel on the halfton threshold read by the halfton threshold reading means. Thus, high-speed processing can be performed.

  According to a fifth aspect of the present invention, the halftone pattern generating means converts the image data after gradation processing generated by the halftone threshold parallel gradation processing means into a fixed length BIT of halftone pattern X width. It has a halftone pattern fixed length data generating means for converting to data.

  According to the present invention, in claim 4, the halftone pattern fixed length data generation means of the halftone pattern generation means converts the image data after gradation processing generated by the halftone threshold parallel gradation processing means into halftone. By converting the data into the fixed length BIT data having the pattern X width, the used capacity of the halftone pattern memory can be reduced.

  According to a sixth aspect of the present invention, the halftone pattern generating means generates a halfton pattern by drawing the halfton pattern X-width fixed length BIT data generated by the halftone pattern fixed length data generating means. It is characterized by having halftone pattern repetitive processing means that is repeatedly arranged so that the number of bits in the width is the same.

  According to the present invention, in claim 5, the halftone pattern repetitive processing means of the halftone pattern generating means generates the data of the fixed length BIT of the halftone pattern X width generated by the halftone pattern fixed length data generating means. By repeatedly arranging the halftone patterns so as to have the number of BITs of the drawing word width, it is possible to reduce the used capacity of the halftone pattern memory.

  The invention according to claim 7 is characterized in that the halftone pattern storage means stores a halftone pattern having a drawing word width generated by the halftone pattern repetition processing means.

  According to the present invention, in the sixth aspect, the halftone pattern storage means stores the halftone pattern having the drawing word width generated by the halftone pattern repetition processing means, thereby enabling storage with a small memory capacity. Become.

  The invention according to claim 8 is characterized in that the cyclic shift means includes cyclic pattern generation means for generating a pattern corresponding to a halftone pattern shift value from the right side of the halftone pattern after the halftone pattern is shifted to the left. Features.

  According to the present invention, in claim 1, the cyclic pattern generation means generates a pattern corresponding to the halftone pattern shift value from the right side of the halftone pattern after the halftone pattern is shifted to the left, and the halftone pattern after the cyclic shift. Therefore, it is not necessary to have a halftone pattern of the least common multiple of the memory boundary width of the drawing unit and the number of basic bit patterns.

  According to a ninth aspect of the present invention, the halftone pattern address generation means divides the Y value of the horizontal line by the Y width of the halftone pattern, and performs a MOD operation for obtaining the remainder.

  According to the present invention, in claim 1, the halftone pattern address generation means divides the Y value of the horizontal line by the Y width of the halftone pattern, and performs the MOD operation for obtaining the remainder, thereby obtaining the obtained Y value. The halftone pattern address is transferred to the halftone pattern storage means.

  The halftone pattern shift value generating means divides the X value of the horizontal line by the X width of the halfton pattern, and performs a MOD operation for obtaining the remainder.

  According to the present invention, in claim 1, the halftone pattern shift value generation means divides the X value of the horizontal line by the X width of the halfton pattern, and performs the MOD operation for obtaining the remainder, thereby obtaining the calculated X value. Is transferred to the cyclic shift means as a halftone pattern value.

  According to an eleventh aspect of the present invention, there is provided an image processing method for directly drawing an image after gradation processing in band units or page units, wherein the halftone threshold value of the halftone pattern X width is set to at least a halftone pattern. A halftone threshold storage step for storing the Y width, a halfton pattern storage step for storing at least the Y width of the halfton pattern for the halftone pattern of the drawing word X width, and a halfton for the halfton threshold storage step Halfton pattern address value of the halftone pattern storage step that stores the corresponding halftone pattern from the Y value of the horizontal line to be drawn and the halftone pattern generation step that performs gradation processing by reading the threshold value and stores the threshold value From the halftone pattern address generation process for generating the horizontal line X value to be drawn, A halfton pattern shift value generating step for generating a halfton pattern shift value of the halftone pattern, and a cyclic shift step for performing a cyclic shift for the halfton pattern shift value in the halfton pattern, To do.

  According to the present invention, the halftone pattern of the drawing word X width is stored in the halfton pattern storage step, and at least the Y width of the halfton pattern is stored, and the halftone pattern corresponding to the halfton pattern address value in the halfton pattern address generation step is stored. The pattern is sent to the cyclic shift process, and the halftone pattern for the drawing object having the same gradation value is repeated by performing the cyclic shift process for the halftone pattern shift value using the halftone pattern in the cyclic shift manual process. It becomes possible to use.

  The invention according to claim 12 is characterized in that, in the halftone pattern storing step, a halftone threshold value is set by a threshold value table set command.

  According to the present invention, in the eleventh aspect, the halftone threshold value is set by the threshold value table set command in the halftone pattern storing step.

  The invention according to claim 13 is characterized in that the halftone pattern generation step includes a halftone threshold value reading step of reading a halftone threshold value specified by a drawing gradation value definition command.

  According to the invention, in the halftone threshold value reading step, the halftone pattern of the drawing object having the same gradation value is read by reading the halftone threshold value specified by the drawing gradation value definition command. It becomes usable.

  According to a fourteenth aspect of the present invention, in the halfton threshold value parallel gradation processing step, the halftone pattern generation step performs gradation processing in parallel with the halfton threshold value read in the halfton threshold value reading step. It is characterized by including.

  According to the present invention, in the thirteenth aspect, the halftone threshold parallel gradation processing step performs high-speed processing by performing gradation processing in parallel on the halftone threshold read in the halfton threshold reading step. It becomes possible to do.

  In the invention according to claim 15, in the halftone pattern generation step, the image data after the gradation processing generated in the halftone threshold parallel gradation processing step is converted into a fixed length BIT of a halfton pattern X width. It includes a halfton pattern fixed length data generation step for converting into data.

  According to the invention, in the halftone pattern fixed length data generation step according to the fourteenth aspect, the halftone pattern X-width fixed length is generated from the gradation processed image data generated in the halftone threshold parallel gradation processing step. By converting the data into BIT data, the used capacity of the halftone pattern memory can be reduced.

  Further, in the invention according to claim 16, in the halftone pattern generation step, the halfton pattern X width fixed length BIT data generated in the halftone pattern fixed length data generation step is used as a halfton pattern drawing word. It includes a halfton pattern repetitive processing step of repeatedly arranging so that the number of BITs in the width is reached.

  According to the present invention, in the halfton pattern repetitive processing step, the halfton pattern X width fixed length BIT data generated in the halftone pattern fixed length data generation step is used as the halfton pattern drawing word. By repeatedly arranging the BITs so as to have a width, the used capacity of the halftone pattern memory can be reduced.

  The invention according to claim 17 is characterized in that the halftone pattern storage step stores a halftone pattern having a drawing word width generated in the halfton pattern repetition processing step.

  According to the present invention, in the sixteenth aspect, the halftone pattern storage step stores the halftone pattern having the drawing word width generated in the halftone pattern repetitive processing step, thereby enabling storage with a small memory capacity. Become.

  The invention according to claim 18 includes a cyclic pattern generation step in which the cyclic shift step generates a pattern corresponding to a halfton pattern shift value from the right side of the halfton pattern after the halfton pattern is shifted leftward. Features.

  According to the present invention, in claim 11, in the cyclic pattern generation step, after the halftone pattern is shifted to the left, a pattern corresponding to the halftone pattern shift value is generated from the right side of the halftone pattern, and the halftone pattern after the cyclic shift is generated. Therefore, it is not necessary to have a halftone pattern of the least common multiple of the memory boundary width of the drawing unit and the number of basic bit patterns.

  According to a nineteenth aspect of the present invention, the halftone pattern address generation step divides the Y value of the horizontal line by the Y width of the halftone pattern, and performs a MOD operation for obtaining the remainder.

  According to the present invention, in claim 11, the halftone pattern address generation step divides the Y value of the horizontal line by the Y width of the halftone pattern, and performs a MOD operation to obtain the remainder, thereby obtaining the obtained Y value. It can be transferred as a halftone pattern address.

  According to a twentieth aspect of the invention, the halftone pattern shift value generation step divides the X value of the horizontal line by the X width of the halftone pattern, and performs a MOD operation for obtaining the remainder.

  According to the present invention, in the halfton pattern shift value generation step according to claim 11, the X value obtained by dividing the X value of the horizontal line by the X width of the halftone pattern and performing a MOD operation for obtaining the remainder. Can be transferred as a halftone pattern value.

  The invention according to claim 21 is characterized in that a program for causing a computer to execute the image processing method according to any one of claims 11 to 20 is recorded.

  According to this invention, the image processing method according to any one of claims 11 to 20 is recorded on a computer-readable recording medium by recording a program to be executed by a computer. One of the image processing methods described above can be executed on a computer.

  The image processing apparatus according to the present invention (Claim 1) stores the halftone pattern of the drawing word X width at least in the Y width of the halfton pattern in the halftone pattern storage means, The halftone pattern corresponding to the ton pattern address value is sent to the cyclic shift means, and the cyclic shift means performs the cyclic shift processing for the halftone pattern shift value using this halfton pattern, so that the same gradation value is obtained. Since the halftone pattern for the drawing object can be used efficiently and repeatedly, there is an effect that high-speed halfton drawing processing is realized.

  The image processing apparatus according to the present invention (Claim 2) has the effect that, in Claim 1, the halftone threshold value can be set by the threshold value table set command in the halftone pattern storage means.

  An image processing apparatus according to a third aspect of the present invention is the image processing apparatus according to the first aspect, wherein the halftone threshold value reading means of the halftone pattern generation means stores the halftone threshold value specified by the drawing gradation value definition command. By reading the halftone threshold value stored by the means, the halftone pattern of the drawing object having the same gradation value can be used.

  The image processing apparatus according to the present invention (Claim 4) is the image processing apparatus according to Claim 3, wherein the halftone threshold parallel gradation processing means of the halftone pattern generation means performs halftoning read by the halfton threshold reading means. By performing gradation processing on threshold values in parallel, there is an effect that processing can be performed at high speed.

  The image processing apparatus according to the present invention (Claim 5) is the image processing apparatus according to Claim 4, wherein the halftone pattern fixed length data generation means of the halftone pattern generation means is generated by the halftone threshold parallel gradation processing means. By converting the image data after gradation processing into data of a fixed length BIT having a halftone pattern X width, there is an effect that the used capacity of the halftone pattern memory can be reduced.

  An image processing apparatus according to a sixth aspect of the present invention is the image processing apparatus according to the fifth aspect, wherein the halftone pattern repetition processing means of the halftone pattern generation means is a halftone pattern generated by the halfton pattern fixed length data generation means. By repeatedly arranging the data of the X-width fixed length BIT so that the halftone pattern has the number of BITs of the drawing word width, the use capacity of the halftone pattern memory can be reduced.

  An image processing apparatus according to a seventh aspect of the present invention is the image processing apparatus according to the sixth aspect, wherein the halftone pattern storage means stores the halftone pattern of the drawing word width generated by the halftone pattern repetition processing means. As a result, the memory can be stored with a small memory capacity.

  An image processing apparatus according to an eighth aspect of the present invention is the image processing apparatus according to the first aspect, wherein the cyclic pattern generation means shifts the halfton pattern to the left after the halfton pattern is shifted to the left from the right side of the halfton pattern. By generating and obtaining a halftone pattern after cyclic shift, there is an effect that it is not necessary to have a halfton pattern of the least common multiple of the memory boundary width of the rendering unit and the number of basic bit patterns.

  The image processing apparatus according to the present invention (claim 9) is the MOD calculation according to claim 1, wherein the halftone pattern address generation means divides the Y value of the horizontal line by the Y width of the halfton pattern and obtains the remainder. As a result, the obtained Y value can be transferred to the halftone pattern storage means as a halftone pattern address.

  The image processing apparatus according to the present invention (Claim 10) is the MOD according to Claim 1, wherein the halftone pattern shift value generation means divides the X value of the horizontal line by the X width of the halftone pattern and obtains the remainder. By performing the operation, the obtained X value can be transferred to the cyclic shift means as a halftone pattern value.

  In the image processing method according to the present invention (claim 11), the halftone pattern of the drawing word X width is stored in the halfton pattern storage step, and at least the Y width of the halfton pattern is stored. By sending a halftone pattern corresponding to the halftone pattern address value to the cyclic shift process, and performing a cyclic shift process for the halfton pattern shift value using this halfton pattern in the cyclic shift manual process, the same gradation value is obtained. Since the halftone pattern for the drawing object can be used repeatedly, there is an effect that high-speed halfton drawing processing is realized.

  The image processing method according to the present invention (Claim 12) has the effect that, in Claim 11, the halftone threshold value can be set by a threshold value table set command in the halftone pattern storage step.

  The image processing method according to the present invention (Claim 13) is the image processing method according to Claim 11, wherein the halftone threshold value reading step reads the halftone threshold value specified by the drawing gradation value definition command. The halftone pattern of the tone value drawing object can be used.

  The image processing method according to the present invention (Claim 14) is the image processing method according to Claim 13, wherein the halftone threshold parallel gradation processing step is configured to parallelize the halftone threshold values read in the halftone threshold value reading step in parallel. By performing the tone adjustment process, there is an effect that the process can be performed at high speed.

  The image processing method according to the present invention (claim 15) is the image after gradation processing according to claim 14, wherein the halftone pattern fixed length data generation step is generated by the halftone threshold parallel gradation processing step. By converting the data into fixed-length BIT data having a halftone pattern X width, there is an effect that the used capacity of the halftone pattern memory can be reduced.

  The image processing method according to the present invention (invention 16) is the image processing method according to claim 15, wherein the halfton pattern repetition processing step is a fixed length BIT of the halftone pattern X width generated in the halfton pattern fixed length data generation step. By repeatedly arranging the halftone pattern so that the number of BITs of the drawing word width is equal to the number of bits, it is possible to reduce the use capacity of the halftone pattern memory.

  The image processing method according to the present invention (invention 17) is the image processing method according to claim 16, wherein the halftone pattern storage step stores the halftone pattern of the drawing word width generated in the halfton pattern repetition processing step. As a result, the memory can be stored with a small memory capacity.

  The image processing method according to the present invention (invention 18) is the image processing method according to claim 11, wherein in the cyclic pattern generation step, the halfton pattern is shifted to the left and then a pattern corresponding to the halfton pattern shift value is added from the right side of the halfton pattern. By generating and obtaining a halftone pattern after cyclic shift, there is an effect that it is not necessary to have a halfton pattern of the least common multiple of the memory boundary width of the rendering unit and the number of basic bit patterns.

  The image processing method according to the present invention (claim 19) is the MOD calculation according to claim 11, wherein the halftone pattern address generation step divides the Y value of the horizontal line by the Y width of the halfton pattern and obtains the remainder. As a result, it is possible to transfer the obtained Y value as a halftone pattern address.

  The image processing method according to the present invention (Claim 20) is the MOD according to Claim 11, wherein the halftone pattern shift value generation step divides the X value of the horizontal line by the X width of the halfton pattern and obtains the remainder. By performing the calculation, the obtained X value can be transferred as a halftone pattern value.

  A computer-readable recording medium according to the present invention (Claim 21) is a computer-readable recording medium that stores a program for causing a computer to execute the image processing method according to any one of Claims 11 to 20. By recording, the image processing method according to any one of claims 11 to 20 can be executed on a computer.

  Exemplary embodiments of an image processing apparatus, an image processing method, and a computer-readable recording medium storing a program for causing a computer to execute the image processing method will be described below in detail with reference to the accompanying drawings. To do.

(Embodiment)
According to the present invention, in an image drawing method after gradation processing, a drawing object having the same gradation value is fixed at the time of creating an intermediate language, and a command for defining a threshold value table and a drawing gradation value are defined in front of the object. By setting a command and defining the threshold table, a two-dimensional threshold table of halftone pattern X width × Y width is set in the halftone threshold storage device in the drawing apparatus, and the drawing floor A halfton process is performed on the threshold value table of the halftone threshold value storage device with a gradation value by a command for defining a tone value, and a two-dimensional halftone pattern of halftone pattern X width × Y width is stored in the halftone pattern memory. The same gradation is obtained by storing and performing drawing processing using the halftone pattern of the above halftone pattern memory by a drawing command. Since a halftone pattern can be efficiently used for a drawing object that is a value, it is not necessary to sequentially access the halftone threshold value storage device, and processing can be performed at high speed. In addition, since the horizontal shift value of the halftone pattern is sequentially obtained for each drawing word to be drawn, the halftone pattern does not have the least common multiple of the memory boundary width of the drawing unit and the width of the basic bit pattern. The capacity of the pattern memory can be reduced. Hereinafter, this embodiment will be described in detail.

  First, the configuration and operation of an image forming apparatus (printer) in which the image processing apparatus according to the present invention is mounted will be described. FIG. 1 is an explanatory diagram illustrating a configuration example of a mechanism unit of an image forming apparatus according to an embodiment of the present invention. Hereinafter, the image forming apparatus of FIG. 1 is described as a color printer. In this embodiment, a laser color printer is taken as an example, but another color printer such as an ink jet printer may be used.

  The color printer 100 shown in FIG. 1 arranges images of four colors (Y (yellow), M (magenta), C (cyan), K (black))) independently according to the laser beam writing and the electrophotographic process. This is a four-drum tandem engine type image forming apparatus that forms the image forming systems 1Y, 1M, 1C, and 1K, and sequentially superimposes and transfers these four color images on recording paper.

  Each of the image forming systems 1Y, 1M, 1C, and 1K includes a photoconductor as an image carrier, for example, small-diameter OPC (organic photoconductor) drums 2Y, 2M, 2C, and 2K, and the OPC drums 2Y, 2M, and 2C. The electrostatic latent images on the charging rollers 3Y, 3M, 3C, and 3K as charging means and the OPC drums 2Y, 2M, 2C, and 2K are developed with a developer from the upstream side of image formation so as to surround 2K. Developing devices 4Y, 4M, 4C, and 4K that generate toner images of Y, M, C, and K colors, cleaning devices 5Y, 5M, 5C, and 5K, and static eliminating devices 6Y, 6M, 6C, and 6K are arranged. .

Beside each developing device 4Y, 4M, 4C, and 4K, a toner bottle unit 7Y that supplies toner of a predetermined color to the developing devices 4Y, 4M, 4C, and 4K with Y toner, M toner, C toner, and K toner, respectively. , 7M, 7C, 7K are arranged. In addition, each of the image forming systems 1Y, 1M, 1C, and 1K is provided with laser-based optical writing devices 8Y, 8M, 8C, and 8K. The optical writing devices 8Y, 8M, 8C, and 8K are laser light sources. As a laser diode (LD) light source 9Y, 9M, 9C, 9K, Collimate Rains 10Y, 1
Optical components such as 0M, 10C, 10K, fθ lenses 11Y, 11M, 11C, 11K, polygon mirrors 12Y, 12M, 12C, 12K as deflection scanning means, folding mirrors 13Y, 13M, 13C, 13K, 14Y, 14M, 14C , 14K, etc.

  The image forming systems 1Y, 1M, 1C, and 1K are arranged vertically, and the transfer belt unit 15 is arranged on the right side so as to be in contact with the OPC drums 2Y, 2M, 2C, and 2K. The transfer belt unit 15 is rotationally driven by a drive source (not shown) with the transfer belt 16 stretched around rollers 17 to 20. A paper feed tray 21 storing recording paper as a transfer material is disposed on the lower side of the apparatus, and a fixing device 22 having a heat fixing roller and a pressure roller, a paper discharge roller 23, and a paper discharge tray 24 are arranged at the top of the apparatus. It is installed.

  At the time of image formation, in each image forming system 1Y, 1M, 1C, 1K, the OPC drums 2Y, 2M, 2C, 2K are rotationally driven by a driving source (not shown), and are charged by charging rollers 3Y, 3M, 3C, 3K. The OPC drums 2Y, 2M, 2C, and 2K are uniformly charged, and the optical writing devices 8Y, 8M, 8C, and 8K modulate the laser diode based on the image data of each color, and deflect and scan the laser light to scan the OPC drum 2Y. By performing optical writing on 2M, 2C, and 2K, electrostatic latent images are formed on the OPC drums 2Y, 2M, 2C, and 2K.

  The electrostatic latent images on the OPC drums 2Y, 2M, 2C, and 2K are developed by developing devices 4Y, 4M, 4C, and 4K, respectively, to become toner images of colors Y, M, C, and K, while the paper feed tray 21 From the sheet feeding roller 25, the recording paper is fed in the horizontal direction and conveyed vertically by the conveying system in the image forming systems 1Y, 1M, 1C, and 1K. This recording paper is electrostatically attracted and held on the transfer belt 16 and conveyed by the transfer belt 16, and a transfer bias is applied by a transfer bias applying means (not shown) so as to be on the OPC drums 2Y, 2M, 2C and 2K. A full color image is formed on the recording paper by sequentially superimposing and transferring the toner images of each color Y, M, C, and K onto the recording paper. The recording paper on which the full-color image is formed is fixed by the fixing device 22 to the full-color toner image by the action of heat and pressure, and is discharged to the discharge tray 24 by the discharge roller 23. It is to be noted that an electrical / control device 26 for driving and controlling each functional element described above and executing various image processing is mounted.

  Next, a detailed configuration and operation of the image processing apparatus in the color printer configured as described above will be described. FIG. 2 is a block diagram showing the configuration of the electrical / control device 26 of the color printer in FIG. This electrical / control device 26 is connected to a CPU 101 and a memory controller 103 that control the entire color printer (printer engine), and controls a CPU I / F 102 and a main memory 104 that perform interface control between the CPU 101 and the memory controller 103. The CPU 101 local bus, decoding device, encoding device, drawing device, communication controller, etc., and the memory controller 103 that controls the transfer between the main memory 104, images from the CPU 101, CPU 101 programs, band data, and page compression Main memory 104 for storing various data such as data, drawing device 105 for receiving a drawing command from the CPU 101 and drawing a band of the main memory 104, encoding the band of the main memory 104, and main memo The encoding device 106 that sends the code data to the code page memory area 104, the decoding device 107 that receives the code encoded by the encoding device 106, decodes it, and transfers it to the engine controller, and the image data decoded by the decoding device 107 Receives and transfers the engine controller 109, printer engine 110, and network engine 50 that receive the PDL from the PC via the network 50, the communication controller 116 that transfers the PDL to the main memory 104, the ROM, the panel controller, and the CPU 101, the main memory 104, and the like. A local bus I / F 111, a ROM 112 that stores font information such as characters and a program of the CPU 101, a panel controller 114 that controls a panel 115 for operation, The operation from Za to produce a panel 115 to notify the printer, PDL (Page Description Language), and a PC (personal computer) 200 to be transferred to the color printer via a network 50.

  The network 50 is classified into a WAN (Wide Area Network) connected to the outside through a public line or a dedicated line, and a LAN (Local Area Network) that constructs a network on the same site. Any method may be used. In addition, when the Internet function is provided, TCP / IP (Transmission Control Protocol / Internet Protocol) may be used. Furthermore, it is of course possible to use a wireless LAN connection.

  FIG. 3 is a block diagram showing a flow of image processing according to the embodiment of the present invention. In this figure, the main memory 104 stores the PDL data from the communication controller 116 in the PDL memory area 104a. The CPU 101 analyzes the PDL in the main memory 104 to generate an intermediate language and transfers it to the main memory 104. The main memory 104 stores the intermediate language generated by the CPU 101 in the intermediate language memory area 104b. The drawing device 105 receives the intermediate language stored in the intermediate language memory area 104 b of the main memory 104 and draws a band in the band memory area 104 c of the main memory 104. The main memory 104 stores band data drawn by the drawing device 105. The encoding device 106 reads and encodes the band data in the band memory area 104 c of the main memory 104, and sends the code to the page code memory area 104 d of the main memory 104. The main memory 104 receives the code from the encoding device 106 and stores it. The decoding device 107 reads and decodes the code for one page including the code for each band stored in the main memory 104, and transfers the code to the engine controller. Print output is performed by the printer engine via the engine controller.

  FIG. 4 is a block diagram showing the concept of image processing according to the first embodiment of the present invention. In this figure, the PC 200 generates PDL (page description language) and transfers it to the printer via the network 50. The printer communication controller 116 receives the PDL from the PC 200 and stores it in the PDL memory area 104 a of the main memory 104. The main memory 104 stores PDL, intermediate language, band data, page codes, programs, various work data, and the like. The CPU 101 analyzes the PDL from the PC 200 and generates an intermediate language. The drawing device 105 reads the intermediate language in the main memory 104 and draws the band in the band memory area 104 c of the main memory 104. At this time, the CPU 101 is informed of the state of processing by a status register.

  The encoding device 106 reads the band into the band memory area 104 c of the main memory 104, decodes the code in the code page memory area 104 d of the main memory 104 in synchronization with the printer engine 109, and transfers the code to the engine controller 109. . The engine controller 109 transfers the image data after image processing to the printer engine 110. The printer engine 110 forms an image on recording paper according to the image data.

  FIG. 5 is an explanatory diagram showing a format example of the main memory 104 in FIG. A PDL (page description language) from the PC 200 is stored in the PDL memory area 104a. The intermediate language generated by the CPU 101 is stored in the intermediate language memory area 104b. The band memory area 104c stores band data. The page code memory area 104d is an area for storing a plurality of pages of encoded data for one encoded band. The program area 104p stores a CPU program. The work area 104w stores an intermediate result of processing by the CPU 101 or the like.

  FIG. 6 is a block diagram showing a flow of image processing in the image processing apparatus of the present invention, and the flow of processing is indicated by a signed arrow. The CPU 101 transfers the intermediate language executed by the drawing device 105 to the intermediate language memory area 104 b of the main memory 104. The drawing device 105 reads the intermediate language from the intermediate language memory area 104 b of the main memory 104 and performs drawing processing on the band memory area 104 c of the main memory 104. The encoding device 106 reads and encodes a band image from the band memory area 104 c of the main memory 104, and transfers the code to the page code memory area 104 d of the main memory 104. The decoding device 107 reads a code from the page memory code area 104d of the main memory 104, decodes it, transfers it to the engine controller 109, and performs a printing process.

  FIG. 7 shows a format of the band memory and a drawing example. The drawing word width is the width of a word for the drawing device 105 to access the band memory. Here, as an example of drawing, an example is shown in which a horizontal line from the horizontal line X start point to the horizontal line X end point is drawn with respect to the horizontal line Y.

  FIG. 8 shows an example of an intermediate language processed by the drawing apparatus 105. FIG. 9 shows a drawing example of a band generated in the intermediate language of FIG. FIG. 10 shows a format example of each drawing command in the intermediate language shown in FIG.

  The band initialization command 201 (C, M, Y, K) defines the start address of the band and the height and width of the band. When the drawing command analysis device 212 (see FIG. 11) receives this command, it stores the head address of the band and the height and width of the band in the parameter storage device 215 (see FIG. 11). A drawing tone definition command 203 (C, M, Y, K) defines a halftone threshold address and a drawing tone value. Upon receiving this command, the drawing command analysis device 212 (see FIG. 11) stores the drawing gradation value in the parameter storage device 215 (see FIG. 11), and the halftone pattern generation device 231 (see FIG. 12) performs halftoning. A halftone threshold value is read from the halftone threshold value storage device 216 (see FIG. 11) designated by the threshold address address, binarized with a drawing gradation value, and transferred to the halftone pattern memory 227 (see FIG. 12).

  The threshold table set command 202 (CM, Y, K) defines the X width and Y width of the halftone pattern and the threshold table address for each pixel. Upon receiving this command, the drawing command analyzer 212 (see FIG. 11) stores the X width and Y width of the halftone pattern in the parameter storage device 215, and the work area 104w of the main memory 104 indicated by the address of the threshold table. Are transferred to the halftone threshold value storage device 216 (see FIG. 11).

  The rectangle drawing command 204 (C, M, Y, K) draws a rectangle from the upper left coordinate to the lower right coordinate of the designated rectangle. Upon receiving this command, the drawing command analyzer 212 (see FIG. 11) transfers the upper left coordinates of the rectangle, the lower right coordinates and the rectangle command name to the horizontal line converter 213 (see FIG. 11), and performs the drawing process. . A triangle drawing 205 (C, M, Y, K) draws a triangle from each end point coordinate of a designated triangle. Upon receiving this command, the drawing command analysis device 212 (see FIG. 11) transfers the end point coordinates of the triangle and the triangle command name to the horizontal line conversion device 213, and performs drawing processing. The band end command 208 (C, M, Y, K) means the end of drawing of the defined band. When the drawing command analysis device 212 (see FIG. 11) receives this command, it ends the processing of the band.

  FIG. 11 is a block diagram illustrating a detailed configuration of the drawing apparatus 105. The drawing device 105 includes a memory controller I / F 211, a drawing command analysis device 212, a horizontal line conversion device 213, a horizontal line drawing device 214, a parameter storage device 215, a halfton threshold storage device 216, and a controller 217.

  The memory controller I / F 211 is an interface with the memory controller 103. The drawing command analysis device 212 reads the drawing command from the memory controller I / F 211 and analyzes the drawing command. If it is a parameter setting command, it transfers the parameter value to the parameter storage device 215. A drawing command is transferred to the horizontal line converter 213. The horizontal line conversion device 213 receives a drawing command from the drawing command analysis device 212, converts it into a horizontal line, and transfers it to the horizontal line drawing device 214. The horizontal line drawing device 214 performs drawing processing on the band memory of the main memory 104 via the memory controller I / F 211 based on the horizontal line data from the horizontal line conversion device 213. The parameter storage device 215 stores the parameters transferred from the drawing command analysis device 212 and transfers them to the horizontal line conversion device 213 and the horizontal line drawing device 214. The halftone threshold value storage device 216 stores a plurality of halftone threshold values transferred from the drawing command analysis device 212 and transfers them to the horizontal line conversion device 213. FIG. 14 shows a format example of the halftone threshold value storage device 216. The controller 217 controls the entire drawing apparatus 105.

  FIG. 12 is a block diagram showing a detailed configuration of the horizontal line drawing device 214 in FIG. The horizontal line drawing device 214 includes a halftone pattern address generation device 221, an X start point word value generation device 222, an X end point word generation device 223, a drawing word X value generation device 224, a halfton pattern shift value generation device 225, a drawing mask. A generation device 226, a Hearton pattern memory 227, a cyclic shift device 228, an AND device 229, a drawing address generation device 230, a halftone pattern generation device 231, a halfton threshold address generation device 232, and a controller 233 are provided.

  The halftone pattern address generation device 221 performs horizontal line Y value−MOD−halftone pattern Y width from the horizontal line Y value and the halftone pattern Y width, and obtains the Y value of the halftone pattern that is the remainder of division. Transfer to the halftone pattern memory 227 as the halftone pattern address. The X start point word value generation device 222 obtains a drawing word X start point value for each drawing word from the horizontal line X start point value, and transfers it to the drawing word X value generation device 224. The X end point word value generation device 223 obtains a drawing word X end point value for each drawing word from the horizontal line X end point value, and transfers it to the drawing word X value generation device 224. The drawing word X value generation device 224 generates the drawing word X value of the end point value from the X start point of the X start point word value generation device 222 and the X start point value of the drawing word unit from the X end point word value generation device 223, and is a halftone. Transfer to the pattern shift value generator 225.

  The halftone pattern shift value generation device 225 performs the drawing word X value−MOD−halfton pattern X width from the drawing word X value and the halfton pattern X width, and obtains the X value of the halfton pattern that is the remainder of the division. The halftone pattern shift value is transferred to the cyclic shift device 228. The drawing mask generation device 226 generates a drawing mask from the X start point to the X end point for each drawing word from the horizontal line X start point value and the horizontal line X end point value, and transfers the drawing mask to the AND device 229.

  As shown in FIG. 16, the halftone pattern memory 227 is a storage device that stores a horizontal line of a halftone pattern and a horizontal line of a halftone pattern Y width, and the halftone pattern from the halfton pattern address generation device 221. The accessed halftone pattern value is transferred to the cyclic shift device 228 according to the address.

  The cyclic shift device 228 receives a halftone pattern value from the halftone pattern memory, a halftone pattern shift value from the halftone pattern shift value generation device 225, and a halftone pattern value from the parameter storage device 215, and a halfton pattern value. Are cyclically shifted, and the halftone pattern value after the cyclic shift is transferred to the AND device 229. The AND device 229 performs an AND operation on the halftone pattern value after the cyclic shift from the cyclic shift device 228 and the drawing mask from the drawing mask generation device 226, generates a drawing pattern value, and sends the drawing pattern to the memory controller I / F 211. Forward.

  The drawing address generation device 230 generates a drawing address that is an address for drawing in the band memory of the main memory 104 from the horizontal line Y value and the horizontal line X start point value, and transfers the drawing address to the memory controller I / F 211. The halftone pattern generation device 231 is activated after receiving the drawing gradation value definition command, reads the halftone threshold value from the designated halftone threshold address of the halftone threshold value storage device 216, and determines the gradation value as the drawing gradation value. Tone processing is performed and stored in the halftone pattern memory 227. The halftone threshold address generation device 232 is activated after receiving the drawing gradation value definition command, and sequentially generates addresses from the designated halftone threshold address of the halftone threshold value storage device 216. The controller 233 controls the entire horizontal line drawing device 214.

  FIG. 13 shows an example of the halftone threshold value stored in the halftone threshold value storage device 216 of FIG. In this way, a plurality of halftone threshold values (in this example, indicated by A, B, and C) are stored in units of words.

  FIG. 14 is a block diagram showing a configuration of the halftone pattern generation device 231 in FIG. The halftone pattern generation device 231 includes a halftone threshold address generation device 281, a parallel gradation processing device 282, a fixed length data generation device 283, an iterative processing device 284, and a halfton pattern value address generation device 285 as shown in the figure. The controller 286 is provided.

  The halftone threshold address generation device 281 generates an address for reading the designated halftone threshold value from the halftone threshold value storage device 216. The parallel gradation processing device 282 performs gradation processing by comparing a plurality of halftone threshold values read from the halftone threshold value storage device 216 with drawing gradation values in parallel. The fixed length data generation device 283 converts the plurality of gradation processed data generated by the parallel gradation processing device 282 into data of a fixed length BIT having a halftone pattern X width. The iterative processing device 284 repeatedly arranges the halftone pattern having the X width of the halftone pattern generated by the fixed length data generating device 283 so as to have the number of BITs of the drawing word width, and writes it to the halftone pattern memory 227. The halftone pattern address generation device 285 generates an address for writing the halftone pattern having the drawing word width generated by the repetition processing device 284 to the halftone pattern memory 290. The controller 286 controls the halftone pattern generation device 231.

  FIG. 15 is a block diagram showing the configuration of the parallel gradation processing device 282 in FIG. The parallel gradation processing device 282 includes comparison devices 301 to 304 as shown in the figure. The comparison devices 301 to 304 perform gradation processing by comparing a plurality of halftone threshold values read from the halftone threshold value storage device 216 with drawing gradation values in parallel.

  FIG. 16 is a block diagram illustrating a configuration of the fixed-length data generation device 283 in FIG. The fixed length data generation device 283 includes a shifter 311, an OR device 312, registers 313, 314, 316, and an adder 315 as shown in the figure.

  The shifter 311 sequentially shifts the plurality of gradation processed data received from the parallel gradation processing device 282 to the position of the fixed length BUT having the halftone pattern X width. The OR device 312 ORs the plurality of post-gradation data shifted by the shifter 311 into the half-length pattern X-width fixed length BIT data stored in the register 314, and inserts the data. The register 313 stores a fixed length BIT having a halftone pattern X width generated by the OR device. The register 314 stores the halfway pattern X width fixed length BIT generated by the OR device 312.

  FIG. 17 is an example of a halftone threshold value table stored in the halftone threshold value storage device 216 in FIG. 11, and is such an m × n halftone threshold value. FIG. 18 shows the format of the halftone threshold value storage device 216 in FIG. 11. Since one word output simultaneously from the halfton threshold value storage device 216 is 32 bits, it is stored in units of 32 bits.

  FIG. 19 is a flowchart showing the processing operation of the halftone pattern generation device 231 in FIG. 12 and is executed by the controller 233. In order to convert the threshold value of the halftone threshold value storage device 216 shown in FIG. 18 into the format of the halftone pattern memory 227 shown in FIG. Gradation processing is performed using the values (step S1), and the data for the halfton pattern X width subjected to the gradation processing is repeatedly written so as to satisfy the drawing word width as shown in FIG. 16 (step S2). , S3).

  FIG. 20 shows the format of the halftone pattern stored in the halftone pattern memory 227. In this way, the half-ton pattern in the X direction is repeatedly filled as long as the drawing word X width is satisfied. Then, the value of the halftone pattern repeatedly embedded is stored as the value of the halftone pattern. In this example, since the drawing word X width is 128 bits and the halftone pattern X width is 20 bits, the halftone pattern value is too much 8 bits.

  FIG. 21 is a flowchart showing the processing operation of the horizontal line drawing device 214 and is executed by the controller 233. First, the halftone pattern address generator 221 shown in FIG. 12 performs an operation as shown in this figure from the horizontal line Y value and the halftone pattern Y width to obtain a halftone pattern address that is a halftone pattern Y value ( Step S11). Subsequently, since the drawing word X width is an example of 128 bits by the X starting point word value generation device 222 of FIG. 12, the horizontal line X starting point value is ANDed with the FF80 value of the 16-bit pattern to obtain a value in units of 128 bits. A drawing word X starting point value is obtained (step S12). Subsequently, the X end point word value generation device 223 of FIG. 12 performs an AND process on the horizontal line X end point value with the FF80 value of the 16-bit pattern because the drawing word X width is 128 bits, and is a value in units of 128 bits. A drawing word X end point value is obtained (step S13). Subsequently, the drawing word X value is set to the drawing word X starting point value of the X starting point by the processing of the drawing word X value generating device 224 of FIG. 12 (step S14). Further, in order to access the halftone pattern memory 227 of FIG. 12, the halftone pattern value obtained in step S11 is accessed to obtain the halftone pattern value of the halftone pattern Y value (step S15).

  Subsequently, the processing of steps S16 to S20 is executed by the drawing mask generation device 226 of FIG. That is, it is determined whether or not the drawing word X value generated by the drawing word X value generation device 224 of FIG. 12 is the starting point (step S16). If it is the starting point, a drawing mask is generated from the horizontal line X starting point value (step S16). S17). If it is not the start point in step S16, it is further determined whether or not the drawing word X value generated by the drawing word X value generation device 224 of FIG. 12 is the end point (step S18). A drawing mask is generated (step S19). Subsequently, when neither the start point nor the end point is set, the drawing mask is set to All “1” and a value without a mask is set (step S20).

  Subsequently, the halftone pattern shift value generation device 225 in FIG. 12 divides the value of the drawing word X value by the halfton pattern X width to obtain the halfton pattern X value of the drawing word X value, and obtains that much. The halftone pattern X value is a halftone pattern shift value for shifting the halftone pattern value accessed from the halftone pattern memory 227 (step S21). Subsequently, the cyclic shift device 228 in FIG. 12 cyclically shifts the halftone pattern value to generate a halftone pattern value after cyclic shift (step S22).

  Subsequently, the AND device 229 in FIG. 12 performs an AND operation on the halftone pattern value after the cyclic shift and the drawing mask value to generate a drawing pattern value (step S23), and the drawing word X value generation device 224 in FIG. In this process, the drawing word width is added to the drawing word X value to obtain the next drawing word X value (step S24). Subsequently, the drawing word X value generation device 224 of FIG. 12 determines whether or not the drawing word X value is equal to or greater than the drawing word X end point (step S25). If not, the processing from step S16 is repeatedly executed. To draw a horizontal line.

  FIG. 22 is a block diagram showing a detailed configuration of the cyclic shift device 228 in FIG. FIG. 23 shows an example of cyclic shift processing. The cyclic shift device 228 includes subtracters 251 and 252, a left shift device 253, a right shift device 254, and an OR device 255.

  FIG. 23 shows an example in which the halfton pattern X width = 20, the halfton pattern shift value = 10, the drawing word width = 128, and the halfton pattern too much value = 8. The ton pattern is repeated 6 times and has a lot of 8 bits. A value obtained by shifting the halftone pattern value by 10 bits to the left by the halfton pattern shift value “10” by the left shift device 253 of FIG. 18 is the halfton pattern value after the left shift, and the rightmost 10 bits after the left shift is “0”. "Is added.

  Further, the subtracters 251 and 252 in FIG. 22 subtract the left shift value and the halftone value from the drawing word width to obtain the end value of the repetitive pattern after the left shift, and obtain the right shift value. A value obtained by shifting the halfton pattern value to the right by “110”, which is the right shift value by the right shift device 254 in FIG. 22, is the halfton pattern value after the right shift, and 110 bits at the left end after the right shift are set to “0”. It is added. Further, the OR device 255 of FIG. 18 performs an OR operation on the halfton pattern value after the left shift and the halfton pattern value after the right shift, and after the right shift to the “0” value at the right end of the halfton pattern value after the left shift. The halftone pattern value after the cyclic shift can be obtained by performing an OR operation on the cyclic halftone pattern at the right end of.

  FIG. 24 is a block diagram showing a detailed configuration of the encoding device 106 in FIG. The encoding device 106 includes a memory controller I / F 261, a BUF (buffer) 262, a JBIG encoding device 263, a BUF (buffer) 264, a memory address generation device 265, and a controller 266.

  The memory controller I / F 261 is an interface with the memory controller 103 of FIG. The buffer 262 stores the image data for one hour. The JBIG encoding device 263 encodes the image data by the encoding method of the JBIG standard and transfers the image data to the buffer 264. The buffer 264 stores code data at 1 o'clock. The memory address generation device 265 generates an address for reading image data from the band memory area 104c of the main memory 104 in FIG. 2 and writes code data into the page code memory area 104d of the main memory 104 in FIG. Generate an address for The controller 266 controls the encoding device 106.

  FIG. 25 is a block diagram showing a detailed configuration of the decoding device 107 in FIG. The decoding device 107 includes a memory controller I / F 271, a BUF (buffer) 272, a JBIG decoding device 273, a BUF (buffer) 274, a memory address generation device 275, and a controller 276.

  The memory controller I / F 271 is an interface with the memory controller 103 of FIG. The buffer 272 stores code data at 1 o'clock. The JBIG decoding device 273 decodes the code data by the decoding method of the JBIG standard and transfers it to the buffer 274. The buffer 274 stores image data for 1 hour. The memory address generation device 275 generates an address for reading code data from the page code memory area 104d of the main memory 104 of FIG. The controller 276 controls the decoding device 107.

  By the way, the image processing method (operation) in the embodiment described so far can be programmed, recorded on a computer-readable recording medium, and executed on the computer. Further, a part of the image processing method can be provided on a network and realized through a communication line.

  That is, the image processing method described in this embodiment is realized by executing a program prepared in advance on a computer (CPU 30) such as a personal computer or a workstation as shown in FIG. This program is operated by a computer such as a memory 31, a hard disk 34, a flexible disk 37, a CD-ROM (Compact-Disc Read Only Memory) 36, an MO (Magneto Optical), a DVD (Digital Versatile Disc), etc. The program is recorded on a readable recording medium, read from the recording medium by a computer (CPU 30), and displayed on the display device 33 as necessary. In addition, data of this image processing method can be transmitted and received from the communication device 32 to an external device as necessary.

  Further, as shown in FIG. 28, this program can be distributed to devices 41 to 43 such as a personal computer via the recording medium via a network such as the Internet 30.

  That is, this program can be provided in a state of being installed in advance on a hard disk as a recording medium built in the computer, for example. The program can be temporarily or permanently stored in a recording medium, and can be provided as packaged software by being incorporated in a computer as a unit or being used as a removable recording medium.

  As the recording medium, for example, a flexible disk, a CD-ROM, an MO disk, a DVD, a magnetic disk, a semiconductor memory, and the like can be used.

  The program can be transferred from a download site to a computer wired or wirelessly via a network such as a LAN (Local Area Network) or the Internet, and downloaded to a storage device such as a built-in hard disk in the computer. .

  As described above, the image processing apparatus and the image processing method according to the present invention, and the computer-readable recording medium on which the program for causing the computer to execute the image processing method is recorded is an image output such as a color digital copying machine or a color laser printer. In particular, the present invention is suitable for various image output systems that realize high-speed halftone drawing processing in image processing using the post-gradation image drawing method.

FIG. 3 is an explanatory diagram illustrating a configuration example of a mechanism unit of the image forming apparatus according to the embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of an electrical / control device of the color printer in FIG. 1. It is a block diagram which shows the flow of the image processing concerning embodiment of this invention. It is a block diagram which shows the concept of the image processing concerning embodiment of this invention. It is explanatory drawing which shows the example of a format of the main memory in FIG. It is a block diagram which shows the flow of the image processing concerning embodiment of this invention. It is explanatory drawing which shows the format and drawing example of a band memory concerning embodiment of this invention. It is explanatory drawing which shows the example of the intermediate language which the drawing apparatus concerning embodiment of this invention processes. It is explanatory drawing which shows the example of a drawing of the band produced | generated by the intermediate language of FIG. FIG. 9 is an explanatory diagram illustrating a format example of each drawing command in the intermediate language of FIG. 8. It is a block diagram which shows the detailed structure of the drawing apparatus in FIG. It is a block diagram which shows the detailed structure of the horizontal line drawing apparatus in FIG. It is explanatory drawing which shows the example of the halftone threshold value table memorize | stored in the halftone threshold value memory | storage device in FIG. It is a block diagram which shows the structure of the halftone pattern production | generation apparatus in FIG. It is a block diagram which shows the structure of the parallel gradation processing apparatus in FIG. It is a block diagram which shows the structure of the fixed length data generation apparatus in FIG. It is explanatory drawing which shows the example of a halftone threshold value table concerning embodiment of this invention. It is explanatory drawing which shows the example of a format of the halftone threshold value memory | storage device concerning embodiment of this invention. It is a flowchart which shows the processing operation of the halftone pattern production | generation apparatus concerning embodiment of this invention. It is explanatory drawing which shows the example of the halftone pattern format concerning embodiment of this invention. It is a flowchart which shows the processing operation of the horizontal line drawing apparatus concerning embodiment of this invention. It is a block diagram which shows the detailed structure of the cyclic shift apparatus concerning embodiment of this invention. It is explanatory drawing which shows the process example in the cyclic shift apparatus concerning embodiment of this invention. It is a block diagram which shows the detailed structure of the encoding apparatus in FIG. It is a block diagram which shows the detailed structure of the decoding apparatus in FIG. It is a block diagram which shows the example which makes a computer perform the image processing method concerning embodiment of this invention. It is a block diagram which shows the example which downloads and performs the image processing method concerning embodiment of this invention from a network. It is a block diagram which shows the structure of a multi-value image drawing system, and the flow of a process. It is a block diagram which shows the structure of the image drawing system after a gradation process, and the flow of a process. It is explanatory drawing which shows the example of the half-ton pattern of the least common multiple in the past. It is explanatory drawing which shows the example of a conventional halftone pattern format.

Explanation of symbols

101 CPU
DESCRIPTION OF SYMBOLS 103 Memory controller 104 Main memory 104a PDL memory area 104b Intermediate language memory area 104c Band memory area 104d Page code memory area 105 Drawing apparatus 106 Encoding apparatus 107 Decoding apparatus 109 Engine controller 110 Printer engine 212 Drawing command analysis apparatus 213 Horizontal line conversion apparatus 214 Horizontal line drawing device 215 Parameter storage device 216 Halfton threshold storage device 221 Halfton pattern address generation device 222 X start point word value generation device 223 X end point word value generation device 224 Drawing word X value generation device 225 Halfton pattern shift value Generation device 226 Drawing mask generation device 227 Halfton pattern memory 228 Cyclic shift device 229 OR device 230 Drawing add Scan generator 231 halftone pattern generator 232 halftone threshold address generator 281 halftone threshold address generator 282 parallel gradation processing unit 283 fixed-length data generating device 284 repeatedly processing apparatus 285 halftone pattern value address generator

Claims (21)

An image processing apparatus that directly draws an image after gradation processing in band units or page units,
A halftone threshold value storage means for storing a halftone threshold value of the halftone pattern X width at least for the Y width of the halftone pattern;
A halftone pattern storage means for storing at least the Y width of the halftone pattern of the halftone pattern of the drawing word X width;
Halftone pattern generation means for reading the halftone threshold value of the halftone threshold value storage means, performing gradation processing, and transferring the halftone pattern value to the halftone pattern storage means;
Halftone pattern address generating means for generating a halftone pattern address value of the halftone pattern storage means storing the corresponding halftone pattern from the Y value of the horizontal line to be drawn;
A halftone pattern shift value generating means for generating a halftone pattern shift value of the halftone pattern from the X value of the horizontal line to be drawn;
A cyclic shift means for performing a cyclic shift for the halftone pattern shift value in the halftone pattern;
An image processing apparatus comprising:   The image processing apparatus according to claim 1, wherein the halftone pattern storage unit sets a halftone threshold value by a threshold value table set command.   2. The halftone pattern generation means comprises halftone threshold value reading means for reading a halftone threshold value stored in the halftone threshold value storage means designated by a drawing gradation value definition command. An image processing apparatus according to 1.   The halftone pattern generation means includes halftone threshold parallel gradation processing means for performing gradation processing on the halftone threshold read by the halfton threshold reading means in parallel. An image processing apparatus according to 1.   The halftone pattern generation means converts halftone pattern fixed-length data that converts the image data after gradation processing generated by the halftone threshold parallel gradation processing means into data of a fixed length BIT having a halfton pattern X width. The image processing apparatus according to claim 4, further comprising a generation unit.   The halftone pattern generation means repeatedly arranges the halfton pattern X width fixed length BIT data generated by the halftone pattern fixed length data generation means so that the halfton pattern has the number of BITs of the drawing word width. 6. The image processing apparatus according to claim 5, further comprising a halftone pattern repetitive processing unit.   The image processing apparatus according to claim 6, wherein the halftone pattern storage unit stores a halftone pattern having a drawing word width generated by the halftone pattern repetition processing unit.   The image according to claim 1, wherein the cyclic shift unit includes a cyclic pattern generation unit that generates a pattern corresponding to a halfton pattern shift value from the right side of the halfton pattern after the halfton pattern is shifted to the left. Processing equipment.   The image processing apparatus according to claim 1, wherein the halftone pattern address generation unit divides the Y value of the horizontal line by the Y width of the halftone pattern and performs a MOD operation for obtaining a remainder.   The image processing apparatus according to claim 1, wherein the halftone pattern shift value generation unit divides the X value of the horizontal line by the X width of the halftone pattern, and performs a MOD operation for obtaining a remainder. An image processing method for drawing an image after gradation processing directly in band units or page units,
A halftone threshold value storing step for storing a halftone threshold value of the halftone pattern X width at least for the Y width of the halftone pattern;
A halftone pattern storing step of storing at least the Y width of the halftone pattern from the halftone pattern of the drawing word X width;
A halftone pattern generating step of reading the halftone threshold value of the halftone threshold value storing step, performing gradation processing, and storing;
A halftone pattern address generation step of generating a halftone pattern address value of the halftone pattern storage step storing the corresponding halftone pattern from the Y value of the horizontal line to be drawn;
A halftone pattern shift value generation step of generating a halftone pattern shift value of the halftone pattern from the X value of the horizontal line to be drawn;
A cyclic shift step of performing a cyclic shift for the halftone pattern shift value in the halftone pattern;
An image processing method comprising:   12. The image processing method according to claim 11, wherein in the halftone pattern storing step, a halftone threshold is set by a threshold table set command.   12. The image processing method according to claim 11, wherein the halftone pattern generation step includes a halftone threshold value reading step of reading a halftone threshold value specified by a drawing gradation value definition command.   The halftone pattern generation step includes a halftone threshold parallel gradation processing step of performing gradation processing in parallel with the halfton threshold read in the halfton threshold reading step. An image processing method described in 1.   In the halftone pattern generation step, halfton pattern fixed length data for converting the image data after the gradation processing generated in the halftone threshold parallel gradation processing step into data of a fixed length BIT having a halfton pattern X width The image processing method according to claim 14, further comprising a generation step.   In the halftone pattern generation step, the halfton pattern X width fixed length BIT data generated in the halfton pattern fixed length data generation step is repeatedly arranged so that the halfton pattern has the number of BITs of the drawing word width. The image processing method according to claim 15, further comprising a halfton pattern repetition processing step.   The image processing method according to claim 16, wherein the halftone pattern storage step stores a halftone pattern having a drawing word width generated in the halfton pattern repetition processing step.   The image according to claim 11, wherein the cyclic shift step includes a cyclic pattern generation step of generating a pattern corresponding to a halfton pattern shift value from the right side of the halfton pattern after the halfton pattern is shifted to the left. Processing method.   12. The image processing method according to claim 11, wherein in the halftone pattern address generation step, a MOD operation for dividing the Y value of the horizontal line by the Y width of the halftone pattern and obtaining the remainder is performed.   12. The image processing method according to claim 11, wherein the halfton pattern shift value generation step divides the X value of the horizontal line by the X width of the halfton pattern and performs a MOD operation for obtaining the remainder.   A computer-readable recording medium having recorded thereon a program that causes a computer to execute the image processing method according to any one of claims 11 to 20.

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