JP2005258650A - Image processor and image processing method and computer-readable recording medium for recording program for making computer perform image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize high-speed processing while maintaining high quality by determining an attribute region configuring the image information of a processing object, and switching and processing the attributes of the pixels. <P>SOLUTION: This image processor for inputting image information such as pictures, graphics and characters, and for performing predetermined image processing to the image information is provided with a drawing means(CPU101) for generating multi-value band data from the image information, a multi-value band memory region 104a for storing the multi-value band data and an image processor 110 for determining a plurality of attributes configuring the image information from the multi-value band data stored in the multi-value band memory 104a, and for performing image processing for every attribute. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus and an image processing method mounted on an image forming apparatus such as a color printer, a color copying machine, and a color MFP, and a computer-readable recording medium on which a program for causing a computer to execute the image processing method is recorded. It is about.

Conventionally, many methods for color conversion have been proposed in the fields of color printing, color televisions, color copying machines, and the like. As one of them, there is a method of directly converting from an input color space, such as an RGB system, to an output color space, such as a CMYK system, using a table memory. However, the amount of information becomes very large when three-color signals such as RGB are converted into digital signals at resolutions of density steps that require them. Therefore, the capacity of the table memory becomes enormous and the cost becomes very high. For example, if 8 bits are assigned to each input RGB color, and each output CMYK color is output in 8 bits, a memory of 2 ²⁴ × 4 bytes is required, which is not practical.

  Therefore, conventionally, a method using interpolation has been mainly studied as a method for reducing the memory capacity when color conversion is performed using a table memory. That is, a method is disclosed in which a memory capacity is reduced by using a color correction memory with the higher-order BIT of the input signal as an address, and the coarser portion is corrected by an interpolation circuit using the lower-order BIT (for example, (See Patent Documents 1 and 2).

  FIG. 43 shows an example of a color space divided into 16 parts by the upper 4 bits. An example of division into tetrahedrons is shown in FIG. Table 1 shows a list of tetrahedron determinations and interpolation coefficients.

  In addition, as a method for realizing the above method by software of the CPU, an input unit for inputting an image, a recognition unit for recognizing the color of a pixel constituting the input image by the input unit, and a recognition unit. A color unit conversion unit that converts each color into another color, a storage unit that stores the correspondence between the color recognized by the recognition unit and the color converted by the color unit conversion unit, and the pixels constituting the image Color conversion of input RGB data having a storage unit for color and a pixel unit conversion unit for converting the color of pixels constituting an image into another color corresponding to the color stored in the storage unit There is disclosed a method that saves the amount of calculation by storing CMYK data output after processing corresponding to input RGB data and saving CMYK data and checking a correspondence table before conversion (for example, Patent Document 3). reference).

  FIG. 45 shows the configuration of an image processing apparatus mounted on a conventional color printer or the like. The image processing apparatus includes a drawing processing device 50, a color conversion processing device 51, a gradation processing device 52, and a binary band memory 53. In this configuration, after drawing an object by the drawing processing device 50, the color conversion processing of the object is performed by the color conversion processing device 51, and thereafter, the gradation processing of the object is performed by the gradation processing device 52, and within one band. When all objects are finished, a binary band memory is created.

  However, in the image processing apparatus as shown in FIG. 45 described above, degradation of image quality has been a problem in the logical operation for generating CMYK 4-plane image data. In order to solve this problem, a multi-valued CMY band memory is configured to perform a logical operation on the multi-valued CMY band (see, for example, Patent Document 4).

  In addition to an image memory that stores image pixels, in order to perform image processing that is optimal for the characteristics of each image element for a plurality of image elements having different characteristics on one page, it corresponds to the pixels of the image memory. This is realized by including a tag memory for storing attributes (see, for example, Patent Document 5).

  Similarly, in order to improve color reproducibility in the output image by performing color processing corresponding to the type of object, a flag for storing attribute information corresponding to the pixels of the band memory, in addition to the band memory for storing the image The color processing apparatus has a memory, reads both the band memory and the flag memory, and realizes color processing in which the contents of the band memory are different for each pixel according to the attribute of the flag memory (see, for example, Patent Document 6).

  As a compression method for binary images, JBIG (Joint Bi-level Image Experts Group), which is an international standard for binary image coding, is known.

Japanese Patent Publication No.58-16180 Japanese Patent Laid-Open No. 2-1887374 JP-A-9-224160 JP 2001-18455 A Japanese Patent No. 2830690 JP-A-10-51653

  However, the conventional techniques as described above have the following problems. First, the methods disclosed in Patent Documents 1 and 2 can reduce the memory capacity as compared with the case where all the table memories are provided, but a large memory capacity is required to increase accuracy. For example, in the case of a 16-division color conversion table using the upper 4 BITs of the processed image, 2、２12 × 8 BIT × 4 memory is required.

  In the case of Patent Document 3, the CPU software is a good method. However, in the case of hardware, it is more important to read the data from the memory than the calculation. It is more desirable to reduce memory access than to reduce it. In the case of Patent Document 4, a band memory is configured with CMY data after color conversion, and then a K version is generated by UCR processing to generate CMYK data. And then the CMYK data is generated by an empirical method rather than the theoretical method of generating the CMYK data from the CMY data, and the method of generating the CMYK data from the RGB data is more theoretical. The image quality is improved.

  In Patent Documents 5 and 6, since a memory for storing attributes for each pixel of an image is used, a large capacity memory is used, and a large cost is required. In particular, even in an area where no object exists, it is a waste of memory that the pixel similarly has an area for storing attributes. In addition, since it is difficult to store the memory for storing the attribute inside the semiconductor, since the memory is provided outside, improvement in processing efficiency is hindered.

  The present invention has been made in view of the above, and by determining the attribute area constituting the image information to be processed and switching the attribute of the pixel to perform processing, high-speed processing is performed while maintaining high image quality. It aims to be realized.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 inputs image information including photographs, graphics, characters, etc., and executes predetermined image processing on the image information. In the image processing apparatus, a drawing means for generating multi-value band data from the image information, a multi-value band data storage means for storing the multi-value band data, and a multi-value band stored in the multi-value band data storage means And image processing means for determining a plurality of attributes constituting the image information from the data and performing image processing for each of the attributes.

  According to the first aspect of the present invention, for image information in which different attributes (photographs, graphics, characters, etc.) are mixed in band or page units, it is determined whether the pixels in the area are the target of the attribute. By executing predetermined image processing (color conversion, gradation processing, etc.), it is possible to reduce the memory capacity compared to a conventional processing device that corresponds one-to-one with one RGB pixel.

  According to a second aspect of the present invention, the image processing means includes pixel attribute generation means for generating attributes of a pixel being processed from attribute information of a plurality of rectangular areas.

  According to the second aspect of the present invention, in the first aspect, by generating the attribute of the pixel being processed by the pixel attribute generating means from the attribute information of a plurality of rectangular areas, the image band or the pixel of the page Therefore, it is possible to determine whether each pixel is a processing target / non-target only in a square area indicating the attribute without requiring an attribute memory for recording the attribute.

  Further, the invention according to claim 3 is characterized in that the image processing means includes flag information storage means for storing flag information indicating presence / absence of an attribute object for each pixel in the rectangular region.

  According to the invention of claim 3, in claim 1, the flag information storage means stores flag information indicating the presence or absence of the attribute object for each pixel in the square area, so that the entire square area stores the attribute. Each pixel need not have flag information.

  According to a fourth aspect of the present invention, the pixel attribute generation means includes a rectangular area attribute information storage means for storing attribute information of a plurality of rectangular areas, and a plurality of rectangular areas in which pixels being processed are set for each band. And an area determination means for determining whether the area is included.

  According to the fourth aspect of the present invention, in the second aspect, the priority order is determined based on the rectangular information indicating each area for each band, the attribute information (photo, character, graphics, etc.) of the rectangular area and the overlap of the rectangular area. Can be determined.

  According to a fifth aspect of the present invention, the pixel attribute generation means obtains an address of the flag information storage means from a plurality of area information obtained by the square area attribute information storage means and the coordinates of the processing pixel. A generation means is provided.

  According to the fifth aspect of the present invention, in the fourth aspect, the flag information address generation means obtains the address of the flag information storage means from the plurality of area information obtained by the square area attribute information storage means and the coordinates of the processing pixel. This makes it possible to specify the attribute information of the rectangular area.

  According to a sixth aspect of the present invention, the rectangular area attribute information storage means includes coordinate storage means for storing coordinate values indicating a plurality of rectangular areas, and the number of the plurality of rectangular areas stored in the coordinate storage means. And an effective number storage means for storing.

  According to the invention of claim 6, in claim 4, the square area attribute information storage means stores the coordinate storage means for storing coordinate values indicating a plurality of square areas, and the plurality of pieces stored in the coordinate storage means. An effective number storage means for storing the number of rectangular areas, storing a plurality of rectangular areas as coordinate values, and storing the effective number of the rectangular areas, thereby making it possible to determine the presence or absence of an attribute in the rectangular area .

  Further, the invention according to claim 7 is characterized in that the square area attribute information storage means stores a priority order when square areas having a plurality of attributes overlap.

  According to the invention of claim 7, in claim 4, by storing the priority order when square areas having a plurality of attributes overlap, the priority order when different attributes overlap in the square area is clearly defined. Become.

  In the invention according to claim 8, the rectangular area attribute information storage means stores a frame type indicating whether the rectangular area having a plurality of attributes is a flag indicating an attribute object for each pixel in the rectangular area. It is characterized by that.

  According to the invention according to claim 8, in claim 4, by storing the frame type indicating whether the square area having a plurality of attributes is a flag indicating the attribute object for each pixel, It can be seen whether the region overlap priority and flag are provided.

  The invention according to claim 9 is characterized in that the image processing means further comprises a color conversion table storage means for storing a color conversion table for a plurality of rectangular regions having different attributes.

  According to the ninth aspect of the invention, in the first aspect, the color conversion table storage means for storing the color conversion table for a plurality of square areas having different attributes is provided, whereby color conversion for each attribute can be performed. become.

  The invention according to claim 10 is characterized in that the image processing means selects a different color conversion table for each of a plurality of rectangular regions in which pixels being processed are set for each band.

  According to the invention of claim 10, in claim 9, it is determined in real time whether a plurality of regions having different attributes are included for each pixel to be processed in band or page units, and a color conversion table is determined according to the result. By selecting, color conversion processing with excellent color reproducibility is realized.

  The invention according to claim 11 is characterized in that the image processing means further includes a threshold value table storage means for storing a threshold value table for a plurality of rectangular regions having different attributes.

  According to the invention according to claim 11, gradation processing for each attribute is performed by providing threshold value table storage means for storing a threshold value table for a plurality of square areas having different attributes. It becomes possible.

  The invention according to claim 12 is characterized in that the image processing means selects a different threshold value table for each of a plurality of rectangular regions in which pixels being processed are set for each band.

  According to the twelfth aspect of the present invention, in the twelfth aspect, it is determined in real time whether a plurality of regions having different attributes are included in each band or page for each pixel to be processed, and a threshold value is determined according to the result. By selecting a table, gradation processing with excellent reproducibility is realized.

  According to a thirteenth aspect of the present invention, there is provided an image processing method for inputting image information including photographs, graphics, characters, etc., and executing predetermined image processing on the image information. A plurality of attributes constituting the image information from a drawing step for generating data, a multi-value band data storage step for storing the multi-value band data, and multi-value band data stored in the multi-value band data storage means And an image processing step of performing image processing for each attribute.

  According to the thirteenth aspect of the present invention, for image information in which different attributes (photographs, graphics, characters, etc.) are mixed in band or page units, it is determined whether the pixels in the area are the target of the attribute. By executing predetermined image processing (color conversion, gradation processing, etc.), it is possible to reduce the memory capacity as compared with the conventional processing method corresponding to one RGB pixel one-to-one.

  The invention according to claim 14 is characterized in that a program for causing a computer to execute the image processing method according to claim 13 is recorded.

  According to the fourteenth aspect of the present invention, the image processing method according to the thirteenth aspect can be performed on the computer by recording the program that causes the computer to execute the image processing method according to the thirteenth aspect. become.

  In the image processing apparatus according to the present invention (Claim 1), whether or not the pixel in the area is a target of attribute for image information in which different attributes (photos, graphics, characters, etc.) are mixed in band or page units. Therefore, by executing predetermined image processing (color conversion, gradation processing, etc.), it is possible to reduce the memory capacity compared to a conventional processing device that corresponds one-to-one with one RGB pixel. In addition to realizing high-speed processing with a small memory capacity, it is possible to provide an image processing apparatus that outputs high-quality images by performing processing for each attribute region.

  According to a second aspect of the present invention, there is provided an image processing apparatus according to the first aspect, wherein the pixel attribute being processed by the pixel attribute generation means is generated from the attribute information of a plurality of rectangular areas, thereby generating an image band. It is possible to determine whether each pixel is a processing target / non-target only in a square area indicating the attribute without requiring an attribute memory for recording the attribute for each pixel of the page. There is an effect that the capacity can be reduced.

  An image processing apparatus according to a third aspect of the present invention is the image processing apparatus according to the first aspect, wherein the flag information storage unit stores flag information indicating the presence / absence of an attribute object for each pixel in the square region. Stores the attribute, and each pixel does not need to have flag information, so that it is possible to perform processing for each attribute area with a small memory capacity.

  The image processing apparatus according to the present invention (Claim 4) is characterized in that, in Claim 2, the square information indicating each area for each band, the attribute information (photo, character, graphics, etc.) of the square area, and the square area Since the priority order can be determined from the overlap of the images, it is possible to preferentially process the images having the attribute overlapping the same square region.

  The image processing apparatus according to the present invention (Claim 5) is the flag information of the flag information storage means according to Claim 4 from the plurality of area information obtained by the square area attribute information storage means and the coordinates of the processing pixels. By obtaining the address generation means, it becomes possible to specify the attribute information of the rectangular area, so that it is possible to specify a fine attribute.

  The image processing apparatus according to the present invention (Claim 6) is characterized in that, in Claim 4, the square area attribute information storage means stores coordinate values indicating coordinate values indicating a plurality of square areas, and the coordinate storage means. Effective number storage means for storing the number of stored square areas, storing the plurality of square areas as coordinate values, and storing the effective number of the square areas, thereby determining whether or not there is an attribute in the square area Therefore, the presence / absence of the attribute in the rectangular area is clarified, and the processing efficiency is improved.

  An image processing apparatus according to a seventh aspect of the present invention is the image processing apparatus according to the fourth aspect, wherein the priority order in the case where the square areas having a plurality of attributes overlap is stored, whereby different attributes overlap in the square area. Since the priority is clarified, the processing efficiency is improved.

  The image processing apparatus according to the present invention (Claim 8) is characterized in that, in Claim 4, the frame type indicating whether the square area having a plurality of attributes is a flag indicating an attribute object for each pixel in the square area. By storing, it can be seen whether the frame type has the priority order of overlapping of the rectangular areas and the flag, and therefore, there is an effect that fine processing and efficient processing are realized.

  The image processing apparatus according to the present invention (Claim 9) further comprises color conversion table storage means for storing a color conversion table for a plurality of square regions having different attributes, thereby providing color conversion for each attribute. Therefore, color conversion corresponding to each attribute is realized.

  In addition, the image processing apparatus according to the present invention (Claim 10) determines in real time whether or not a plurality of regions having different attributes in each band or page are included in each pixel to be processed. Since the color conversion table is selected according to the above, there is an effect that color conversion processing with excellent color reproducibility can be performed.

  The image processing apparatus according to the present invention (claim 11) is the image processing apparatus according to claim 1, further comprising threshold value table storage means for storing a threshold value table for a plurality of square areas having different attributes. Since gradation processing can be performed, there is an effect that gradation processing corresponding to each attribute is realized.

  The image processing apparatus according to the present invention (Claim 12) determines in real time whether or not a plurality of regions having different attributes in each band or page are included in each pixel to be processed. Since the threshold value table is selected according to the above, there is an effect that gradation processing with excellent reproducibility is realized.

  In addition, in the image processing method according to the present invention (claim 13), pixels in the area are targeted for the attribute with respect to image information in which different attributes (photos, graphics, characters, etc.) are mixed for each band or page. By determining whether it is present and executing predetermined image processing (color conversion, gradation processing, etc.), it is possible to reduce the memory capacity as compared with a conventional processing device that corresponds one-to-one with one RGB pixel. Therefore, high-speed processing with a small memory capacity is realized, and an image processing method for high-quality image output can be provided by performing processing for each attribute region.

  Moreover, since the computer-readable recording medium concerning this invention (Claim 14) recorded the program which makes a computer perform the image processing method of Claim 13, it recorded the image of Claim 13 on a computer. There is an effect that the processing operation can be performed.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Exemplary embodiments of an image processing apparatus, an image processing method, and a computer-readable recording medium storing a program for causing a computer to execute the image processing method according to the present invention will be described below in detail with reference to the accompanying drawings. . The present invention is not limited to this embodiment.

(Summary of Invention)
In the present invention, as shown in FIGS. 1 to 4, each pixel is RGB of a photographic image or RGB of a graphics image in addition to the multi-value RGB data when the printer draws each band with multi-value RGB. Or attribute information indicating whether the character image is RGB.

  Generally, each RGB pixel has attribute information corresponding to one-to-one like multi-value RGB band data. On the other hand, according to the present invention, first, as attribute information, not every pixel but as square information enclosed by XS, XE, YS, and YE. Thereby, since a general photographic image is a square, processing by a square area becomes possible. Since characters and graphics images are not square, as shown in FIGS. 1 to 4, character information is given as square information of XS, XE, YS, and YE surrounding the character area, and 1 BIT corresponding to the square is obtained. FLAGBIT determines whether each pixel is a target / non-target of an attribute, and supports a complicated outer shape image.

  For example, as shown in FIG. 1, when one page is divided into bands 0 to 7, image information including photographic image areas P1, P2, P3, character areas T1, T2, and graphics area G1 is mixed for each band. In many cases, image processing is performed. Here, each area is designated by a rectangular area surrounded by coordinates XS, XE, YS, and YE. FIG. 2 shows attributes of each area in band 5 of FIG. 1, FIG. 3 shows an image of a multi-value band memory area described later, and FIG. 4 shows data in the FLAGBIT memory.

  In order to set the attribute of the area in the area “0” like the area “3” shown in FIG. 2, each area is given a priority. As a result, in the overlapping rectangular area, the area of higher priority determines the attribute of the pixel. In the example shown in FIG. 2, the area “3” has higher priority than the area “0”, and the area “3” A pixel becomes a character area. Since the area “3” has FLAGBIT, the area where FLAGBIT is “1” is a character, and the area where “0” is given the attribute of the next priority, and the area “0” It has a picture image attribute.

  That is, paying attention to the fifth band in FIG. 2, as shown in FIG. 2, the attribute of the photographic image is stored as a rectangular area surrounding the photographic image in the area “0” with XS0, XE0, YS0, and YE0. In the character area “, the square area enclosed by XS1, XE1, YS1, and YE1 has the attribute of the character area. At this time, for each pixel of the area“ 1 ”, FLAGBIT indicating the target / non-target of the attribute of this area As shown in FIG. 4, a pixel whose flag flag is “1” in this region “1” is a target of an attribute, but a pixel whose flag is “0” is not a target. Since the area “2” is a graphics area and cannot be expressed in a rectangular area, it has a FLAGBIT having an outer shape of a graphics image as shown in FIG.

  In addition, the area “3” is in the photographic image of the area “0”. In order to cope with such a case, priority is given to each region, and pixels in a plurality of regions are made to follow the attribute of the region having a high priority of the region. Therefore, the priority of the area “3” is set higher than the priority of the area “0”. In the case where the upper region in the case of overlapping as described above has FLAGBIT, the pixel having FLAGBIT of “0” has the attribute of the next priority region. By performing the processing in this manner, it is possible to perform image processing with the pixel of the character portion in the region “3” having the character attribute and the pixel of the non-character portion having the attribute of the photographic image. Table 2 shows the relationship of attributes, priorities, etc. to the above areas.

  This method has a smaller memory capacity for storing attributes than the conventional one. In particular, FLAGBIT is not used in a region where no object is present on the band image. Further, FLAGBIT is 1 BIT and basically does not have attribute information, and the attribute information has square information of XS, XE, YS, and YE.

  The color conversion table is selected by determining in real time whether or not a plurality of rectangular areas having different attributes for each band or page are included in each area for each pixel processed by the image processing apparatus, and color conversion processing is performed. Selects a threshold matrix and performs gradation processing to achieve high-speed printer image processing and high image quality. Also, since objects with text and graphics attributes cannot be represented in the square area, the attributes for each square area It has a FLAGBIT that expresses whether it is a pixel having, and makes it possible to specify a fine attribute. This will be specifically described below.

(Embodiment)
First, the configuration and operation of an image forming apparatus (printer) in which the image processing apparatus according to the present invention is mounted will be described. FIG. 5 is an explanatory diagram illustrating a configuration example of a mechanism unit of the image forming apparatus according to the embodiment of the present invention. Hereinafter, the image forming apparatus in FIG. 5 is described as a color printer. In this embodiment, a laser color printer is taken as an example, but another color printer such as an ink jet printer may be used.

  The color printer 100 shown in FIG. 5 has four color images (Y (yellow), M (magenta), C (cyan), K (black))) arranged independently according to laser light writing and electrophotographic processes. This is a four-drum tandem engine type image forming apparatus that forms the image forming systems 1Y, 1M, 1C, and 1K, and sequentially superimposes and transfers these four color images on a recording sheet.

  Each of the image forming systems 1Y, 1M, 1C, and 1K includes a photoconductor as an image carrier, for example, small-diameter OPC (organic photoconductor) drums 2Y, 2M, 2C, and 2K, and the OPC drums 2Y, 2M, and 2C. The electrostatic latent images on the charging rollers 3Y, 3M, 3C, and 3K as charging means and the OPC drums 2Y, 2M, 2C, and 2K are developed with a developer from the upstream side of image formation so as to surround 2K. Developing devices 4Y, 4M, 4C, and 4K that generate toner images of Y, M, C, and K colors, cleaning devices 5Y, 5M, 5C, and 5K, and static eliminating devices 6Y, 6M, 6C, and 6K are arranged. .

  Beside each developing device 4Y, 4M, 4C, and 4K, a toner bottle unit 7Y that supplies toner of a predetermined color to the developing devices 4Y, 4M, 4C, and 4K with Y toner, M toner, C toner, and K toner, respectively. , 7M, 7C, 7K are arranged. In addition, each of the image forming systems 1Y, 1M, 1C, and 1K is provided with laser-based optical writing devices 8Y, 8M, 8C, and 8K. The optical writing devices 8Y, 8M, 8C, and 8K are laser light sources. Laser diode (LD) light sources 9Y, 9M, 9C, and 9K, collimating lenses 10Y, 10M, 10C, and 10K, fθ lenses 11Y, 11M, 11C, and 11K, polygon mirrors 12Y as deflection scanning means, 12M, 12C, and 12K, and folding mirrors 13Y, 13M, 13C, 13K, 14Y, 14M, 14C, and 14K.

  The image forming systems 1Y, 1M, 1C, and 1K are arranged vertically, and the transfer belt unit 15 is arranged on the right side so as to be in contact with the OPC drums 2Y, 2M, 2C, and 2K. The transfer belt unit 15 is rotationally driven by a drive source (not shown) with the transfer belt 16 stretched around rollers 17 to 20. A paper feed tray 21 storing recording paper as a transfer material is disposed on the lower side of the apparatus, and a fixing device 22 having a heat fixing roller and a pressure roller, a paper discharge roller 23, and a paper discharge tray 24 are arranged at the top of the apparatus. It is installed.

  At the time of image formation, in each image forming system 1Y, 1M, 1C, 1K, the OPC drums 2Y, 2M, 2C, 2K are rotationally driven by a driving source (not shown), and are charged by charging rollers 3Y, 3M, 3C, 3K. The OPC drums 2Y, 2M, 2C, and 2K are uniformly charged, and the optical writing devices 8Y, 8M, 8C, and 8K modulate the laser diode based on the image data of each color, and deflect and scan the laser light to scan the OPC drum 2Y. By performing optical writing on 2M, 2C, and 2K, electrostatic latent images are formed on the OPC drums 2Y, 2M, 2C, and 2K.

  The electrostatic latent images on the OPC drums 2Y, 2M, 2C, and 2K are developed by developing devices 4Y, 4M, 4C, and 4K, respectively, to become toner images of colors Y, M, C, and K, while the paper feed tray 21 Then, the transfer paper is fed in the horizontal direction from the paper feed roller 25 and is conveyed vertically in the image forming systems 1Y, 1M, 1C and 1K by the transport system. This recording paper is electrostatically attracted and held on the transfer belt 16 and conveyed by the transfer belt 16, and a transfer bias is applied by a transfer bias applying means (not shown) so as to be on the OPC drums 2Y, 2M, 2C and 2K. A full color image is formed on the recording paper by sequentially superimposing and transferring the toner images of each color Y, M, C, and K onto the recording paper. The recording paper on which the full-color image is formed is fixed by the fixing device 22 to the full-color toner image by the action of heat and pressure, and is discharged to the discharge tray 24 by the discharge roller 23.

  Next, the configuration and operation of the image processing apparatus in the color printer configured as described above will be described. FIG. 6 is a block diagram showing the configuration of the electrical / control system of the image forming apparatus in FIG. This electrical / control system is a CPU 101 that controls the entire color printer 100, a CPU I / F 102 that is connected to the memory controller 103 and executes interface control between the CPU 101 and the memory controller 103, a main memory 104, and a local bus of the CPU 101. A memory controller 103 that controls transfer between the decoding device, the image processing device, the encoding device, and the main memory is provided.

  Also, the main memory 104, ROM 106, panel controller 107, etc. for storing images to be printed, CPU 101 control programs, various data, etc., and the local I / F 105 for executing interface control with the CPU 101, main memory 104, characters, etc. ROM 106 for storing font information and control program for CPU 101, panel controller 107 for controlling operation panel 108, operation panel 108 for notifying the printer of user input operations, memory for receiving various data and commands connected to the network The communication controller 109 connected to various controllers via the controller 103 and the color change for the band image data drawn by the CPU 101. An image processing apparatus 110 that performs processing and gradation processing and transfers the image data that has been converted into binary data to the main memory 104, and encodes the binary band data in the main memory 104 and transfers the code to the main memory 104 Decoding device 111, receiving code encoded by encoding device 111, decoding each plate, and transferring to C (cyan), M (magenta), Y (yellow), K (black) plate engine controller An engine controller 113 that receives image data from each decoding processing device and transfers it to each version of the printer engine 114; and a printer engine 114 (see FIG. 5) that forms C, M, Y, and K version images. I have.

  The decoding device 112 includes a C version decoding processing device 112C, an M version decoding processing device 112M, a Y version decoding processing device 112Y, and a K version decoding processing device 112K. The engine controller 113 includes a C version engine controller 113C, an M version engine controller 113M, a Y version engine controller 113Y, and a K version engine controller 113K. The printer engine 114 includes a C plate printer engine 114C, an M plate printer engine 114M, a Y plate printer engine 114Y, and a K plate printer engine 114K.

  FIG. 7 is a block diagram showing a schematic processing system of image data according to the embodiment of the present invention. In this figure, a multi-value RGB band is generated by the CPU 101, and the generated multi-value RGB band data is stored in the multi-value RGB band memory 104 a of the main memory 104. The color conversion processing device 120 of the image processing device 110 performs color conversion on the multi-value RGB band data stored in the multi-value RGB band memory 104a. The gradation processing device 121 of the image processing device 110 performs gradation processing on the multivalued CMYK data color-converted by the color conversion processing device 120, and binary CMYK band data for each of C, M, Y, and K. 122 is stored in the memory area. The encoding device 111 encodes C, M, Y, K binary band data stored in the main memory 104 and stores one page in the code page memory area. The data encoded by the encoding device 111 is decoded by the decoding processing device 112 for each version, and transferred to the engine controller 113 as binary CMYK page data 124. These details are described below.

  FIG. 8 is a functional block diagram for processing image data according to the embodiment of the present invention. FIG. 9 is an explanatory diagram showing the format of the main memory 104. As shown in these figures, this format includes a multi-value band memory area 104a that is an area for storing multi-value RGB data for one band, a FLAGBIT memory area 104b corresponding to pixels in the multi-value band memory area, an image Binary band memory storage areas 104c, 104m, 104y, and 104k for C, M, Y, and K versions, which are areas for storing the processed binary, quaternary, and 16-value band information for each version. The C, M, Y, and K code page memory areas 104cc, 104cm, 104cy, 104ck, and the control program for the CPU 101, which are the page memory areas of the codes obtained by encoding the binary band memory data of each version for each version, A program area 104p for storage is prepared.

  In FIG. 8, the CPU 101 draws a band of multi-value RGB data in the multi-value band memory area 104a. The image processing device 110 reads the multi-value RGB data band data in the multi-value band memory area 104a and the FLAGBIT data in the FLAGBIT memory area 104b, and performs color conversion processing, gradation processing, etc. To the binary band memory area (104m to 104k). The band data of multi-value RGB data, FLAGBIT data, codes for each band obtained by the encoding device 111, and the like are stored in the code page memory area (104cc to 104ck). The data in the binary band memory area of each version is encoded by the encoding device 111 and written to the code page memory area (104 cc to 104 ck) of each version of the main memory 104. The decoding device 112 of each version reads the code from the code page memory area (104 cc to 104 ck) of each version, decodes it, and transfers it to the engine controller 113 of each version. Each printer engine 114 forms an image of each color according to this image.

  FIG. 10 is a block diagram showing how multi-value band data is generated according to the embodiment of the present invention. As shown by the arrows in FIG. 10, the CPU 101 generates RGB bands and FLAGBIT data in the main memory 104 via the CPU I / F 102 and the memory controller 103.

  FIG. 11 is a block diagram showing a state of image processing according to the embodiment of the present invention. As shown by the arrows in FIG. 11, when printing the image as shown in FIG. 1, the CPU 101 sends a square indicating each area for each band as shown in Table 2 to the area determination device of the image processing apparatus 110 for each band. Information and attribute information of the rectangular area (photograph image, character, graphics, etc.), priority of overlapping of the rectangular areas, and a frame type and FLAGBIT indicating whether the rectangular information has FLAGBIT The FLAGBITBASE address, which is the base address on the FLAGBIT memory area 104b, is sent. The image processing apparatus 110 reads multi-value RGB from the multi-value band memory area 104 a of the main memory 104 and performs image processing. At this time, the image processing apparatus 110 determines whether the pixel to be subjected to image processing is related to the rectangular area information set as shown in Table 2 above. In such a case, the attribute is obtained to obtain the binary band memory areas 104c to 104k. Forward to.

  FIG. 12 is a block diagram showing a state of the encoding process according to the embodiment of the present invention. As indicated by the arrows in FIG. 12, the encoding device 111 reads and encodes the gradation-processed images from the plate binary band memory areas 104c to 104k of the main memory 104. The encoding device 111 transfers the encoded data to the plate code page memory areas 104 cc to 104 ck of the main memory 104.

  FIG. 13 is a block diagram showing a print output process according to the embodiment of the present invention. As indicated by the arrows in FIG. 13, each version of the decoding processor 112 reads and decodes the code from the code page memory areas 104 cc to 104 ck of each version of the main memory 104 in synchronization with the printer engine 114. The decryption processing device 112 transfers the decrypted gradation data of each version to the engine controller 113 of each version. Each version of the engine controller 113 transfers data to each version of the printer engine 114 in synchronization with each version of the printer engine 114.

  Next, the detailed configuration and operation of each functional block described above will be described. FIG. 14 is a block diagram showing a configuration of the image processing apparatus 110 according to the embodiment of the present invention. As illustrated, the image processing apparatus 110 includes a memory controller I / F 125, a BUF (buffer) 126 for temporarily storing RGB data, a BUF (buffer) 127 for temporarily storing FLAGBIT data, a color conversion processing apparatus 128, a gradation. The processing device 129 includes a BUF (buffer) 130, a DELAY (delay buffer) 131, a pixel attribute generation device 132, a memory address generation device 133, and a controller 134 that temporarily store binary CMYK plane data.

  The memory controller I / F 125 receives image data from the multilevel band memory area 104 a of the main memory 104, transfers the image data to the color conversion processing device 128 and the gradation processing device 129, and the data after gradation processing is stored in each main memory 104. Transfer to the binary band memory areas 104c to 104k of the plate. The address is received from the pixel attribute generation device 132, and FLAGBIT data is read from the FLAGBIT memory area 104 b of the main memory 104 and transferred to the pixel attribute generation device 132. The BUF 126 temporarily stores the multi-value band image data received from the memory controller I / F 125. The BUF 127 temporarily stores the FLAGBIT data received from the memory controller I / F 125.

  The color conversion processing device 128 sequentially reads image data from the multi-value band memory area 104 a of the main memory 104, performs color conversion processing, and transfers the image data to the gradation processing device 129. Details of the color conversion processing device 128 will be described later. The gradation processing device 129 receives the data after color conversion processing from the color conversion processing device 128, performs gradation processing, and transfers the data to the BUF 30. Details of the gradation processing device 129 will be described later.

  The BUF 130 temporarily stores the data after gradation processing received from the gradation processing device 129. The DRAY (delay buffer) 131 delays the pixel attribute FLAG from the pixel attribute generation device 132 by the pipeline of the color conversion processing device 128. The pixel attribute generation device 132 receives a command as shown in Table 2 from the CPU 101 and generates an attribute of a pixel to be processed by the color conversion processing device 128 and the gradation processing device 129. The memory address generation device 133 generates an address of the multi-level band memory area 104a of the main memory 104 and addresses of the binary band memory areas 104c to 104k of the respective versions. The controller 134 controls the entire image processing apparatus 110.

  FIG. 15 is a block diagram illustrating a configuration of the pixel attribute generation device 132 of the image processing device 110 in FIG. The pixel attribute generation device 132 includes a horizontal pixel count device 135, a vertical pixel count device 136, a rectangular information storage device 137, an area determination device 138, a FLAGBIT address generation device 139, and a controller 140.

  The horizontal pixel counting device 135 counts the horizontal pixel value of the pixel processed by the color conversion processing device 128 and outputs the number of horizontal pixels. The vertical pixel counting device 136 counts the vertical pixel values of the pixels processed by the color conversion processing device 128 and outputs the number of vertical pixels. As shown in Table 2, the square information storage device 137 has rectangular information indicating each area of the band, attribute information (photo image, character, graphics, etc.) of the rectangular area, and priority of overlapping of the rectangular areas. A frame type indicating whether the square information has FLAGBIT, a FLAGBITBASE address which is a base address on the FLAGBIT memory area 104b in the case of having FLAGBIT, and the like are stored. Details of the rectangular information storage device 137 will be described later.

  The area determination device 138 receives the number of horizontal pixels from the horizontal pixel counting device 135 and the number of vertical pixels from the vertical pixel counting device 136, and the pixel currently being processed indicates an area of each attribute from the rectangular information storage device 137. From the rectangular information and its priority, the attribute of the highest area of the area to be processed (the highest priority is given when multiple areas overlap) and the next area (the priority is higher than the highest area). If the uppermost area has FLAGBIT, the FLAGBIT data corresponding to the pixel to be processed is read by sending the uppermost area number to the FLAGBIT address generator 139, and FLAGBIT is read. Based on the data value, it is determined whether the attribute is the highest attribute or the next attribute, and the color conversion processing device sends pixel attribute information. Details of the area determination device 138 will be described later.

  The FLAGBIT address generation device 139 receives the number of horizontal pixels from the horizontal pixel counting device 135 and the number of vertical pixels from the vertical pixel counting device 136, and the currently processed pixel stores the area of each attribute from the rectangular information storage device 137. The square information shown and the FLAGBIT base address of each square area of the FLAGBIT memory area 104b of the main memory 104 are received, the highest area number is received from the area determination device 138, and the address of the FLAGBIT memory area 104b of the pixel currently being processed is received. It is generated and sent to the memory controller I / F 125. Details of the FLAGBIT address generation device 139 will be described later. The controller 140 controls the pixel attribute generation device 132.

  Next, the operation of the pixel attribute generation device 132 configured as described above will be described with reference to the flowchart of FIG. This operation is controlled by the controller 140. Further, as an example of the image and the processing example, FIGS. 1 to 4 and Table 2 described above are taken as examples. First, the numbers of pixels of the horizontal pixel counting device 135 and the vertical pixel counting device 136 are initialized (step S1), and a plurality of photographic image areas, character areas, and graphics areas in the multi-value band are set (step S1). S2). Subsequently, the FLAGBIT in the square is set to the FLAGBIT area in order to show the details of the character area and the graphics area where the detail area is not square (step S3). Further, the number of horizontal pixels is set to 0 (step S4), and the region determination device 138 obtains the region number included in the number of horizontal pixels and the number of vertical pixels indicating the position of the multi-value band in the set square regions (step S5). In this area number, the highest area number which is the highest priority area number and the lower priority area number which is the next priority are obtained (step S6).

  Subsequently, it is determined whether or not the region having the highest region number is a region having FLAGBIT (step S7). If it is determined that the area with the highest area number is an area having FLAGBIT, the address of the FLAGBIT area is obtained and the FLAGBIT data is read from the FLAGBIT area of the main memory 104 (step S8). On the other hand, if it is determined that the region with the highest region number is not a region having FLAGBIT, the attribute of the highest region is set as the attribute of the pixel (step S9), and the process proceeds to step S13.

  After executing the process of step S8, it is further determined whether or not the FLAGBIT data is 1 (step S10). If FLAGBIT data = 1, the attribute of the uppermost area is set as the attribute of the pixel (step S11). On the other hand, if FLAGBIT data is not 1, the attribute of the lower area is set as the attribute of the pixel (step S11). S12). After executing step S11 or step S12, the number of horizontal pixels is incremented by one (step S13), and it is determined whether or not the number of horizontal pixels has reached the multi-value band horizontal width (step S14). Here, if the number of horizontal pixels = the multi-value band horizontal width, the number of vertical pixels is incremented by one (step S15), and it is determined whether or not the number of vertical pixels has reached the multi-value band vertical width (step S16). ). Here, if the number of vertical pixels = the multi-value band vertical width, this process is terminated. If the number of horizontal pixels is not the multi-value band horizontal width in step S14, the process returns to step S5. If the number of vertical pixels is not the multi-value band vertical width in step S16, the process returns to step S5.

  FIG. 17 is a block diagram showing a configuration of the rectangular information storage device 137 in FIG. This rectangular information storage device 137 includes a decoder 141, rectangular information storage registers 142, 143, 144, 145, 146, and a register 147.

  The decoder 141 decodes the address from the CPU 101 and selects the square information storage registers 142, 143, 144, 145, and 146. The square information storage register 142 stores the 0th square information. In this register, as shown in FIG. 2, XS and YS indicate the upper left of each area, and XE and YE indicate the lower right of the area. That is, XS and YS indicate the left / right ends of the X coordinate of each region, and YS and YE indicate the top / bottom of the Y coordinate. The attribute information indicates attribute information (photo image, character, graphics image, etc.) in the square area indicated by the 0th XS, XE, YS, YE. (Table 2 shows an example of the band in FIG. 2)

  The frame type indicates whether the square area indicated by the 0th XS, XE, YS, or YE has FLAGBIT data. FIG. 4 shows an example of data in the FLAGBIT memory. (Table 2 shows an example of the band in FIG. 2. In this example, the area having the character and graphics attributes has the frame type “1” and has FLAGBIT data.)

  The priority order is the priority order of the square areas indicated by the 0th XS, XE, YS, and YE. (In the example of the band in FIG. 2, there is a region “3” in the region “0”, and the region “3” has a higher priority than the region “1” as shown in Table 2.) FLAGBITBASE address is 0th When the rectangular area indicated by XS, XE, YS, YE has FLAGBIT data, it is the base address of the FLAGBIT data as shown in FIG. 4 of the FLAGBIT memory.

  The square information storage register 143 stores the first square information. The square information storage register 144 stores the second square information. The square information storage register 145 stores the third square information. The square information storage register 146 stores the nth square information. For example, if the register 147 for storing the effective number is “1”, it indicates that information is contained in the square information storage register by the 0th position. If “3”, for example, 0, 1 and 2 indicate that information is contained. For example, “0” indicates that there is no area.

  FIG. 18 is a block diagram showing the configuration of the area determination device 138 in FIG. The area determination device 138 includes square area determination processing devices 150, 151, and 152, a priority order determination device 153, and a pixel attribute determination device 154.

  The 0th area determination processing device 150 receives the 0th area information, its effective number, the horizontal and vertical pixel values of the pixel to be processed from the square information storage device 137, and determines whether the processing pixel enters the 0th area. And the determination result and its priority are transferred to the priority determination device 153. The first region determination processing device 151 receives the first region information, the effective number thereof, and the horizontal and vertical pixel values of the pixel to be processed from the rectangular information storage device 137, and determines whether the processing pixel enters the first region. And the determination result and its priority are transferred to the priority determination device 153. The nth region determination processing device 152 receives the seventh region information, its effective number, the horizontal and vertical pixel values of the pixel to be processed from the square information storage device 137, and determines whether the processing pixel enters the nth region. And the determination result and its priority are transferred to the priority determination device 153.

  The priority determination device 153 receives the determination results from the rectangular region determination processing devices 150 to 152 and their priorities, and receives the highest region number, its attribute (most attribute), its frame type (highest frame type), and region. If they overlap, the highest next attribute (next attribute) is obtained and transferred to the pixel attribute determination device 154, and the highest region number is transferred to the FLAGBIT address generation device 139.

  The pixel attribute determination device 154 receives the highest attribute, the next attribute, and the highest frame type from the priority determination device 153, and the FLAGBIT address generation device 139 stores the addressed main memory 104 as shown in FIG. The FLAGBIT data of the pixel to be processed is received from the FLAGBIT data, the attribute of the pixel is obtained, and transferred to the color conversion processing device 128.

  FIG. 19 is a block diagram illustrating the configuration of the rectangular basin determination processing devices 150 to 152 in FIG. 18. The rectangular area determination processing devices 150 to 152 include a comparison device 155 that compares XS and the number of horizontal pixels, a comparison device 156 that compares the number of horizontal pixels and XE, and a comparison device 157 that compares YS and the number of vertical pixels. A comparison device 158 that compares the number of vertical pixels with YE, a comparison device 159 that compares a square number with an effective number, an AND device 160 that performs AND processing from the comparison results of these comparison devices 156 to 159 and outputs a region determination result I have.

  That is, the comparison devices 155 and 156 determine whether or not the horizontal pixel value of the pixel to be processed falls within the area. The comparison devices 157 and 158 determine whether the vertical pixel value of the pixel to be processed falls within the area. The comparison device 159 determines whether the information processed by the square area determination processing devices 150 to 152 is valid. If the determination results of the comparison devices 156 to 159 are all OK, the AND device 160 has a pixel to be processed in this area.

  FIG. 20 is a block diagram showing the configuration of the priority determination device 153 in FIG. The priority order determination device 153 includes MUXs (multiplexers) 161 to 163, a priority order comparison device 164, and MUXs (multiplexers) 165 to 167.

  Based on the area determination result from the square area determination processing device 150, the MUX 161 transfers the priority from the rectangular area determination processing device 150 to the priority comparison device 164 if it is within the area, and if it is outside the area, Transfer the lowest priority value. Based on the area determination result from the square area determination processing device 151, the MUX 162 transfers the priority from the rectangular area determination processing device 151 to the priority comparison device 164 if it is within the area, and if it is out of the area, Transfer the lowest priority value. Based on the area determination result from the square area determination processing device 153, the MUX 163 transfers the priority from the rectangular area determination processing device 153 to the priority comparison device 164 if it is within the region, and if it is outside the region, Transfer the lowest priority value.

  The priority comparison device 164 obtains the region number of the highest priority and the region number of the next priority from the priorities from the square region determination processing devices 150, 151, and 152. The MUX 165 selects the highest attribute from the attribute values of each area from the rectangular area determination devices 150, 151, and 152 based on the highest area number from the priority comparison device 164. The MUX 166 selects the next attribute from the attribute value of each area from the rectangular area determination device based on the next area number from the priority order comparison device 164. The MUX 167 selects the highest frame type from the frame type values of the respective areas from the rectangular area determination devices 150, 151, and 152 based on the highest region number from the priority comparison device 164.

  FIG. 21 is a block diagram showing a configuration of the pixel attribute determination device 154 in FIG. The pixel attribute determination device 154 includes a register 168, an inverter 169, registers 170 to 171, an AND device 172, and a MUX (multiplexer) 173.

  The register 168 temporarily stores the highest frame type value from the priority determination device 153. Inverter 169 inverts the most significant frame type value stored in register 168. The register 170 temporarily stores the highest attribute value from the priority determination device 153. The register 171 temporarily stores the next attribute value from the priority determination device 153. The AND device 172 determines whether the most significant frame is “0” (the most significant area has no FLAGBIT data) or the most significant frame is “1” (the most significant area has FLAGBIT data) and FLAGBIT data. When the value is “1” (having the highest attribute), the highest attribute is selected by MUX 173, the highest frame is “1”, and the FLAGBIT data value is “0” (the next priority area) The next attribute is selected by the MUX 173. The MUX 173 selects a register value based on a control signal from the AND circuit 172.

  FIG. 22 is a block diagram showing a configuration of the FLAGBIT address generation device 139 in FIG. The FLAGBIT address generation device 139 includes a MUX (multiplexer) 174 and a FLAGBIT address processing device 175.

  The MUX 174 determines the XS, XE, YS, and YE square area information from the square information storage device 137 and the FLAGBITBASE of each square area of the FLAGBIT memory area of the main memory 104 based on the highest area number from the area determination device 138. The address is selected, and the uppermost XS, XE, YS, YE square area information and the FLAGBITBASE address are selected. The FLAGBIT address processing unit 175 has the horizontal pixel value of the horizontal pixel counting unit 135 and the vertical pixel value of the vertical pixel counting unit 136 shown in FIG. 15 and the XS, XE, YS, YE square area information of the uppermost area from the MUX 174. And the FLAGBITBASE address, an operation as shown in FIG. 23 is performed to obtain the FLAGBIT memory address of the pixel to be processed.

  FIG. 24 is a block diagram showing the configuration of the FLAGBIT address processing device 175 in FIG. The FLAGBIT address processing device 175 includes subtracters 176 to 178, a multiplier 179, and adders 180 and 181.

  The subtractor 176 obtains the horizontal X width in the specified area of the FLAGBIT memory as shown in FIG. As shown in FIG. 23, the subtractor 177 obtains the Y width of the pixel in the vertical direction in the designated area of the FLAGBIT memory. The subtractor 178 obtains the X width of the horizontal pixel in the specified area of the FLAGBIT memory as shown in FIG. Multiplier 179 multiplies the outputs of subtracter 176 and subtractor 177. The adder 180 obtains the relative pixel address from the base address of the FLAGBIT memory as shown in FIG. As shown in FIG. 23, the adder 181 adds the FLAGBIT base address of the area on the FLAGBIT memory to the relative address obtained by the adder 180, and obtains the FLAGBIT address which is the absolute address on the FLAGBIT memory of the pixel.

  FIG. 25 is a block diagram showing the configuration of the color conversion processing device 128 in FIG. The color conversion processing device 128 includes a lattice point selection device 182, a lattice point interpolation processing device 183, a color conversion table memory 184, a lattice point address generation device 185, and a data cutout device 186.

  The lattice point selection device 182 receives image (RGB) data from the CPU 101, divides each R, G, B component into upper NBIT and lower 8-NBIT, which are designated as HR, G, BDR, G, B, 8 It is determined which of the six tetrahedrons of a cube made up of a number of grid points corresponds to TYPE, and is transferred to the grid point address generation unit 185 and the grid point interpolation processing unit 183.

  The lattice point interpolation processing device 183 interpolates with the DR, DG, DB of the lattice point selection device 182 from the C, M, Y, K values at the four lattice points of the tetrahedron to be interpolated from the data cutout device 186, Obtain C, M, Y, K data. The color conversion table memory 184 stores the grid point information in the format shown in FIG. 34 described later, and the grid point address generation device 185 receives the address and transfers the grid point information to the data cutout device 186. FIG. 35 shows the format of each grid point data.

  The grid point address generation device 185 uses the HR, G, B and HRU, GU, BU, and TYPE from the grid point selection device 182 and the pixel attribute from the pixel attribute generation device 132 (see FIG. 14), and the color conversion table memory 184. Find the grid point address. The data cutout device 186 cuts out four parameters for interpolating the lattice point data received from the color conversion table memory 184 by the lattice point interpolation processing device 183.

  FIG. 26 is a flowchart showing the operation of the color conversion processing device 128 of FIG. First, the image (RGB) data input by the lattice point selection device 182 is converted from upper NBIT to HR, G, B and lower (8-N) BIT to DR, G, B (step S21). Subsequently, TYPE is obtained from the obtained HR, G, B by the lattice point selection device 182 (step S22). Further, a lattice point address is obtained by the lattice point address generation device 185 (step S23). Subsequently, the grid point data is read from the color conversion table memory 184 (step S24), and the grid point interpolation processor 183 performs an interpolation process between the grid point data to obtain C, M, Y, K data (step S25).

  FIG. 27 is a block diagram showing a configuration of the lattice point selection device 182 in FIG. The lattice point selection device 182 executes steps S61 to S74 as shown in the flowchart of FIG.

  FIG. 28 is a block diagram showing the configuration of the lattice point interpolation processing device 183 in FIG. This lattice point interpolation processing device 183 includes a difference data generation device 186 that generates difference data based on the values of C, M, Y, K, and TYPE of the four lattice points in the tetrahedron to be interpolated from the color conversion table memory 184. And an interpolation device 187 for performing interpolation processing from the difference data obtained by the difference data generation device 186 and the DR, G, B data from the grid point selection device 182.

  29A to 29B are block diagrams illustrating the configuration of the interpolating device 187 in FIG. 28, which are divided into C, M, Y, and K blocks. This interpolation device 187 includes multipliers 191 to 193 and adders 194 to 196 that perform C color interpolation processing, multipliers 197 to 199 that perform M color interpolation, and adders 200 to 202, and Y color interpolation. Multipliers 204 to 206 to be performed, adders 207 to 209, multipliers 210 to 212 to perform K color interpolation, and adders 213 to 215 are provided.

  In these figures, multipliers 191 to 193 multiply the DR, G, B data from the lattice point selection device 182 and the lattice point differences 1, 2, 3C of the difference data, respectively. Adders 194 to 196 add the multiplication results of multipliers 191 to 193 and grid point data 00C. Multipliers 197 to 199 multiply the DR, G, B data from the grid point selection device 182 by the grid point differences 1, 2, 3M of the difference data, respectively. Adders 200 to 202 add the multiplication results of multipliers 197 to 199 and grid point data 00M. Multipliers 204 to 206 multiply the DR, G, B data from the grid point selection device 182 and the grid point differences 1, 2, 3Y of the difference data, respectively. Adders 207 to 209 add the multiplication results of multipliers 204 to 206 and grid point data 00Y. Multipliers 210 to 212 multiply the DR, G, B data from the grid point selection device 182 by the grid point differences 1, 2, 3K of the difference data, respectively. Adders 213 to 215 add the multiplication results of multipliers 210 to 212 and lattice point data 00K.

  30-1 to 30-2 are flowcharts illustrating the processing of the difference data generation device 186 in FIG. In the processing of the difference data generation device 186, TIPE 1 to 6 are determined according to the tetrahedron case and the list of interpolation coefficients shown in Table 1 above, and the calculation for each TYPE is executed. That is, grid point data is input (step S31), and in the case of TYPE4 (step S32, determination Yes), steps S33, S34, and S35 are executed. In the case of TYPE3 (step S36, determination Yes), steps S37, S38, and S39 are executed. In the case of TYPE2 (step S40, determination Yes), steps S41, S42, and S43 are executed. In the case of TYPE1 (step S44, determination Yes), steps S45, S46, and S47 are executed. In the case of TYPE 6 (step S48, determination Yes), steps S49, S50, and S51 are executed. In the case of TYPE5 (step S52, determination Yes), steps S53, S54, and S55 are executed.

  FIG. 32 is a block diagram showing a configuration of the lattice point address generation device 185 in FIG. The lattice point address generation device 185 includes multipliers 216 and 217, adders 218 and 219, multipliers 220, 222, and 224, a MUX (multiplexer) 221, and a color conversion table address storage device 223.

  The lattice point address generation device 185 creates an address in a data format as shown in FIG. In this example, since HR, G, and B are examples of 4 BITs, the multipliers 216, 217, and adders 218, 219 perform processing for creating 12 BITs that connect HR, G, and B. Multiplier 220 multiplies 8 words in one block of the data format shown in FIG. The MUX 221 outputs “0” when reading the 0th P0 and P7, which are data common to each type in FIG. 35, and selects “TYPE” when accessing each type. The color conversion table address storage device 223 is a storage device that stores the start address of the color conversion table shown in FIG. 34 for each FLAG color conversion table number. The adder 224 generates an address of the color conversion table shown in FIG.

  FIG. 33 is a block diagram showing the configuration of the data cutout device 186 in FIG. This data cutout device 186 includes registers 225 to 228, receives grid point data as shown in FIG. 35 from the color conversion table as shown in FIG. 34, and outputs it by separating it for each of C, M, Y, and K. To do.

  FIG. 36 is a block diagram showing the configuration of the gradation processing device 129 in FIG. The gradation processing device 129 includes a graphics threshold table storage device 230, a photo threshold table storage device 231, a character threshold table storage device 232, a table threshold matrix storage device address generation device 233, MUX (multiplexer) 234, comparison devices 235 to 238, fixed length data generation devices 239 to 243 for C, M, Y, and K, buffers 244 to 247 for C, M, Y, and K, MUX (multiplexer) 248, A controller 249 is provided.

  The threshold matrix storage device address generation device 233 generates addresses for the graphics threshold table storage device 230, the photo threshold table storage device 231, and the character threshold table storage device 232. The MUX 234 selects the output of each threshold table storage device based on the attribute data from the delay buffer 131 shown in FIG. The comparison devices 235 to 238 compare the threshold C, M, Y, K data selected by the MUX 234 with the C, M, Y, K data from the color conversion processing device 128 and generate binary data. The fixed length data generation devices 239 to 243 for each of C, M, Y, and K collect the binary data generated by the comparison devices 235 to 238 into a fixed length. The buffers 244 to 247 for each of C, M, Y, and K are configured by FIFO (First-In First-Out), and are fixed-length by the fixed-length data generators 239 to 243 for each of C, M, Y, and K. Data is received and accumulated in the FIFO.

  FIG. 37 is a flowchart showing the operation of the gradation processing device 129 in FIG. This operation is executed by the controller 249. First, the threshold matrix storage device address generation device 233 obtains the address of the horizontal threshold matrix (step S81), and further obtains the address in the horizontal matrix (step S82). Subsequently, threshold value (C, M, Y, K) data is read (step S83), and the threshold value (C, M, Y, K) data is compared with the C, M, Y, K data. 235 to 238 (step S84), and binarized (C, M, Y, K) data is added to the fixed length data (step S85). Subsequently, it is determined whether or not the data has grown to a fixed length (step S86). If the data has grown, the fixed length data of C, M, Y, and K is buffered for each C, M, Y, and K (FIFO). ) Write to 244 to 247 (step S87). If the data has not grown to the fixed length in step S86, or after executing step S87, it is further determined whether or not all of the data has been completed in the horizontal direction (step S88). It is determined whether or not all have been completed (step S89). If all the horizontal and vertical directions have been completed, this operation is terminated. If all have not been completed, the process returns to step S81.

  FIG. 38 is a block diagram showing a configuration of fixed-length data generation devices 239 to 243 for each of C, M, Y, and K in FIG. Each of the fixed-length data generation devices 239 to 243 includes a shifter 250, an OR device 251, registers 252 and 253, an adder 254, and a shift value register 255.

  The shifter 250 receives the binary data from the comparison device 235 (˜238), shifts it by the value of the shift value register 2556, and transfers it to the OR device 251. The OR device 251 performs OR processing on the shifted binary data and sends it to the register 252. The register 253 stores the added binary data that is ORed by the OR device 251. The register 252 stores data that has reached a fixed length. The adder 254 adds “1” every time binary data is received from the comparison device 235 (˜238). The register 255 stores the shift value.

  FIG. 39 is a block diagram showing the configuration of the encoding device 111 in FIG. The encoding device 111 includes a memory controller I / F 260, a BUF (buffer) 261, a JBIG encoding device 262, a BUF (buffer) 263, a memory address generation device 264, and a controller 265.

  The memory controller I / F 260 receives the image data from the memory controller 103, transfers it to the JBIG encoding device 262, receives the encoded data from the JBIG encoding device 262, and transfers it to the memory controller 103. Also, the address is received from the memory address generation device 264 and transferred to the memory controller 103. The BUF 261 temporarily stores the image data received from the memory controller I / F 103. The JBIG encoding device 262 sequentially encodes from the binary band memory area of each version and creates a code for each band. The BUF 263 temporarily stores the code data received from the JBIG encoding device 262. The memory address generation device 264 generates the address of the binary band memory area of each version in the main memory 104 and the address of the code page memory of each version. The controller 265 controls the entire encoding device.

  FIG. 40 is a block diagram showing the configuration of the C version decoding processing device 112C in FIG. This configuration is the same in other versions. The C version decoding processing device 112C includes a memory controller I / F 266, a BUF (buffer) 267, a JBIG decoding device 268, a C version line memory 269, a read memory address generation device 270, and a controller 271.

  The memory controller I / F 266 receives the image after gradation processing from the C-page code page memory area, and transfers the image to the buffer of the JBIG decoding apparatus. The BUF (buffer) 267 transfers the code data to the JBIG decoding device 268. The JBIG decoding device 268 reads and decodes the code from the code page memory area of the main memory 104 and transfers the code to the C plane line memory 269. The C plane line memory 269 stores the gradation-processed pixels decoded by the JBIG decoding device 260. The read memory address generation device 270 generates an address of a code page memory area in the C version of the main memory 104. The controller 271 controls the entire C decoding processing device 112C.

  Therefore, according to the image processing apparatus (method) of the embodiment described above, it is determined in real time whether a plurality of different areas are included in each area for each pixel to be processed in units of bands or pages. Select the color conversion table according to the result, perform color conversion processing, and select the threshold matrix to perform gradation processing, thereby requiring an attribute memory to store attributes for each pixel of the image band and page Instead, only the rectangular area indicating the character and graphics area has only the BIT indicating whether the pixel in the area is the target of the attribute, so the memory capacity is reduced. In addition, since color conversion processing and gradation processing for each photographic image and graphics image can be switched, the color reproducibility is excellent, and each pixel of the character is also attributed as a character in the character inside the photographic image. Therefore, color reproducibility is improved.

  By the way, the image processing method (operation) described so far can be programmed, recorded on a computer-readable recording medium, and executed on the computer. Further, a part of the image processing method can be provided on a network and realized through a communication line.

  That is, the image processing method described in this embodiment is realized by executing a program prepared in advance on a computer (CPU 30) such as a personal computer or a workstation as shown in FIG. This program is operated by a computer such as a memory 31, a hard disk 34, a flexible disk 37, a CD-ROM (Compact-Disc Read Only Memory) 36, an MO (Magneto Optical), a DVD (Digital Versatile Disc) by operating the keyboard 35. The program is recorded on a readable recording medium, read from the recording medium by a computer (CPU 30), and displayed on the display device 33 as necessary. In addition, data of this image processing method can be transmitted and received from the communication device 32 to an external device as necessary.

  Further, as shown in FIG. 42, this program can be distributed to devices 41 to 43 such as a personal computer via the recording medium via a network such as the Internet 30.

  That is, this program can be provided in a state of being installed in advance on a hard disk as a recording medium built in the computer, for example. The program can be temporarily or permanently stored in a recording medium, and can be provided as packaged software by being incorporated in a computer as a unit or being used as a removable recording medium.

  As the recording medium, for example, a flexible disk, a CD-ROM, an MO disk, a DVD, a magnetic disk, a semiconductor memory, and the like can be used.

  The program can be transferred from a download site to a computer wired or wirelessly via a network such as a LAN (Local Area Network) or the Internet, and downloaded to a storage device such as a built-in hard disk in the computer. .

  As described above, the image processing apparatus and the image processing method according to the present invention, and the computer-readable recording medium recording the program for causing the computer to execute the image processing method have different pixel values expressed in a predetermined color space. This is useful for image processing that converts pixel values expressed in a color space, and is particularly suitable for image processing systems such as image forming apparatuses such as color printers and color copying machines.

It is explanatory drawing which shows the example of an image of the image process concerning embodiment of this invention. It is explanatory drawing which shows the example of an attribute of each area | region of the band in FIG. It is explanatory drawing which shows the image of the multi-value band memory area | region in FIG. It is explanatory drawing which shows the data of the FLAGBIT memory corresponding to each area | region of the band in FIG. 3 is an explanatory diagram illustrating a configuration example of a mechanism unit of the image forming apparatus according to the embodiment of the present invention. FIG. 6 is a block diagram illustrating a configuration of an electrical / control system of the image forming apparatus in FIG. 5. It is a block diagram which shows the schematic processing system of the image data concerning embodiment of this invention. It is a functional block diagram which processes the image data concerning embodiment of this invention. It is explanatory drawing which shows the format of the main memory in FIG. It is a block diagram which shows the mode of the production | generation of the multi-value band data concerning embodiment of this invention. It is a block diagram which shows the mode of the image processing concerning embodiment of this invention. It is a block diagram which shows the mode of the encoding process concerning embodiment of this invention. It is a block diagram which shows the mode of the print output process concerning embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus concerning embodiment of this invention. It is a block diagram which shows the structure of the pixel attribute production | generation apparatus of the image processing apparatus in FIG. It is a flowchart which shows operation | movement of the pixel attribute production | generation apparatus of FIG. It is a block diagram which shows the structure of the square information storage device in FIG. It is a block diagram which shows the structure of the area | region determination apparatus in FIG. It is a block diagram which shows the structure of the square basin determination processing apparatus in FIG. It is a block diagram which shows the structure of the priority determination apparatus in FIG. FIG. 19 is a block diagram illustrating a configuration of the pixel attribute determination device in FIG. 18. It is a block diagram which shows the structure of the FLAGBIT address generation apparatus in FIG. It is explanatory drawing which shows the calculation method of a FLAGBIT address. It is a block diagram which shows the structure of the FLAGBIT address processing apparatus in FIG. It is a block diagram which shows the structure of the color conversion processing apparatus in FIG. It is a flowchart which shows operation | movement of the color conversion processing apparatus of FIG. It is a block diagram which shows the structure of the lattice point selection apparatus in FIG. It is a block diagram which shows the structure of the lattice point interpolation processing apparatus in FIG. It is a block diagram which shows the structure of the interpolation apparatus (C, M) in FIG. It is a block diagram which shows the structure of the interpolation apparatus (Y, K) in FIG. It is a flowchart which shows the process (1) of the difference data generation apparatus in FIG. It is a flowchart which shows the process (2) of the difference data generation apparatus in FIG. It is a flowchart which shows operation | movement of the lattice point selection apparatus in FIG. It is a block diagram which shows the structure of the lattice point address generation apparatus in FIG. It is a block diagram which shows the structure of the data cut-out apparatus in FIG. It is explanatory drawing which shows the data format of a color conversion table memory. It is explanatory drawing which shows a lattice point data format. It is a block diagram which shows the structure of the gradation processing apparatus in FIG. It is a flowchart which shows operation | movement of the gradation processing apparatus in FIG. It is a block diagram which shows the structure of the fixed length data generation apparatus for every C, M, Y, K in FIG. It is a block diagram which shows the structure of the encoding apparatus in FIG. It is a block diagram which shows the structure of the C version decoding processing apparatus in FIG. It is a block diagram which shows the example which makes a computer perform the image processing method concerning embodiment of this invention. It is a block diagram which shows the example which downloads and performs the image processing method concerning embodiment of this invention from a network. It is explanatory drawing which shows the example of the color space divided into 16 by upper 4BIT. It is explanatory drawing which shows the division | segmentation form to the tetrahedron in FIG. It is a block diagram which shows the structure of the conventional image processing apparatus.

Explanation of symbols

100 color printer 101 CPU
DESCRIPTION OF SYMBOLS 103 Memory controller 104 Main memory 104a Multi-valued band memory area 104b FLAGBIT memory area 110 Image processing apparatus 111 Coding apparatus 112 Decoding processing apparatus 113 Engine controller 114 Printer engine 128 Color conversion apparatus 129 Gradation processing apparatus 132 Pixel attribute generation apparatus 135 Horizontal Pixel counting device 136 Vertical prime counting device 137 Square information storage device 138 Area determination device 139 FLAGBIT address generation device 150, 151, 152 Square region determination processing device 153 Priority determination device 154 Pixel attribute determination device 184 Color conversion table memory 230 Graphic Threshold table storage device 231 Photo threshold table storage device 232 Character threshold table storage device 233 Trix memory address generator 234 MUX (multiplexer)

Claims (14)

In an image processing apparatus that inputs image information including photographs, graphics, characters, etc., and executes predetermined image processing on the image information.
Drawing means for generating multi-value band data from the image information;
Multi-value band data storage means for storing the multi-value band data;
Image processing means for determining a plurality of attributes constituting the image information from the multi-value band data stored in the multi-value band data storage means, and performing image processing for each attribute;
An image processing apparatus comprising:   The image processing apparatus according to claim 1, wherein the image processing unit includes a pixel attribute generation unit configured to generate an attribute of a pixel being processed from attribute information of a plurality of rectangular regions.   The image processing apparatus according to claim 1, wherein the image processing means includes flag information storage means for storing flag information indicating presence / absence of an attribute target for each pixel in a square area. The pixel attribute generation means includes
Square area attribute information storage means for storing attribute information of a plurality of square areas;
Area determination means for determining whether the pixel being processed is included in a plurality of rectangular areas set for each band;
The image processing apparatus according to claim 2, further comprising:   The pixel attribute generation means includes flag information address generation means for obtaining an address of the flag information storage means from a plurality of area information obtained by the square area attribute information storage means and the coordinates of the processing pixel. The image processing apparatus according to claim 4. The rectangular area attribute information storage means includes
Coordinate storage means for storing coordinate values indicating a plurality of rectangular regions;
Effective number storage means for storing the number of a plurality of rectangular regions stored in the coordinate storage means;
The image processing apparatus according to claim 4, further comprising:   The image processing apparatus according to claim 4, wherein the square area attribute information storage unit stores a priority in a case where square areas having a plurality of attributes overlap.   The image processing apparatus according to claim 4, wherein the square area attribute information storage unit stores a frame type indicating whether the square area having a plurality of attributes is a flag indicating an attribute object for each pixel. .   The image processing apparatus according to claim 1, wherein the image processing unit further includes a color conversion table storage unit that stores a color conversion table for a plurality of square regions having different attributes.   The image processing apparatus according to claim 9, wherein the image processing unit selects a different color conversion table for each of a plurality of rectangular regions in which pixels being processed are set for each band.   The image processing apparatus according to claim 1, wherein the image processing unit further includes a threshold value table storage unit that stores a threshold value table for a plurality of square regions having different attributes.   The image processing apparatus according to claim 11, wherein the image processing unit selects a different threshold value table for each of a plurality of rectangular regions in which pixels being processed are set for each band. In an image processing method for inputting image information including photographs, graphics, characters, etc., and executing predetermined image processing on the image information,
A drawing step of generating multi-value band data from the image information;
A multi-value band data storage step for storing the multi-value band data;
An image processing step of determining a plurality of attributes constituting the image information from the multi-value band data stored in the multi-value band data storage means, and performing image processing for each attribute;
An image processing method comprising:   A computer-readable recording medium having recorded thereon a program for causing a computer to execute the image processing method according to claim 13.

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