JP2007208392A - Asynchronous digital wireless communication method and system thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology whereby consecutiveness of received voice data is maintained even when a receiver side reaches an underflow state or an overflow state so as to achieve a complete free run state (asynchronous state) between a transmitter side and the receiver side. <P>SOLUTION: In an asynchronous digital wireless communication method wherein the transmitter includes digital voice data to a packet with a prescribed time length and transmits repetitively the data in the unit of the packet, the receiver 200 stores once the voice data to a memory 213 and gives the data to a D/A converter 215 to obtain a drive signal for a voice reproducing unit, the receiver 200 includes a control means 220 that monitors a data storage state of the memory 213, slows down a reception processing time Tr by a prescribed time when the memory 213 reaches an underflow state, and quickens the reception processing time Tr by a prescribed time when the memory 213 reaches an overflow state, wherein the Tr is the reception processing time per one packet at the receiver 200. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an asynchronous digital radio communication system, and more particularly to a real-time voice radio transmission technology capable of one-way communication suitable for a digital wireless microphone system.

  First, FIG. 17 shows an outline of a transmission / reception system (in the case of a superheterodyne system) that wirelessly transmits digital audio data such as radio waves and light, and this will be described.

  On the transmitter 10 side in FIG. 17A, an analog audio signal output from the microphone 11 is converted into a digital audio signal by the A / D converter 12, and data compression processing is performed by the encoder 13 at the next stage. After performing enhancement effect processing, error correction coding processing, and the like, the modulation unit 14 performs modulation processing, frequency conversion, and the like to transmit from the antenna. When the audio signal source itself is a digital output type such as a CD player, the digital audio signal is directly input to the encoder 13. Also, light may be used as a transmission medium.

  On the receiver 20 side in FIG. 17B, the demodulator 21 converts the frequency of the received signal received by the antenna and demodulates it, and the decoder 22 at the next stage performs expansion processing and the like. The digital audio signal is obtained and converted to an analog signal by the D / A converter 23 to obtain a driving signal for the speaker 24.

  In such a wireless transmission / reception system, the transmitter 10 and the receiver 20 usually each have an internal system clock as an operation reference, and based on the clock, an A / D conversion rate, a D / A conversion rate, and the like. Although the write timing to the memory is controlled, it is practically impossible to make the clock frequencies completely coincide between the transmitter 10 and the receiver 20. Even with a highly accurate clock generator, the clock frequency will gradually vary over time.

  Therefore, for example, in a digital wireless microphone system, when digital audio signals are continuously transmitted in real time asynchronously over a long period of time, data excess or deficiency may occur on the receiver 20 side due to different clock frequencies. is there.

  That is, when the A / D conversion clock frequency on the transmitter 10 side is higher than the D / A conversion clock frequency on the receiver 20 side, an overflow state occurs in which data overflows on the receiver 20 side. When the A / D conversion clock frequency is lower than the D / A conversion clock frequency on the receiver 20 side, an underflow state that causes data shortage on the receiver 20 side occurs. In such a state, in the microphone system, a fatal problem that the sound output from the speaker 24 is temporarily skipped or interrupted occurs.

  In order to solve this point, for example, in the invention described in Patent Document 1, when the transmitter side performs A / D conversion on the audio signal and temporarily stores it in the buffer memory, the amount of data stored in the buffer memory The data compression rate is made variable according to (for example, a threshold value that is a criterion for determination of overflow), and the compression rate is added to the audio data as auxiliary data for transmission. Judgment is made to perform extension processing. If overflow cannot be avoided even by the data compression rate, the buffer memory is cleared and an empty packet is transmitted.

  In order to prevent the above-mentioned sound interruption, in the invention described in Patent Document 2, audio data is transmitted as uncompressed packets from the transmitter, and the D / A conversion clock frequency fr is set on the transmitter side on the receiver side. The A / D conversion clock frequency ft of the A / D conversion is intentionally created to create an underflow state, and the voice data in the packet sent from the transmitter is alternately stored in the two memory banks, and then the D / A When alternately outputting to the converter, if one memory bank is underflowed, the audio data of the other memory bank is held in a register until the underflow state of one memory bank is resolved The held data is output to the D / A converter.

JP 2002-268691 A JP 2004-349929 A

  According to the above-mentioned Patent Document 1, asynchronous one-way communication can be performed. However, since the audio data is compressed on the transmitter side, the delay time is increased to, for example, about 10 mS, and the performance stage, etc. It is not preferable for real-time voice transmission required for a microphone system applied to the above.

  In addition, since the size of the microphone as a transmitter is limited, it is not only difficult to design a data compression circuit in a limited space, but also a problem in miniaturization. become. Furthermore, since the power consumption in the transmission circuit is increased by providing the data compression circuit, it is not preferable for the wireless microphone that requires a built-in battery for the power supply because the battery replacement time is shortened.

  Further, according to Patent Document 2, the system clock frequency on the receiver side is set higher than the system clock frequency on the transmitter side to intentionally create a state in which the receiver side periodically underflows. When the flow state is reached, for example, the last one packet of audio data is held in the register and supplied to the D / A converter, so that sound interruption can be prevented. Further, since the audio data is not compressed, the delay time can be shortened.

  However, in the case of the above-mentioned Patent Document 2, as an initial setting, there is an inconvenience that the system clock frequency on the receiver side must be set faster than the system clock frequency on the transmitter side. A crystal oscillator is usually used as the clock generator, but the crystal oscillator causes a slight frequency change due to a temperature change or a change with time.

  Therefore, even if the above initial settings are made, the system clock frequency on the transmitter side may exceed the system clock frequency on the receiver side over a long period of use. As a result, data loss occurs.

  Therefore, an object of the present invention is to receive received audio data regardless of whether the receiver side is in an underflow state or an overflow state due to the difference between the system clock frequency on the transmitter side and the system clock frequency on the receiver side. Is to achieve a complete free run (asynchronous state) between the transmitter side and the receiver side.

  In order to solve the above-described problem, the invention described in claim 1 includes a transmitter and a receiver that are communicated by radio, and includes digital voice data from the transmitter in a packet having a predetermined time length. Asynchronous digital wireless communication method in which the receiver side repeatedly stores the audio data in the memory and then gives the D / A converter to the D / A converter to obtain a drive signal for the audio player. And a control means for monitoring the data storage state of the memory, wherein the reception processing time per packet on the receiver side is Tr, and the reception processing time when the memory is in an underflow state Tr is delayed by a predetermined time, and when the memory is overflowed, the reception processing time Tr is increased by a predetermined time. That.

  According to a second aspect of the present invention, in the first aspect, the receiver is configured to delay the phase at the same frequency as the master clock generated by the clock generator as a system clock serving as an operation reference of the receiver. A plurality of shifted first clocks and a plurality of second clocks whose frequency and phase or phase are faster than those of the master clock. In the case of the underflow state, the first clock is appropriately switched, and the overflow state is In this case, the second clock is switched as appropriate.

  In order to solve the above problem, the invention described in claim 3 includes a transmitter and a receiver that are communicated by radio, and transmits an audio signal as digital audio data from the transmitter. In the asynchronous digital radio communication system, which demodulates the audio data on the side and performs D / A conversion to obtain a drive signal for the audio player, the transmitter includes the audio data in a packet having a predetermined time length. The receiver repeatedly transmits in units, and the receiver has a storage capacity for a predetermined number of packets, stores a memory for storing the demodulated audio data, and converts the audio data read from the memory into an analog signal D / A converter, a clock output means for outputting a system clock as an operation reference of the receiver, and writing / reading of the audio data to / from the memory And control means for controlling the clock output means and monitoring the data storage state of the memory, wherein the control means is in an underflow state when the audio data is written to or read from the memory. In this case, a system clock that delays the reception processing time Tr of the receiver by a predetermined time is output from the clock output unit, and when the memory is in an overflow state, the reception processing time is output from the clock output unit. A system clock for increasing Tr by a predetermined time is output.

  According to a fourth aspect of the present invention, in the third aspect, the clock output means has the same frequency as the master clock generated by the clock generator when the memory is underflowed as the system clock. When the first clock with the phase shifted in the delay direction is output, and the memory is in an overflow state, a second clock whose frequency and phase or phase is faster than the master clock is output.

  According to a fifth aspect of the present invention, in the fourth aspect, the clock output means creates the second clock using the first clock as a master clock.

  According to a sixth aspect of the present invention, in the third, fourth, or fifth aspect, the memory includes at least two first and second memory banks that store the audio data. The audio data is written alternately.

  According to the first aspect of the present invention, the data storage state of the memory is monitored by the control means on the receiver side, and when the memory is in an underflow state, reception per packet on the receiver side is performed. If the processing time Tr is delayed by a predetermined time and the memory is in an overflow state, the reception processing time Tr is increased by a predetermined time, so that the system clock frequency on the transmitter side and the receiver side Regardless of the system clock frequency, the continuity of the received audio data is maintained regardless of whether the receiver side is underflowed or overflowed. Therefore, the transmitter side and the receiver side are completely Free run, that is, initial setting of the system clock frequency between the transmitter side and the receiver side is unnecessary, and the system can be operated asynchronously.

  In delaying or speeding up the reception processing time Tr on the receiver side by a predetermined time, according to the second aspect of the present invention, a predetermined delay time with respect to the reception processing time Tr can be obtained by simply switching the first clock or the second clock. The shortening time can be set easily.

  According to the third aspect of the present invention, when the memory is in an underflow state when audio data is written to or read from the memory, the reception processing time Tr of the receiver is delayed by a predetermined time from the clock output means. 2. The system clock according to claim 1, wherein when the system clock is output and the memory is in an overflow state, the clock output means outputs a system clock that increases the reception processing time Tr by a predetermined time. Similar to the invention, due to the difference between the system clock frequency on the transmitter side and the system clock frequency on the receiver side, the continuity of the received audio data is maintained regardless of whether the receiver side is in an underflow state or an overflow state. So that a complete free run can be achieved on the transmitter side and the receiver side .

  According to the fourth aspect of the present invention, when the memory is underflowed as the system clock by the clock output means, the phase is shifted in the delay direction at the same frequency as the master clock generated by the clock generator. When the first clock is output and the memory is in an overflow state, the second clock is output in which only the frequency and phase or phase is faster than the master clock. The predetermined delay time and shortening time can be easily set for the reception processing time Tr.

  According to the fifth aspect of the present invention, the clock output means generates the second clock using the first clock as the master clock, so that the first clock can be generated in a normal operation that is neither an underflow state nor an overflow state. Either the clock or the second clock can be used as the system clock.

  According to the sixth aspect of the present invention, the first and second memory banks are provided as the voice data memory, and the voice data is alternately written in each memory bank. Thus, the voice data can be processed efficiently.

  Next, an embodiment in which the present invention is applied to a wireless microphone system will be described with reference to FIGS. FIG. 1 is a circuit block diagram schematically showing a configuration of a transmitter 100 provided in the present invention, and FIG. 2 is a circuit block diagram schematically showing a configuration of a receiver 200.

  As shown in FIG. 1, the transmitter 100 includes a microphone 110, an A / D converter 120, an encoder 130, a buffer memory 140, a transmission processing unit 150, a clock generator 160, and a control circuit 170. . For convenience of explanation, FIG. 1 shows that each component after the A / D converter 120 is connected to the microphone 110, but in reality, each component after the A / D converter 120 is Built in the microphone 110.

  The microphone 110 may be either an electrostatic type or an electrodynamic type. However, since the microphone 110 is wireless, it is a microphone with a built-in battery as a power source. The A / D converter 120 converts an analog audio signal output from the microphone unit of the microphone 110 into digital audio data. The A / D converter 120 operates based on a system clock (a reference clock signal that governs operation) from the clock generator 160. In this example, the sampling rate (A / D conversion clock frequency) is 48 KHz, The number of quantization bits is 24 bits per sample.

  The A / D converted speech data is converted into a code pulse composed of a combination of presence / absence of a pulse by the encoder 130 and subjected to, for example, enhancement effect processing (enhancement processing) or error correction coding processing. At least compression processing is not performed. The audio data processed by the encoder 130 is temporarily stored in the buffer memory 140 and then sequentially transmitted to the transmission processing unit 150 by a FIFO method (first-in first-out method).

  The transmission processing unit 150 corresponds to the modulation unit 14 described in the conventional example of FIG. 17 and transmits the audio data from the antenna after performing modulation processing or frequency conversion. However, in the present invention, the audio data is time-divided into one unit. Audio data is transmitted on a packet-by-packet basis. The transmission medium may be either radio waves or light.

  In this example, one packet length is 2 mS (milliseconds). Therefore, one packet contains 2 mS ÷ 1/48 KHz = 96 samples, and the transmitter 100 repeatedly transmits voice data as one packet 96 samples. Is done. FIG. 3 shows a flowchart of a transmission procedure executed by the transmitter 100.

  Based on the system clock from the clock generator 160, the control circuit 170 controls encoding processing of the audio data by the encoder 130, writing / reading of audio data to / from the buffer memory 140, and packet transmission of the transmission processing unit 150. .

  As shown in FIG. 2, the receiver 200 includes a demodulation unit 210 that demodulates a reception signal received by an antenna (a light receiver in the case of optical communication). The demodulator 210 corresponds to the demodulator 21 described in the conventional example of FIG. 17, performs frequency conversion on the received signal, performs demodulation processing, and stores it in the first memory (buffer memory) 211 at the next stage.

  The received signal stored in the first memory 211 is returned to the original audio data in units of packets by the decoding process of the decoder 212 and then accumulated in the second memory 213 in the next stage. Note that the order of the first memory 211 and the decoder 212 may be switched. That is, the received signal may be first decoded and stored in the first memory 211.

  In this example, the second memory 213 includes two storage units BANK (memory bank) 1 and BANK 2, and voice data is alternately stored in BANKs 1 and 2 in units of packets so that data continuity is not lost. Is done.

  For example, if audio data included in odd-numbered packets is stored in BANK1, audio data (both 96 samples) included in even-numbered packets is stored in BANK2. The distribution of data to BANK 1 and 2 is controlled by a control circuit (control means) 220.

  The storage capacities of BANK 1 and 2 and the first memory 211 may be arbitrarily determined so that a predetermined number of packets can be stored. However, in order to complete underflow processing and overflow processing in a short time, BANK 1 and 2 Each of the storage capacities of the first memory 211 is preferably a storage capacity for one packet.

  A BANK selector (memory bank selector) 214 is connected to the output stages of BANK 1 and 2, and BANK 1 and 2 are alternately connected to the D / A converter 215 by the BANK selector 214. The BANK selector 214 is controlled by the control circuit 220, and the audio data read from each of the BANKs 1 and 2 is converted into an analog signal by the D / A converter 215 and applied to a speaker 216 as an audio player.

  The receiver 200 includes a clock generator 230 that generates a basic master clock, an underflow processing circuit 240 that generates a fast clock that is used for underflow processing from the master clock, and an overflow processing that uses the first clock as a master clock. An overflow processing circuit 250 that generates a second clock to be used and a system clock selection circuit 260 that selects either the first clock or the second clock as a system clock are provided.

  The underflow processing circuit 240 selects a first clock from the phase shift circuit 241 that creates a plurality of first clocks having phases shifted from the master clock at the same frequency in the delay direction. A first clock selector 242 for outputting is included. The first clock selector 242 is controlled by the control circuit 220.

  The overflow processing circuit 250 uses a first clock selected by the first clock selector 242 as a master clock, a phase shift and frequency multiplication circuit 251 that creates a plurality of second clocks that accelerate only the frequency and phase or phase, and a plurality of them. A second clock selector 252 that selects and outputs one second clock from the second clocks. The second clock selector 252 is also controlled by the control circuit 220.

  The system clock selection circuit 260 has a port A to which the first clock is input and a port B to which the second clock is input. The system clock selection circuit 260 selects the first clock during the underflow processing and selects the second clock for the overflow processing. Any one of the clocks is supplied to the demodulator 210, the D / A converter 215, and the control circuit 220 as the system clock of the receiver 200.

  In addition, since the second clock is created based on the first clock, in the normal state which is neither the underflow state nor the overflow state, either the first clock or the second clock may be selected as the system clock. Unlike this example, the second clock may be generated directly from the master clock of the clock generator 230.

  FIG. 4A shows a flowchart of the main routine of the control circuit 220, and FIG. 4B shows a flowchart of the subroutine. First, referring to the main routine of FIG. 4A, the audio data restored in units of packets by the decoding process of the decoder 212 is stored in BANK 1 and then D / A converted via the BANK selector 214. Is output to the device 215.

  During this time, the next audio data is stored in BANK2, and when the output of BANK1 is completed, the BANK selector 214 is switched to the BANK2 side, and the BANK2 audio data is output to the D / A converter 215.

  When storage in BANK1 is started in parallel with the output of BANK2, but when the output of BANK2 is completed, an excess or deficiency of audio data is checked in BANK1, and there is an excess or deficiency Is flagged with a check flag. Then, in the subroutine of FIG. 4B, the presence / absence of a check flag is determined, and if there is a check flag, it is determined whether it is an underflow state or an overflow state.

  In the underflow state, a predetermined fast clock is selected by the first clock selector 242 of the underflow processing circuit 240, and the first clock is supplied as a system clock via the system clock selection circuit 260. Then, the underflow process is repeatedly executed a predetermined number of times until the underflow state is resolved.

  On the other hand, in the overflow state, a predetermined second clock is selected by the second clock selector 252 of the overflow processing circuit 250, and the second clock is supplied as the system clock via the system clock selection circuit 260. Then, the overflow process is repeatedly executed a predetermined number of times until the overflow state is resolved.

  Thus, in the present invention, underflow processing and overflow processing are performed. First, when the frequency CLKr of the system clock on the receiver 200 side is higher than the frequency CLKt of the system clock on the transmitter 100 side (CLKt <CLKr ) Will be described.

  As described above, when CLKt <CLKr, the receiver 200 enters an underflow state in which data is insufficient in a predetermined cycle. At this time, the control circuit 220 performs D / A conversion on the phase of the system clock on the receiver 200 side. The underflow process is executed with a delay as long as the operation of the device 215 is not hindered.

During the underflow process, the first clock selector 242 selects the first clock as the system clock. The first clock will be described with reference to the timing chart of FIG. In this example, the phase shift circuit 241 generates the following four types of first clocks FCLK0 to FCLK270.
FCLK0; clock in phase with master clock FCLK90; clock shifted by 2π / 4 from master clock FCLK180; clock shifted by 2π / 2 from master clock FCLK270; clock shifted by 6π / 4 from master clock

  As described above, in the normal state that is neither the underflow state nor the overflow state, either the first clock or the second clock is selected as the system clock. When an underflow clock control signal is output to the 1 clock selector 242, the first clock selector 242 selects the fast clock FCLK shifted by 2π / 4 and becomes a new system clock.

  For example, assuming that the currently selected system clock is the first clock FCLK0, when the underflow clock control signal is turned ON, the system waits for the first clock FCLK0 to become “0 (Low)”, and the first clock FCLK0 is “0”. Then, when the next first clock FCLK90 becomes “0”, the first clock FCLK0 switches to the first clock FCLK90.

  When the underflow clock control signal is turned on again, the next fast clock FCLK180 is selected as the system clock in the same manner. In this way, each time the underflow clock control signal is turned ON, the first clock is cyclically switched in the order of FCLK0 → FCLK90 → FCLK180 → FCLK270 → FCLK0 →, so that the phase of the system clock is 2π / 4 each. Shifted in the delay direction.

  In a normal design, the system clock of the D / A converter 215 adopts the standard value described in the specification, but the maximum value and the minimum value are also described in addition to the standard value. There is an acceptable range. Therefore, even if the system clock is phase-shifted in the present invention, the shift amount is performed within the allowable range of the D / A converter.

  Next, details of the underflow process will be described with reference to the timing chart of FIG. FIG. 6A shows audio data transmitted from the transmitter 100 side, and FIG. 6B shows audio data received on the receiver 200 side (both are shown as analog waveforms). Since it is not necessary to compress the data on the transmitter 100 side and decompress the data on the receiver 200 side, the delay time between transmission and reception is 5 ms or less (for example, a delay unique to each component such as A / D conversion). Time is not included).

  As described above, when the frequency CLKr of the system clock on the receiver 200 side is higher than the frequency CLKt of the system clock on the transmitter 100 side (CLKt <CLKr), an underflow condition periodically occurs on the receiver 200 side. However, here, it is assumed that the frequencies of CLKt and CLKr are known.

If Tt is the transmission processing time per packet on the transmitter 100 side and Tr is the reception processing time per packet on the receiver 200 side, Tt> Tr because CLKt <CLKr. Δt1 is represented by Δt1 = Tt−Tr. Note that the transmission processing time Tt and the reception processing time Tr are expressed by the following equations.
Tt≈ (1 / CLKt) × number of clocks required for transmission processing of one packet Tr≈ (1 / CLKr) × number of clocks required for reception processing of one packet

If transmission / reception has been performed n times, the accumulated error in the processing time of the transmitter 100 and the receiver 200 is
nTt−nTr = n (Tt−Tr) = n × Δt1
Thus, if this accumulation error exceeds the allowable memory capacity of each of BANK 1 and 2, an underflow state in which data is insufficient occurs.

  The control circuit 220 monitors the accumulation error n × Δt1, and if it is determined that the accumulated error exceeds the BANK memory capacity, the first clock selector 242 cancels the accumulation error (to eliminate the underflow state). The underflow clock control signal is output to the receiver 200, and the phase of the system clock of the receiver 200 is shifted in the delay direction.

  That is, the reception processing time Tr per packet is delayed by Δt2, and the reception processing time per packet is set as Tr → Tr + Δt2 (where Δt2> Δt1). In this example, the reception processing time Tr per packet is 2 mS required to process one packet (96 samples).

  Here, if the delay time is DΔt2, the delay time DΔt2 is obtained by switching the first clocks FCLK0 to CLK270 shown in FIG. That is, for example, when the system clock is switched from FCLK0 to the next FCLK90, the phase shifts in the 1/4 delay direction, and the delay time becomes 1/4 × (CLKr).

This delay time (1/4 × (CLKr)) is the minimum delay time, and in order to obtain a predetermined delay time DΔt2 per reception processing time Tr, the system clock is cyclically changed from, for example, FCLK0 → FCLK90 → FCLK180 → FCLK270. Switch to. Accordingly, the delay time DΔt2 is expressed as m (positive integer) as the number of switching times.
DΔt2 = m × (1/4 × (CLKr))
It is represented by

  In this way, the underflow state is canceled by delaying the reception processing time Tr per packet by DΔt2, but the number M of receptions until the underflow state is canceled is obtained as follows.

Assuming that the difference between the delay time DΔt2 and the difference in processing time Δt1 between the transmitter 100 and the receiver 200 is Δt3 (= DΔt2−Δt1), the number of receptions M is the number of times Δt3 is included in the accumulated error n × Δt1. It is calculated depending on whether it is included. Therefore, the number of receptions M is
M = (n × Δt1) / Δt3
Can be obtained from After the underflow state is eliminated, the delay time DΔt2 is not added, and the reception processing time Tr is restored to the original system clock.

  The number of receptions M (underflow elimination time) can be determined by adjusting Δt3 within a range where the sound quality does not deteriorate. In the above example, the system clock is cyclically switched to set the desired delay time DΔt2. However, in some cases, the current system clock is directly changed to the system clock having the delay time DΔt2. You may jump to.

  For reference, FIG. 7A shows a sound signal waveform output from the D / A converter 215 during underflow processing (Tr = 1 / 47.9 KHz), and FIG. The audio signal waveform output from the D / A converter 215 at Tr = 1 / 48.0 KHz) is shown. As can be seen, by appropriately selecting the delay time DΔt2, the continuity of the waveform is maintained even during the underflow process, and the sound quality is not deteriorated or abnormal sounds are not detected in the sense of hearing.

Next, a system clock for obtaining the delay time DΔt2 will be described. In general, assuming that k system clocks whose phases are shifted by 2π / k can be used, the delay time DΔt2 for delaying the reception processing time Tr per packet is as described above.
DΔt2 = m × (1 / k × (CLKr)) (Formula 1)
Is required.

Further, the difference Δt1 in processing time between the transmitter 100 and the receiver 200 is
Δt1 = Tt−Tr
= Sclk × Sample × (1 / CLKt−1 / CLKr) (Expression 2)
Is replaced by
Sclk: Number of clocks required for one sampling (for example, when the system clock is 12.288 MHz and the sampling frequency is 48 KHz, 256 clocks).
Sample: Number of samplings (the number of samples subjected to one transmission / reception process, for example, 96 (2 mS)).

In order to eliminate the underflow, it is necessary that DΔt2> Δt1. From Equation 1 and Equation 2 above,
m × (1 / k × (CLKr))>
Sclk × Sample × (1 / CLKt−1 / CLKr)
To organize this,
m / k> Sclk × Sample × (CLKr / CLKt−1) (Equation 3)
It becomes.
m: The number of switching of the system clock for obtaining the delay time DΔt2.
k: the number of system clocks whose phase is shifted by 2π / k, generated by the phase shift circuit.

  The maximum phase difference of the system clock is 2π / 2 and k = 2 (however, depending on the input conditions (for example, duty ratio) of the subsequent device). The minimum phase difference is 2π / k, and the maximum value k can take depends on the difference in the system clock frequency between the transmitter 100 and the receiver 200.

For example, in order to simplify the calculation, when CLKt = 10 MHz, CLKr = 10.0001 MHz, m = 3, Sclk = 256, Sample = 96,
k <12.2
It becomes. Therefore, in the above example, the maximum value of k (positive integer) is 12, and the minimum phase difference of the system clock is 2π / 12. For this reason, in order to perform the underflow process finely, it is only necessary to increase the value of k while increasing the value of k.

  Next, changes in frequency before and after underflow processing of the audio signal converted by the D / A converter 215 will be described with reference to FIG. The left side of FIG. 8 is the waveform before the underflow process, and the right side of FIG. 8 is the waveform after the underflow process.

Before the underflow processing, if a waveform corresponding to a sine wave of Y [Hz] is generated between x [s],
x = 1 / Y (Formula 4)
Holds. On the other hand, a waveform corresponding to a sine wave of W [Hz] is generated between x + nΔx [s] by switching the system clock whose relative phase difference is Δx n times due to underflow processing. Then
x + nΔx = 1 / W (Formula 5)
Holds. Furthermore, if Z is the sampling frequency,
x = n / Z (Formula 6)
Holds.

Substituting the above (formula 4) into the above (formula 5),
1 / Y + nΔx = 1 / W
Then, when this is arranged about Y,
(1 + nYΔx) / Y = 1 / W
Therefore, the frequency W [Hz] after underflow processing is
W = Y / (YnΔx + 1) (Expression 7)
It is represented by

For example, if the frequency Y before underflow processing is 1000 Hz, the system clock switching number n is 48 times, CLKr is 12.288 MHz, 4 system clocks shifted by 2π / k, that is, k is 4, the above equation (7) )
W = Y / ((Y × n × 1/4 × (1 / CLKr)) + 1)
Yes, and substituting each numerical value shown in this example,
W ≒ 999 [Hz]
It becomes. As described above, even if underflow processing is performed, the frequency hardly changes (in this example, 1000 Hz → 999 Hz), and thus a reproduced sound with no deterioration in sound quality can be obtained.

  Next, an overflow process executed when the frequency CLKr of the system clock on the receiver 200 side is lower than the frequency CLKt of the system clock on the transmitter 100 side (CLKr <CLKt) will be described.

  In this case, the second clock SCLK shown in FIGS. 9 to 12 created by the overflow processing circuit 250 is used. First, in the first example of FIG. 9, the following four types of second clocks SCLK0 to SCLK270 are generated by the phase shift and frequency multiplication circuit 251 using the fast clock FCLK output from the underflow processing circuit 240 as a master clock.

SCLK0; clock in phase with first clock SCLK90; clock shifted by 2π / 4 from first clock SCLK180; clock shifted by 2π / 2 from first clock SCLK270; clock shifted by 6π / 4 from first clock

  Since these four types of second clocks SCLK0 to SCLK270 have the same frequency as the fast clock FCLK, the waveforms are the same as those of the first clocks FCLK0 to FCLK270 shown in FIG. 5, but the switching order is different.

  That is, when the overflow state occurs, the control circuit 220 issues an overflow clock control signal to the second clock selector 252 several times until the overflow state is resolved. As a result, as shown in FIG. The second clock is cyclically output from the second clock selector 252 in the order of SCLK 0 → SCLK 270 → SCLK 180 → SCLK 90 → SCLK 0 → and supplied as a system clock via the system clock selection circuit 260. According to this, every time an overflow clock control signal is issued, the phase of the system clock is advanced by 2π / 4, and the overflow state is eliminated.

  Note that the switching timing of the second clock SCLK is the same as that of the first clock FCLK described above. For example, when the currently selected system clock is the second clock SCLK0 and the overflow clock control signal is turned ON, the second clock SCLK0. After the second clock SCLK0 becomes “0” after the second clock SCLK270 becomes “0”, the second clock SCLK0 is switched to the second clock SCLK270 (described later). The same applies to the example).

  Next, in the second example of FIG. 10, the first clock FCLK output from the underflow processing circuit 240 is used as a master clock, and the following three types of second clocks SCLK0, SCLK45, and SCLK135 are generated by the phase shift and frequency multiplication circuit 251. create.

SCLK0: Clock in phase with the first clock SCLK45: Clock that is twice the frequency of the first clock and shifted from the rising edge of the first clock (leading edge) to the rising edge of SCLK45 by 2π / 8 SCLK135; Twice the first clock Clock with a shift of 6π / 8 from the rising edge of the first clock to the rising edge of SCLK 135 at the frequency of (this may be an inverted clock of SCLK 45)

  According to the second example, five system clocks can be output by overflow processing during an output period of four clocks (four system clock pulses) output when overflow processing is not performed. In order to realize this, the second clock SCLK is switched as follows.

  In this case, the overflow clock control signal is output from the control circuit 220 five times. However, assuming that the second clock SCLK0 is currently used as the system clock, every time the overflow clock control signal is output, SCLK0 → SCLK135 → The second clock is switched in the order of SCLK 45 → SCLK 135 → SCLK 45 → SCLK 0 →.

According to this, it is shortened by 2π / 8 by selecting SCLK135 first, then by 2π / 4 by selecting SCLK45, and then by 2π / 4 by selecting SCLK135, Next, SCLK 45 is selected to reduce by 2π / 4, and finally SCLK 0 is selected to reduce by 2π / 8. When these shortened times are added up,
2π / 8 + 2π / 4 + 2π / 4 + 2π / 4 + 2π / 8 = 2π
Thus, the system clock is shortened by one clock.

  Next, in the third example of FIG. 11, the following five types of second clocks SCLK0 to SCLK240 are created by the phase shift and frequency multiplication circuit 251 using the fast clock FCLK output from the underflow processing circuit 240 as a master clock. .

SCLK0: Clock in phase with the first clock SCLK60: Clock that is 1.5 times the frequency of the first clock and shifted by 2π / 6 from the rising edge of the first clock to the rising edge of SCLK60 SCLK120; 1.5 times the frequency of the first clock The clock SCLK180 shifted from the rising edge of the first clock to the rising edge of the SCLK 120 by 4π / 6. The frequency from the rising edge of the first clock to the rising edge of the SCLK 180 shifted by 6π / 6 at a frequency 1.5 times that of the first clock. Clock SCLK240: Clock that is 1.5 times the frequency of the first clock and shifted from the rising edge of the first clock to the rising edge of SCLK240 by 8π / 6

  According to the third example, nine system clocks can be output by the overflow process during an output period of 8 clocks (eight pulses of the system clock) output when the overflow process is not performed. In order to realize this, the second clock SCLK is switched as follows.

  In this case, the overflow clock control signal is output nine times from the control circuit 220. However, assuming that the second clock SCLK0 is currently used as the system clock, every time the overflow clock control signal is output, SCLK0 → SCLK60 → The second clock is switched in the order of SCLK 120 → SCLK 180 → SCLK 240 → SCLK 60 → SCLK 120 → SCLK 180 → SCLK 240 → SCLK 0.

According to this, by selecting SCLK 60 first, it is delayed by 2π / 6, then by selecting SCLK 120, it is shortened by 2π / 6, and then by selecting SCLK 180, it is shortened by 2π / 6, and then 2π / 6 is shortened by selecting SCLK 240, and 2π / 6 is shortened by selecting SCLK 60, and 2π / 6 is shortened by selecting SCLK 120, and then SCLK 180 is selected. Is reduced by 2π / 6, and then by selecting SCLK 240, it is shortened by 2π / 6. Although SCLK0 is finally selected, the clock cycle is not shortened at this time. Summing each of these shortened times,
-2π / 6 + 2π / 6 + 2π / 6 + 2π / 6 + 2π / 6 + 2π / 6 + 2π / 6 = 2π
Thus, the system clock is shortened by one clock.

  Next, a fourth example of FIG. 12 will be described. In the fourth example, the same five types of second clocks SCLK0, SCLK60, SCLK120, SCLK180, and SCLK240 as in the third example are used, but the switching order is different from that in the third example.

  That is, the rising timing of the overflow clock control signal output from the control circuit 220 may differ depending on the error in the system clock frequency of the transmitter 100 and the receiver 200, the memory capacity for generating the packet, and the like. Even in the case of overflow clock control signals generated at such different timings, the second clock SCLK is switched in the following order in this fourth example in order to allow the overflow processing to operate normally.

  Also in the fourth example, the overflow clock control signal is output nine times from the control circuit 220. However, if the second clock SCLK0 is currently used as the system clock, each time the overflow clock control signal is output, The second clock is switched in the order of SCLK0-> SCLK180-> SCLK240-> SCLK60-> SCLK120-> SCLK180-> SCLK240-> SCLK60-> SCLK120-> SCLK0.

  According to the fourth example, 2π / 6 is delayed by selecting SCLK 180 first, 2π / 6 is shortened by selecting SCLK 240, and 2π / 6 is shortened by selecting SCLK 60 next. Next, SCLK 120 is selected to reduce 2π / 6, SCLK 180 is selected to reduce 2π / 6, SCLK 240 is selected to reduce 2π / 6, and then SCLK 60 Is selected, 2π / 6 is shortened, and then SCLK 120 is selected to reduce 2π / 6. Although SCLK0 is finally selected, the clock cycle is not shortened at this time.

Summing each of these shortened times,
-2π / 6 + 2π / 6 + 2π / 6 + 2π / 6 + 2π / 6 + 2π / 6 + 2π / 6 = 2π
Thus, as in the third example, the system clock is shortened by one clock. Therefore, in the output period of 8 clocks (eight pulses of the system clock) output when the overflow process is not performed, 9 clocks are generated by the overflow process. System clock can be output.

Next, details of the underflow process will be described with reference to the timing chart of FIG. FIG. 13A shows audio data transmitted from the transmitter 100 side, and FIG. 13B shows audio data received on the receiver 200 side (both are shown as analog waveforms). Since it is not necessary to compress the data on the transmitter 100 side and decompress the data on the receiver 200 side, the delay time between transmission and reception is 5 ms or less (for example, a delay unique to each component such as A / D conversion). Time is not included).

  As described above, when the frequency CLKr of the system clock on the receiver 200 side is lower than the frequency CLKt of the system clock on the transmitter 100 side (CLKr <CLKt), an overflow condition periodically occurs on the receiver 200 side. However, here, it is assumed that the frequencies of CLKr and CLKt are known.

If the transmission processing time per packet on the transmitter 100 side is Tt, and the reception processing time per packet on the receiver 200 side is Tr, then Tr> Tt because CLKr <CLKt, and this difference in processing time Δt1 is represented by Δt1 = Tr−Tt. Note that the transmission processing time Tt and the reception processing time Tr are expressed by the following equations.
Tt≈ (1 / CLKt) × number of clocks required for transmission processing of one packet Tr≈ (1 / CLKr) × number of clocks required for reception processing of one packet

If transmission / reception has been performed n times, the accumulated error in the processing time of the transmitter 100 and the receiver 200 is
nTr−nTt = n (Tr−Tt) = n × Δt1
Thus, when this accumulation error exceeds the allowable memory capacity of BANKs 1 and 2, an overflow condition occurs.

  When the control circuit 220 determines that it is in an overflow state, the frequency and phase of the system clock of the receiver 200 is increased or phased, contrary to the case of the underflow state in order to cancel the accumulation error n × Δt1. Only shift forward.

  That is, the reception processing time Tr per packet is shortened by Δt2, and the reception processing time per packet is set as Tr → Tr−Δt2 (where Δt2> Δt1). In this example, the reception processing time Tr per packet is 2 mS required to process one packet (96 samples).

  Here, assuming that the shortening time is SΔt2, the shortening time SΔt2 is obtained by switching the second clock SCLK as shown in FIGS. As described above, when the second clock SCLK is switched, the system clock is normally output as n + 1 clocks where n + 1 clocks are output. Therefore, the shortened time per overflow clock control signal output is 1 / CLKr.

Therefore, when the overflow clock control signal is output m times, the shortened time SΔt2 per reception processing time Tr is
SΔt2 = m × (1 / CLKr)
It is represented by In this way, by reducing the reception processing time Tr per packet by SΔt2, the overflow state is eliminated. However, the number M of receptions until the overflow state is eliminated is obtained as follows.

If the difference between the shortened time SΔt2 and the difference in processing time Δt1 between the transmitter 100 and the receiver 200 is Δt3 (= SΔt2−Δt1), the number of receptions M is the number of times Δt3 is included in the accumulated error n × Δt1. It is calculated depending on whether it is included. Therefore, the number of receptions M is
M = (n × Δt1) / Δt3
Can be obtained from After the overflow state is eliminated, the reception processing time Tr is returned to the original system clock.

  For reference, FIG. 14A shows a sound signal waveform output from the D / A converter 215 before overflow processing (Tr = 1 / 48.0 KHz), and FIG. 14B shows the overflow processing time (Tr = The audio signal waveform output from the D / A converter 215 at 1 / 48.1 KHz) is shown. As can be seen, by properly selecting the shortening time SΔt2, the continuity of the waveform is maintained even during the overflow process, and the sound quality is not deteriorated or abnormal sounds are not detected in the sense of hearing.

Here, if the time is shortened by one clock by the overflow processing in the reception processing time Tr, the shortened time SΔt2 is as described above.
SΔt2 = m × (1 / CLKr) (Expression 8)
(M; the number of times the system clock is switched to obtain the shortening time SΔt2).

Further, the difference Δt1 in processing time between the transmitter 100 and the receiver 200 is
Δt1 = Tr−Tt
= Sclk × Sample × (1 / CLKr−1 / CLKt) (Equation 9)
It is represented by
Sclk: Number of clocks required for one sampling (for example, when the system clock is 12.288 MHz and the sampling frequency is 48 KHz, 256 clocks).
Sample: Number of samplings (the number of samples subjected to one transmission / reception process, for example, 96 (2 mS)).

In order to eliminate the overflow, the condition is that SΔt2> Δt1. From Equation 8 and Equation 9 above,
m × (1 / CLKr)>
Sclk × Sample × (1 / CLKr−1 / CLKt)
If this is expanded and organized,
m> Sclk × Sample × CLKr × (1 / CLKr−1 / CLKt)
m> Sclk × Sample × (1-CLKr / CLKt)
It becomes. For this reason, if the difference between CLKr and CLKt increases, the number of overflow processing times represented by m must be increased.

  Next, changes in frequency before and after the overflow processing of the audio signal converted by the D / A converter 215 will be described with reference to FIG. The left side of FIG. 15 is the waveform before the overflow process, and the right side of FIG. 15 is the waveform after the overflow process.

If the waveform corresponding to the sine wave of Y [Hz] was generated between x [s] before the overflow processing,
x = 1 / Y (Expression 10)
Holds. On the other hand, by switching the system clock whose relative phase difference is Δx n times for overflow processing, a waveform corresponding to a sine wave of W [Hz] is generated between x−nΔx [s]. Then,
x−nΔx = 1 / W (Expression 11)
Holds. Furthermore, if Z is the sampling frequency,
x = n / Z (Formula 12)
Holds.

Substituting the above (formula 10) into the above (formula 11),
1 / Y-nΔx = 1 / W
Then, when this is arranged about Y,
(1-nYΔx) / Y = 1 / W
Therefore, the frequency W [Hz] after overflow processing is
W = Y / (1-YnΔx) (Equation 13)
It is represented by

  In the receiver 200 shown in FIG. 2, the second memory 213 including BANK 1 and 2 is used separately from the first memory 211. However, as another embodiment, the second memory 213 is shown in FIG. The memory may be only the first memory 211 without using. In this case, the storage capacity of the first memory 211 is also preferably one packet.

  That is, while the audio signal demodulated by the demodulator 210 is sequentially written in the first memory 211, the audio signal is read out by the FIFO method in parallel with this and decoded by the decoder 212 and then the D / A converter 215. Note that the first memory 211 may be stored after the decryption process.

  In FIG. 16, the underflow processing circuit 240 and the overflow processing circuit 250 are omitted, but the control circuit 220 monitors whether data is excessive or insufficient each time the output of the first memory 211 is completed. In case of underflow, underflow processing is executed, and in case of overflow, overflow processing is executed.

  The present invention has been described above by taking the wireless microphone system as an example. However, the present invention can be widely used in asynchronous digital wireless communication systems including other transceivers, such as a time division multiple access system.

The circuit block diagram which shows typically the structure of the transmitter included in this invention. The circuit block diagram which shows typically the structure of the receiver contained in this invention. The flowchart which shows the transmission procedure of the said transmitter. In the flowchart which shows operation | movement of the said receiver, (a) is a main routine, (b) is a subroutine. The timing chart which shows an example of the system clock at the time of underflow processing. The timing chart for operation | movement description of an underflow process. The wave form diagram which shows the waveform before (b) underflow processing of the audio | voice signal by which D / A conversion was carried out, and (a) after underflow processing. The wave form diagram explaining the change state of the frequency before underflow processing and after underflow processing. The timing chart which shows the 1st example of the system clock at the time of an overflow process. The timing chart which shows the 2nd example of the system clock at the time of an overflow process. The timing chart which shows the 3rd example of the system clock at the time of an overflow process. 9 is a timing chart showing a fourth example of a system clock at the time of overflow processing. The timing chart for operation explanation of overflow processing. The wave form diagram which shows the waveform before (a) underflow process of the audio | voice signal by which D / A conversion was carried out, and (b) after underflow process. The wave form diagram explaining the change state of the frequency before overflow processing after overflow processing. The circuit block diagram which shows typically the principal part of another embodiment of the receiver contained in this invention. The typical circuit block diagram which shows each structure of (a) transmitter and (b) receiver used for the conventional digital transmission / reception system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Transmitter 110 Microphone 120 A / D converter 130 Encoder 140 Buffer memory 150 Transmission processor 160 Clock generator 170 Control circuit 200 Receiver 210 Demodulator 211 First memory 212 Decoder 213 Second memory 214 BANK selector 215 D / A converter 216 Speaker 220 Control circuit 230 Clock generator 240 Underflow processing circuit 241 Phase shift circuit 242 First clock selector 250 Overflow processing circuit 251 Phase shift and frequency multiplication circuit 252 Second clock selector 260 System clock selection circuit FCLK First clock SCLK Second clock

Claims (6)

Including a transmitter and a receiver that are communicated by radio, and from the transmitter, digital audio data is included in a packet having a predetermined time length and repeatedly transmitted in units of packets. In an asynchronous digital wireless communication method in which audio data is temporarily stored in a memory and then given to the D / A converter from the memory to obtain a drive signal for the audio player.
Control means for monitoring the data storage state of the memory, where Tr is the reception processing time per packet at the receiver side, and the reception processing time Tr when the memory is in an underflow state An asynchronous digital radio communication method characterized in that the reception processing time Tr is increased by a predetermined time when the memory is overflowed by a predetermined time delay.   The receiver has, as a system clock serving as an operation reference of the receiver, a plurality of first clocks whose phases are shifted in the delay direction at the same frequency as the master clock generated by the clock generator, and only the frequency and phase or phase. A plurality of second clocks faster than the master clock, wherein the first clock is appropriately switched in the underflow state, and the second clock is appropriately switched in the overflow state. Item 4. The asynchronous digital wireless communication method according to Item 1. Including a transmitter and a receiver communicated by radio, transmitting an audio signal as digital audio data from the transmitter, demodulating the audio data on the receiver side, performing D / A conversion, and In an asynchronous digital wireless communication system for obtaining a drive signal,
The transmitter includes the audio data in a packet having a predetermined time length and repeatedly transmits the packet unit,
The receiver has a storage capacity for a predetermined number of packets, stores a demodulated audio data, a D / A converter that converts the audio data read from the memory into an analog signal, Clock output means for outputting a system clock serving as an operation reference of the receiver, and control means for controlling writing and reading of the audio data to and from the memory and the clock output means and monitoring a data storage state of the memory Including
The control means is a system for delaying the reception processing time Tr of the receiver by a predetermined time from the clock output means when the memory is in an underflow state when the audio data is written to or read from the memory. An asynchronous digital radio communication system, characterized in that a clock is output, and when the memory is in an overflow state, a system clock is output from the clock output means to increase the reception processing time Tr by a predetermined time.   The clock output means outputs, as the system clock, a fast clock whose phase is shifted in the delay direction at the same frequency as the master clock generated by the clock generator when the memory is in an underflow state. 4. The asynchronous digital radio communication system according to claim 3, wherein when the memory is in an overflow state, a second clock having a frequency and a phase or a phase faster than that of the master clock is output.   5. The asynchronous digital radio communication system according to claim 4, wherein the clock output means creates the second clock using the first clock as a master clock.   The said memory is provided with the 1st and 2nd at least 2 memory bank which memorize | stores the said audio | voice data, The said audio | voice data are alternately written in each said memory bank, The 3, 4 or 5 characterized by the above-mentioned. Asynchronous digital wireless communication system described in 1.

Images