JP2007208198A - Impurity analysis method, and impurity analysis jig of semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an impurity analysis method and an impurity analysis jig of a semiconductor substrate having a sufficient accuracy. <P>SOLUTION: A main surface of a semiconductor substrate is masked with a protective plate having an opening in a central part, the etching liquid is spread in the opening of the protective plate, and the method comprises: a first step (S01 to S04) of etching a surface layer of the semiconductor substrate; a second step (S05 to S06) of analyzing impurity in the surface layer of the semiconductor substrate; and a third step (S07 to S10) of sandwiching the etching liquid between gaps and etching a non-etched area of the surface layer of the semiconductor substrate, wherein the first to third steps are repeated for a prescribed number of times (S11). Contamination from the non-etched area of the surface layer of the semiconductor substrate is prevented to perform impurity analysis. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an impurity analysis method for a semiconductor substrate and an impurity analysis jig.

  In the semiconductor manufacturing process, if metal impurities such as Na, K, and Fe are present in the surface layer of the semiconductor substrate or various thin film surfaces such as polysilicon formed on the semiconductor substrate, even if the amount is small, it is electrically It is well known to adversely affect properties.

  In addition, as the density and integration of devices increase, the influence of impurities on the surface of the semiconductor substrate, which is the active region, or on the surface of the superficial layer such as the surface of the polysilicon thin film formed on the semiconductor substrate becomes a problem. ing.

  In order to improve the electrical characteristics of semiconductor devices, the amount of impurities contained in the semiconductor must be accurately grasped, and the distribution in the depth direction (hereinafter referred to as impurity profile) of the amount of impurities in the extremely shallow region can be measured. By grasping, it is necessary to suppress or remove impurities from being mixed into the surface layer of the semiconductor substrate or the surface layer of the thin film such as polysilicon formed on the semiconductor substrate.

  2. Description of the Related Art Conventionally, a method is known in which a surface layer impurity amount is obtained by dissolving a surface layer of a thin film such as polysilicon formed on a semiconductor substrate and analyzing a solution in which the impurity is dissolved (for example, Patent Document 1). reference.).

  In the method for analyzing impurities such as the surface layer of a semiconductor substrate disclosed in Patent Document 1, a protective frame is tightly fixed on a semiconductor substrate placed on a base, and an object to be measured (target depth) is placed inside the frame. ) The surface layer of the semiconductor substrate is etched by filling with an etching solution for dissolution and allowing contact for a certain period of time.

  At this time, the uniformity of the in-plane depth of etching is improved by controlling the initial etching rate by gradually increasing the concentration of the fluorine-based gas in the etching solution containing the oxidizing agent.

However, the method for analyzing impurities such as the surface layer of a semiconductor substrate disclosed in Patent Document 1 is a method for determining an impurity profile by repeating etching, in which an unetched region on the surface layer of a semiconductor substrate that has not been etched due to close contact with a protective frame. There is a problem that the analysis accuracy is lowered due to the influence.
Japanese Patent Laid-Open No. 9-213688

  The present invention provides a semiconductor substrate impurity analysis method and impurity analysis jig having sufficient accuracy.

  In the impurity analysis method for a semiconductor substrate of one embodiment of the present invention, the main surface of the semiconductor substrate is masked with a protective plate having an opening in the center, the opening of the protective plate is filled with an etching solution, and the surface layer of the semiconductor substrate is formed A first step of etching, a second step of collecting the etchant and analyzing impurities in a surface layer of the semiconductor substrate, and providing a gap between the main surface of the semiconductor substrate and the protective plate; And a third step of etching an unetched region of the surface layer of the semiconductor substrate by sandwiching an etching solution in the gap, and repeating the first to third steps a predetermined number of times.

  The impurity analysis method for a semiconductor substrate according to another aspect of the present invention masks the main surface of the semiconductor substrate with a protective plate having an opening in the center, fills the opening of the protective plate with an etchant, and forms a surface layer of the semiconductor substrate. A first step of etching, a second step of collecting the etchant and analyzing impurities in a surface layer of the semiconductor substrate, and a protective plate having an opening smaller than the protective plate, And a third step of masking the etching region, and the first to third steps are repeated a predetermined number of times.

  A jig for analyzing an impurity of a semiconductor substrate according to one embodiment of the present invention includes a base on which the semiconductor substrate is placed, a plurality of protective plates that are smaller than the semiconductor substrate and have different openings at the center, and the semiconductor substrate. And means for adhering and fixing the protective plate having the opening on the main surface.

  According to the present invention, a semiconductor substrate impurity analysis method and impurity analysis jig having sufficient accuracy can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  A method for analyzing impurities in a semiconductor substrate according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a flowchart showing a method for analyzing impurities on a semiconductor substrate, FIG. 2 is a diagram showing a jig for analyzing impurities on a semiconductor substrate, FIG. 2 (a) is a perspective view thereof, and FIG. 2 (b) is along the line AA. FIG. 3 and FIG. 4 are views showing the analysis process in order.

First, an impurity analysis jig for a semiconductor substrate will be described. As shown in FIG. 2, a jig 10 for impurity analysis of a semiconductor substrate is placed on a base 12 on which a semiconductor substrate 11 is placed, and an opening 14a that is slightly smaller than the semiconductor substrate 11 at the center. And a protective plate 14.
In the case where the semiconductor substrate 11 is a silicon wafer having a diameter of 200 mm, for example, the opening 14a is suitably about 180 to 190 mm in diameter.

The base 12 has screw holes (not shown) penetrating the base 12 at the four corners, and the protective plate 14 has through holes (not shown) at positions corresponding to the screw holes of the base 12. .
By sandwiching the semiconductor substrate 11 between the base 12 and the protective plate 14 and screwing with the screw 15, the protective plate 14 is tightly fixed on the semiconductor substrate 11.

  In order to position the semiconductor substrate 11 in the base 12 and the protection plate 14, for example, countersink holes shallower than ½ of the thickness of the semiconductor substrate 11 are preferably formed.

  The material of the base 12, the protective plate 14, and the screw 15 needs to be resistant to the etching solution, and for example, a fluorine resin is suitable.

  As shown in FIG. 1, according to the semiconductor substrate impurity analysis method of the present embodiment, the semiconductor substrate 11 is first set on the base 12 (step S01), and then the semiconductor substrate is covered with the protective plate 14 having the opening 14a. 11 is masked (step S02).

  Specifically, as shown in FIG. 3A, a semiconductor substrate 11 is placed on a base 12, a protective plate 14 having an opening 14 a is placed on the semiconductor substrate 11, and screwed with screws 15. Then, the protective plate 14 is tightly fixed on the semiconductor substrate 11. Thereby, the etched region of the semiconductor substrate 11 is masked.

  Next, an etching solution is applied to the inside of the opening 14a of the protective plate 14 (step S03), and the semiconductor substrate 11 is etched by contacting for a predetermined time (step S04).

  Specifically, as shown in FIG. 3 (b), using a pipette 16, an etching solution 17 for dissolving the semiconductor substrate 11 in a predetermined amount (target depth) inside the opening 14a, for example, hydrofluoric acid and nitric acid The semiconductor substrate 11 is etched by filling a minimum amount, for example, several tens of ml of the mixed solution and contacting for a predetermined time.

Thereby, as shown in FIG. 3C, the surface layer of the semiconductor substrate 11 is etched by a predetermined etching depth Δx, for example, 10 nm.
Since the surface layer of the semiconductor substrate 11 masked by the protective plate 14 is side-etched by an etching depth Δy that is about the same as Δx, a side-etched region 18 is generated, and an unetched region 19 is left.

Next, the etching solution 17 is recovered (step S05), and the impurities dissolved in the etching solution are analyzed (step S06).
Specifically, as shown in FIG. 4A, the analytical jig 10 is tilted and the etching solution 17 is poured into a beaker 20 made of a fluorine resin and collected. The collected etching solution 21 is analyzed by, for example, a frameless atomic absorption device (not shown), and the metal impurities in the surface layer of the semiconductor substrate 11 are measured.

Next, a gap is provided between the semiconductor substrate 11 and the protective plate 14 (step S07), an etching solution is sandwiched in the gap (step S08), and the unetched region 19 masked by the protective plate 14 is etched for a predetermined time. (Step S09).
Specifically, as shown in FIG. 4B, a gap of, for example, several millimeters is provided between the semiconductor substrate 11 and the protective plate 14 by loosening the screws 15 and floating the protective plate 14 from the base 12. δ is secured.

Next, as shown in FIG. 4C, when the etchant 23 is dropped, for example, several ml, into the gap δ between the semiconductor substrate 11 and the protective plate 14 using the pipette 22, the etchant 23 is caused by surface tension. The etching solution 24 is filled in the gap δ between the semiconductor substrate 11 and the protective plate 14 by being sucked into the gap δ.
By etching the unetched region 19 with the etching solution 24, the semiconductor substrate 11 having a substantially flat surface is obtained.

  In order to spread the etching solution 24 over the entire surface of the unetched region 19 of the semiconductor substrate 11, it is preferable to hang the etching solution 23 at several places in the gap δ between the semiconductor substrate 11 and the protective plate 14.

  Next, the etching solution 24 is sucked up using, for example, the pipette 22 and discarded (step S10).

Next, it is checked whether step S02 to step S09 have been executed a predetermined number of times (step S11). If the predetermined number of times has not been satisfied (No in step S11), the process returns to step S02 and steps S02 to S09 are executed.
On the other hand, if the predetermined number of times is satisfied (Yes in step S11), the impurity analysis of the semiconductor substrate 11 is terminated.

  Thereby, in the impurity profile analysis of the semiconductor substrate 11, the unetched region 19 of the semiconductor substrate 11 that is an error factor can be removed every time, so that a more accurate impurity profile can be obtained.

  FIG. 5 shows a measurement result of an impurity profile in the case where a high concentration impurity such as cobalt (Co) is ion-implanted into the surface of the semiconductor substrate 11 in comparison with the conventional example. The impurity profile obtained by the example and the broken line 31 in the figure are the impurity profile obtained by the conventional example in which the unetched region 19 is not removed.

As shown in FIG. 5, the impurity profile 30 obtained by this example shows a high concentration of 7E18 atoms / cm ³ from the surface of the semiconductor substrate 11 to 20 nm.
Exceeds 20 nm, the impurity concentration is reduced to rapidly 2E15atoms / cm ^3, it has decreased over the 100nm to 2E14atoms / cm ^3.

On the other hand, the impurity profile 31 obtained by the conventional example is 7E17 atoms / cm ³ from the surface of the semiconductor substrate 11 to 20 nm, which is the same value as the impurity profile 30 of this embodiment.
However, when it exceeds 20 nm (that is, after step 02), the impurity concentration is 5E16 atoms / cm ^3, which is one digit higher than the impurity profile 30 according to the present example, and gradually decreases to 2E15 atoms / cm ³ over 100 nm. Who can be seen in the profile.

  From this, it is shown that the impurity profile 31 obtained by the conventional example is affected by contamination from the unetched region 19 and the background level is also increased by one digit or more.

For example, when the diameter of the semiconductor substrate 11 is 200 mm, the diameter of the opening 14 a is 180 mm, the impurity concentration of the surface layer 10 nm of the semiconductor substrate 11 is 1E14 atoms / cm ² , and the side etching amount Δy is 10 nm, the calculation results in contamination from the unetched region 19. The amount is estimated to be 6E10 atoms (2E8 atoms / cm ² ), but in actual measurement, side etching further progressed, and sometimes 1E10 to 11 atoms / cm ² or more was detected.

  Therefore, according to the present embodiment, it is possible to obtain an accurate impurity profile without the tail of the profile particularly when the surface has a high concentration and a steep impurity profile.

  As described above, in the semiconductor substrate impurity analysis method of this embodiment, the unetched region 19 of the semiconductor substrate 11 masked by the protective plate 14 is removed each time.

  As a result, contamination from the unetched region 19 is prevented, and a semiconductor substrate impurity analysis method having sufficient accuracy can be obtained.

  Here, the case of analyzing the impurity profile of the surface layer of the semiconductor substrate 11 has been described, but the impurity profile of the surface layer of a film formed on the semiconductor substrate 11, such as a polysilicon film or an insulating film, may be analyzed.

  Further, it has been described that impurity analysis (step S06) is performed every time the semiconductor substrate 11 is etched. However, it is preferable to perform impurity analysis collectively after a predetermined number of etchings in order to ensure the reproducibility of the analysis.

  Further, the case of analyzing impurities with a flameless atomic absorption device has been described, but there is no particular limitation as long as the concentration of the target substance can be measured.

  A semiconductor substrate impurity analysis method according to Example 2 of the present invention will be described with reference to FIGS. FIG. 6 is a flowchart showing a method for analyzing impurities in a semiconductor substrate, FIG. 7 is a diagram showing a tool for analyzing impurities in a semiconductor substrate, and FIG. 8 is a diagram showing a process for analyzing impurities in a semiconductor substrate.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

  This embodiment differs from the first embodiment in that the unetched region is masked and isolated from the etching solution, and the unetched region is substantially removed.

  That is, as shown in FIG. 6, the impurity analysis method for a semiconductor substrate according to the present embodiment protects the unetched region 19 of the semiconductor substrate 11 with a smaller opening instead of steps S07 to S10 shown in FIG. A step of masking using a plate (step S21) is provided.

  Specifically, as shown in FIG. 7, the impurity analyzing jig 40 of the semiconductor substrate of this embodiment is smaller than the opening 14 a of the protective plate 14 and different from each other in addition to the base 12 and the protective plate 14. A plurality of protective plates 41, 42, 43 having 41a, 42a, 43a are provided.

The opening 41a of the protection plate 41 is set smaller than the opening 14a of the protection plate 14, the opening 42a of the protection plate 42 is set smaller than the opening 41a of the protection plate 41, and the opening 43a of the protection plate 43 is set smaller than the opening 42a of the protection plate 42. ing.
The sizes of the openings 14a, 41a, 42a, 43a are set so as to be reduced by 5 mm, for example.

  As shown in FIG. 8, a sealing material 44, for example, an O-ring made of a fluorine resin, is attached to the protective plate 41 at the end of the opening 41a on the side of the semiconductor substrate 11 to block a step caused by the unetched portion 19. . Similarly, the same sealing material (not shown) is also attached to the protection plates 42 and 43.

  First, the first step S02 to step S06 are executed using the protective plate 14 having the opening 14a. As a result, a side etching region 18 is generated, and an unetched region 19 is left.

  Next, when the protection plate 14 is replaced with the protection plate 41, the unetched region 19 is masked by the protection plate 41 and isolated from the etching solution 17, so that the unetched region 19 is substantially removed.

  When the second step S02 to step S06 are performed using the protection plate 41, the surface layer of the semiconductor substrate 11 is etched by Δx, the side etching region 45 is generated, and the unetched region 46 is left.

  Next, the protection plate 41 is replaced with the protection plate 42 and the third step S02 to step S06 is executed, and the protection plate 42 is replaced with the protection plate 43 and the fourth step S02 to step S06 is executed. .

  Thereby, in the next etching process (step S04), it is possible to prevent contamination from the unetched region generated in the previous etching process (step S04) and to perform impurity analysis of the semiconductor substrate.

  As described above, the impurity analysis method of the semiconductor substrate of this embodiment is not etched in the plurality of protection plates 41, 42, 43 having openings 41a, 42a, 43a which are smaller than the openings 14a of the protection plate 14 and different from each other. Since the region is substantially removed by masking, it is not necessary to etch and remove the unetched region, and there is an advantage that the analysis process can be reduced.

  Here, the case where an O-ring made of a fluorine-based resin is used as the sealing material 44 is explained. However, since the level difference due to the unetched region 19 is slight, a paste-like wax, grease, or the like can be used as long as the material does not contain an element for analysis. Can also be used.

  Further, the sealing material 44 may be omitted as long as the influence of the etching solution 17 entering the unetched region 19 on the analysis accuracy can be ignored.

  Moreover, although the case where the three protection plates 41, 42, and 43 are added to the protection plate 14 has been described, it is needless to say that the protection plate is required for the number of repetitions.

  FIG. 9 is a diagram showing a jig for impurity analysis of a semiconductor substrate according to Example 3 of the present invention. In the present embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, description thereof is omitted, and only different portions will be described.

  This embodiment is different from the second embodiment in that an annular protective plate is fitted coaxially.

  That is, as shown in FIG. 9, the impurity analyzing jig 50 of the semiconductor substrate of this embodiment is fitted inside the opening 14a of the protective plate 14 in addition to the base 12 and the protective plate 14, and has a diameter of each other. A plurality of different annular protective plates 51, 52, 53 and means (not shown) for pressing the protective plates 51, 52, 53 to adhere and fix to the semiconductor substrate 11 are provided.

  The protective plate 51 is inscribed in the side wall of the opening 14 a of the protective plate 14, the protective plate 52 is inscribed in the side wall of the opening 51 a of the protective plate 51, and the protective plate 53 is inscribed in the side wall of the opening 52 a of the protective plate 52. Has been.

  As shown in FIG. 10, first, the first step S02 to step S06 are executed using the protective plate 14 having the opening 14a. As a result, a side etching region 18 and an unetched region 19 are generated.

  Next, when the protective plate 51 is coaxially fitted to the protective plate 14, the protective plate 51 is dropped so as to be in contact with the side wall of the opening 14 a of the protective plate 14 and contact the semiconductor substrate 11.

  When the protective plate 51 is pressed from above, the protective plate 51 is tightly fixed on the semiconductor substrate 11 and the unetched region 19 is masked and isolated from the etching solution 17, so that the unetched region 19 is substantially removed. Is done.

  When the second step S02 to step S06 are executed using the protective plate 51, the surface layer of the semiconductor substrate 11 is etched by Δx, the side etching region 54 is generated, and the unetched region 55 is left.

Next, after the protective plate 52 is coaxially fitted to the protective plate 51, the protective plate 52 is dropped so as to contact the semiconductor substrate 11 and pressed from above, the third step S02 to step S06 are executed.
Next, the protective plate 53 is coaxially fitted to the protective plate 52, and the protective plate 53 is dropped so as to be in contact with the semiconductor substrate 11 and pressed from above, and then the fourth step S02 to step S06 are executed.

  Thereby, in the next etching process (step S04), it is possible to prevent contamination from the unetched region generated in the previous etching process (step S04), and to perform the impurity analysis of the semiconductor substrate 11.

  As described above, the impurity analysis method for a semiconductor substrate according to the present embodiment uses a plurality of annular protection plates 51, 52, and 53 that are coaxially fitted inside the opening 14 a of the protection plate 14. Compared to the case where the protection plates 41, 42 and 43 are exchanged, there is an advantage that the analysis work becomes easy.

  Further, since the protective plates 51, 52 and 53 are in contact with the semiconductor substrate 11 and are fixed in close contact with each other, there is an advantage that the sealing material 43 is unnecessary.

  Here, a case has been described in which the protective plates 51, 52, and 53 are inscribed, but they may not be inscribed. In that case, positioning may be performed using an auxiliary jig, or visual observation may be performed.

  FIG. 11 is a view showing a jig for analyzing an impurity of a semiconductor substrate according to Embodiment 4 of the present invention. In the present embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, description thereof is omitted, and only different portions will be described.

  This embodiment differs from the second embodiment in that a protective plate having a cylindrical portion protruding from the opening edge toward the semiconductor substrate is fitted coaxially.

  That is, as shown in FIG. 11, the impurity analyzing jig 60 of the semiconductor substrate of this embodiment is fitted inside the opening 14a of the protective plate 14 in addition to the base 12 and the protective plate 14, and has a diameter of each other. Protective plates 61, 62, 63 having different cylindrical portions 61b, 62b, 63b, and means (not shown) for pressing the protective plates 61, 62, 63 to adhere and fix to the semiconductor substrate 11 are provided. ing.

The cylindrical portion 61b protrudes from the edge of the opening 61a of the protective plate 61 toward the semiconductor substrate, and the outer wall of the cylindrical portion 61b is set to be inscribed in the side wall of the opening 14a of the protective plate 14.
The cylindrical portion 62 b protrudes from the edge of the opening 62 a of the protective plate 62 toward the semiconductor substrate, and the outer wall of the cylindrical portion 62 b is set to be inscribed in the inner wall of the cylindrical portion 61 b of the protective plate 61.
The cylindrical portion 63 b protrudes from the edge of the opening 63 a of the protective plate 63 toward the semiconductor substrate, and the outer wall of the cylindrical portion 63 b is set to be inscribed in the inner wall of the cylindrical portion 62 b of the protective plate 62.

  As shown in FIG. 12, first, Step S02 to Step S06 are executed using the protective plate 14 having the opening 14a. As a result, a side etching region 18 is generated, and an unetched region 19 is left.

  Next, when the protective plate 61 is coaxially fitted to the protective plate 14, the cylindrical portion 61 b of the protective plate 61 is overlaid so as to contact the semiconductor substrate 11.

  By pressing the protective plate 61 from above, the protective plate 61 is closely fixed on the semiconductor substrate 11 and the unetched region 19 is masked and isolated from the etching solution 17, so that the unetched region 19 is substantially removed. The

  When the second step S02 to step S06 are executed using the protective plate 61, the surface layer of the semiconductor substrate 11 is etched by Δx, the side etching region 64 is generated, and the unetched region 65 is left.

Next, the protective plate 62 is coaxially fitted to the protective plate 61, and the cylindrical portion 62b of the protective plate 62 is overlapped and pressed from above so as to contact the semiconductor substrate 11, and then the third step from step S02 is performed. Steps up to S06 are executed.
Next, the protective plate 63 is coaxially fitted to the protective plate 62, and the cylindrical portion 63b of the protective plate 63 is overlapped and pressed from above so as to come into contact with the semiconductor substrate 11. Steps up to S06 are executed.

  Thereby, in the next etching process (step S04), it is possible to prevent contamination from the unetched region generated in the previous etching process (step S04), and to perform the impurity analysis of the semiconductor substrate 11.

  As described above, the impurity analysis method for the semiconductor substrate of this embodiment uses the protective plates 61, 62, and 63 having the same outer shape as the protective plate 14, and therefore uses the annular protective plates 51, 52, and 53. Compared to the case, there is an advantage that the work of tightly fixing the cylindrical portions 61b, 62b, and 63b after fitting is facilitated.

  In the above-described embodiments, the case where the opening size of the protective plate is constant has been described. However, the present invention is not limited to this, and an opening size that can be varied, for example, an iris diaphragm-like protective plate can also be used. .

  As shown in FIG. 13, the iris diaphragm-shaped protective plate 71 includes a plurality of thin fluorine resin blades 72 surrounding the opening 71a and a fluorine resin fixing ring that rotatably fixes one end of the blade 72. 73, a fluororesin control ring 74 (not shown) that slidably holds the other end of the blade 72, and a level actuator 75 that rotates the control ring to adjust the opening size. .

  The vane 72 has a low stud (not shown) at one end and a high stud (not shown) at the other end. The low stud falls into the hole 76 in the fixing ring 73 and is fixed rotatably. The high stud is slidably held in the radial groove of the rotating control ring 74.

  When the control ring 74 is rotated, the high stud slides along the radial groove of the control ring 74, and the blade 72 rotates about the low stud, so the size of the opening 71a is varied. The greater the number of blades 72, the closer to a perfect circle.

1 is a flowchart showing a method for analyzing impurities in a semiconductor substrate according to Embodiment 1 of the present invention. FIGS. 2A and 2B are views showing a jig for impurity analysis of a semiconductor substrate according to Example 1 of the present invention, FIG. 2A is a perspective view thereof, and FIG. 2B is cut along a line AA in FIG. Cross section viewed in the direction of the arrow. The figure which shows the impurity analysis process of the semiconductor substrate which concerns on Example 1 of this invention in order. The figure which shows the impurity analysis process of the semiconductor substrate which concerns on Example 1 of this invention in order. The figure which shows the impurity analysis result of the semiconductor substrate which concerns on Example 1 of this invention compared with a prior art example. 9 is a flowchart showing a method for analyzing impurities in a semiconductor substrate according to Embodiment 2 of the present invention. The perspective view which shows the jig | tool for impurity analysis of the semiconductor substrate which concerns on Example 2 of this invention. The figure which shows the impurity analysis process of the semiconductor substrate which concerns on Example 2 of this invention. The perspective view which shows the jig | tool for impurity analysis of the semiconductor substrate which concerns on Example 3 of this invention. The figure which shows the impurity analysis process of the semiconductor substrate which concerns on Example 3 of this invention. The perspective view which shows the jig | tool for impurity analysis of the semiconductor substrate which concerns on Example 4 of this invention. The figure which shows the impurity analysis process of the semiconductor substrate which concerns on Example 4 of this invention. The figure which shows the other protection board which concerns on this invention.

Explanation of symbols

10, 40, 50, 60 Analysis jig 11 Semiconductor substrate 12 Base 14, 41, 42, 43, 51, 52, 53, 61, 62, 63, 71 Protection plate 14a, 41a, 42a, 43a, 51a, 52a , 53a, 61a, 62a, 63a, 71a Opening 15 Screw 16, 22 Pipette 17, 21, 23, 24 Etching solution 18, 45, 54, 64 Side etching region 19, 46, 55, 65 Unetched region 20 Beaker 30 Impurity profile 31 of the present embodiment Impurity profile 44 of the conventional example Sealing members 61b, 62b, 63b Cylindrical portion 72 Blade 73 Fixing ring 75 Level actuator 76 Hole Δx, Δy Etching depth δ Clearance

Claims (5)

A first step of masking a main surface of the semiconductor substrate with a protective plate having an opening in the center, filling an opening in the protective plate with an etching solution, and etching a surface layer of the semiconductor substrate;
A second step of recovering the etchant and analyzing impurities in a surface layer of the semiconductor substrate;
A third step of providing a gap between the main surface of the semiconductor substrate and the protective plate, sandwiching an etching solution in the gap, and etching an unetched region of the surface layer of the semiconductor substrate;
Comprising
A method for analyzing impurities in a semiconductor substrate, wherein the first to third steps are repeated a predetermined number of times. A first step of masking a main surface of the semiconductor substrate with a protective plate having an opening in the center, filling an opening in the protective plate with an etching solution, and etching a surface layer of the semiconductor substrate;
A second step of recovering the etchant and analyzing impurities in a surface layer of the semiconductor substrate;
A third step of masking an unetched region of the surface layer of the semiconductor substrate with a protective plate having an opening smaller than the protective plate;
Comprising
A method for analyzing impurities in a semiconductor substrate, wherein the first to third steps are repeated a predetermined number of times. A base on which a semiconductor substrate is placed;
A plurality of protective plates having openings that are smaller than the semiconductor substrate at the center and different from each other;
Means for closely fixing the protective plate having the opening on the main surface of the semiconductor substrate;
A jig for impurity analysis of a semiconductor substrate, comprising:   The jig for impurity analysis of a semiconductor substrate according to claim 4, wherein the protective plate is an annular protective plate fitted coaxially.   5. The jig for impurity analysis of a semiconductor substrate according to claim 4, wherein the protective plate has a cylindrical portion protruding from the opening edge toward the semiconductor substrate and fitted coaxially.

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