JP2007206181A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce brightness irregularity caused by a manufacture process. <P>SOLUTION: A liquid crystal display device comprises: a display panel DP having a plurality of liquid crystal pixels PX and a plurality of thin film transistors T connected to the plurality of the liquid crystal pixels PX; and drive circuits 5, YD, XD for applying a video signal voltage on the corresponding liquid crystal pixels PX by driving each thin film transistor T for writing a non-video signal, applying a non-video signal voltage on the corresponding liquid crystal pixels and further driving the thin film transistor T for writing a video signal. The drive circuits 5, YD, XD apply an over-drive voltage of smaller amplitude than the video signal voltage prior to application of the video signal voltage in a period driving the thin film transistor T for writing the video signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device in which a display panel performs, for example, a video signal display corresponding to a video signal and a non-video signal display of black or a specific halftone not corresponding to the video signal every frame period.

  A flat display device typified by a liquid crystal display device is widely used to display an image in a computer, a car navigation system, a television receiver, or the like. A liquid crystal display device generally includes a liquid crystal display panel including a matrix array of a plurality of liquid crystal pixels, a backlight that illuminates the liquid crystal display panel, and a display control circuit that controls the display panel and the backlight.

  The liquid crystal display panel has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate. In general, an array substrate has a plurality of pixel electrodes arranged in a substantially matrix shape, a plurality of gate lines arranged along a row of the plurality of pixel electrodes, and a plurality of source lines arranged along a column of the plurality of pixel electrodes. And a thin film transistor (TFT) disposed as a pixel switching element in the vicinity of the intersection of the plurality of gate lines and the plurality of source lines. Each thin film transistor becomes conductive when the corresponding gate line is driven, and applies the potential of the corresponding source line to the corresponding pixel electrode. The counter substrate has a color filter and a common electrode that covers the color filter and faces the plurality of pixel electrodes. The pair of pixel electrodes and the common electrode constitute a liquid crystal pixel together with a pixel region which is a part of the liquid crystal layer located between the electrodes. The potential difference between the pixel electrode and the common electrode is held as a liquid crystal driving voltage after the thin film transistor is turned off, and the liquid crystal molecular arrangement in the pixel region is controlled by an electric field corresponding to the liquid crystal driving voltage. In this control, when the liquid crystal molecule alignment is controlled by a unidirectional electric field, the liquid crystal molecules are unevenly distributed in the liquid crystal layer, and finally become uncontrollable. When the potential of the common electrode is constant, in order to prevent this uneven distribution, the polarity of the liquid crystal driving voltage, which is the potential relationship between the common electrode and the pixel electrode, is set to, for example, one frame unit or horizontal pixel line (for one row). It is necessary to set the potential of the pixel electrode so as to periodically invert the pixel.

  A display control circuit includes a gate driver that drives a plurality of gate lines, a source driver that drives a plurality of source lines by a pixel voltage with respect to a pixel electrode of a horizontal pixel line corresponding to the gate line driven by the gate driver, and the gate drivers And a controller circuit for controlling the operation timing of the source driver.

  In fields such as large-sized liquid crystal televisions, OCB (Optically Compensated Bend) mode liquid crystal display panels having high-speed liquid crystal response required for moving image display are being adopted. This liquid crystal display panel performs a display operation by previously changing the alignment state of the liquid crystal molecules from the splay alignment to the bend alignment, but this bend alignment is not applied with a voltage or close to this state for a long time. Reverse transition to splay orientation. In such a liquid crystal display panel, black insertion driving is used with the intention of preventing reverse transition to splay alignment (see Patent Document 1). In this case, the liquid crystal display panel performs video signal display, for example, in about 80% of one frame period, and performs black display (non-video signal display) in which the liquid crystal driving voltage is maximized in the remaining 20% of one frame period. To be driven. In addition, this black insertion drive artificially creates an impulse-type luminance response similar to a CRT in moving image display, so it is also effective for clearing the retinal afterimage that occurs in the viewer's vision and making the movement of the object appear smooth It is.

In general black insertion driving, a plurality of gate lines need to be scanned twice for black insertion writing and video signal writing every frame period. For this reason, the gate driver sequentially selects and drives a plurality of gate lines by the gate pulse output using the first half of one horizontal scanning period (1H) of the video signal as the black insertion writing scan, and further the video signal writing. A plurality of gate lines are sequentially selected and driven by gate pulses output using the second half of one horizontal scanning period (1H) of the video signal as the embedded scanning. The source driver drives all the source lines in parallel so that a black insertion voltage is applied as a pixel voltage to the pixel electrode of one horizontal pixel line in the first half of one horizontal scanning period (1H), and further, one horizontal scanning period (1H) In the second half, all the source lines are driven in parallel so that the video signal voltages are applied as the pixel voltages to the pixel electrodes of one horizontal pixel line. In this case, the black insertion period of each pixel PX is equal to the period from the black insertion write scan to the signal write scan.
JP 2002-202491 A

  By the way, when the characteristics (particularly, mobility μ and threshold value Vt) of a plurality of thin film transistors vary due to the manufacturing process of the liquid crystal display panel, this is observed as luminance unevenness on the display screen. This luminance unevenness is particularly noticeable when the screen size is large.

  An object of the present invention is to provide a liquid crystal display device capable of reducing luminance unevenness caused by a manufacturing process.

  According to the present invention, a display panel having a plurality of liquid crystal pixels and a plurality of thin film transistors connected to the liquid crystal pixels, and driving each thin film transistor for writing a non-video signal and applying a non-video signal voltage to the corresponding liquid crystal pixel And a driving circuit for driving the thin film transistor for video signal writing and applying a video signal voltage to the corresponding liquid crystal pixel. The driving circuit is configured to output a video signal during a period in which the thin film transistor is driven for video signal writing. A liquid crystal display device configured to apply an overdrive voltage having an amplitude smaller than the video signal voltage prior to the application of the voltage is provided.

  In this liquid crystal display device, an overdrive voltage having an amplitude smaller than the video signal voltage is applied to the corresponding liquid crystal pixel prior to application of the video signal voltage during a period in which the thin film transistor is driven for video signal writing. As a result, the variation in charging error, which is the difference between the video signal voltage amplitude and the potential amplitude of the liquid crystal pixel at the end of the charging period when the thin film transistor is maintained in the conductive state for writing the video signal, and the end of this charging period. The variation in recharge error, which is the difference between the potential amplitude of the liquid crystal pixel and the retention potential amplitude of the liquid crystal pixel in the holding period after the thin film transistor is completely non-conductive, is superimposed on the opposite sign and cancels each other out. Become. Accordingly, variation in holding potential amplitude is reduced, and unevenness in luminance due to the manufacturing process can be reduced.

  Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 schematically shows a circuit configuration of the liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel DP, a backlight BL that illuminates the display panel DP, and a display control circuit CNT that controls the display panel DP and the backlight BL. The liquid crystal display panel DP has a structure in which a liquid crystal layer 3 is sandwiched between an array substrate 1 and a counter substrate 2 which are a pair of electrode substrates. For example, the liquid crystal layer 3 is preliminarily transitioned from the splay alignment to the bend alignment for a normally white display operation, and the reverse transition from the bend alignment to the splay alignment is periodically applied to be blocked by a voltage that causes black display. Includes liquid crystal material. The display control circuit CNT controls the transmittance of the liquid crystal display panel DP by the liquid crystal driving voltage applied from the array substrate 1 and the counter substrate 2 to the liquid crystal layer 3. The transition from the splay alignment to the bend alignment can be obtained by applying a relatively large electric field to the liquid crystal by a predetermined initialization process performed by the display control circuit CNT when the power is turned on.

  FIG. 2 schematically shows a cross-sectional structure of the liquid crystal display panel DP. The array substrate 1 includes a transparent insulating substrate GL made of a glass plate or the like, a plurality of pixel electrodes PE formed on the transparent insulating substrate GL, and an alignment film AL formed on the pixel electrodes PE. The counter substrate 2 is a transparent insulating substrate GL made of a glass plate or the like, a color filter layer CF formed on the transparent insulating substrate GL, a common electrode CE formed on the color filter layer CF, and on the common electrode CE. It includes an alignment film AL to be formed. The liquid crystal layer 3 is obtained by filling the gap between the counter substrate 2 and the array substrate 1 with a liquid crystal material. In FIG. 2, the liquid crystal molecules 19 are in a splay alignment state. The liquid crystal display panel DP includes a pair of retardation plates RT arranged outside the array substrate 1 and the counter substrate 2, a pair of polarizing plates PL arranged outside the retardation plates RT, and the array substrate 1 side. A light source backlight BL is provided outside the polarizing plate PL. The alignment film AL on the array substrate 1 side and the alignment film AL on the counter substrate 2 side are rubbed in parallel with each other. Thereby, the pretilt angle of the liquid crystal molecules is set to about 10 °.

  In the array substrate 1, a plurality of pixel electrodes PE are arranged in a substantially matrix shape on the transparent insulating substrate GL. In addition, a plurality of gate lines Y (Y1 to Ym) are arranged along the rows of the plurality of pixel electrodes PE, and a plurality of source lines X (X1 to Xn) are arranged along the columns of the plurality of pixel electrodes PE. . Near the intersection of the gate line Y and the source line X, a thin film transistor T is disposed as a pixel switching element. Each thin film transistor T has a gate connected to the gate line Y, a source-drain path connected between the source line X and the pixel electrode PE, and becomes conductive when driven through the corresponding gate line Y. The potential of the line X is applied to the corresponding pixel electrode PE.

  Each pixel electrode PE and common electrode CE are made of a transparent electrode material such as ITO, for example, and are each covered with an alignment film AL to form a liquid crystal pixel PX together with a pixel region that is a part of the liquid crystal layer 3. The liquid crystal molecule arrangement in the pixel region is controlled by an electric field corresponding to the liquid crystal driving voltage which is a potential difference between the electrodes CE.

  Each of the plurality of liquid crystal pixels PX has a liquid crystal capacitance Clc between the pixel electrode PE and the common electrode CE. The plurality of storage capacitor lines C1 to Cm are each capacitively coupled to the pixel electrode PE of the liquid crystal pixel PX in the corresponding row to form a storage capacitor Cst.

  The display control circuit CNT includes a gate driver YD that sequentially selects and drives the plurality of gate lines Y1 to Ym so that the plurality of thin film transistors T are conducted in units of horizontal pixel lines (pixels for one row). A source driver XD that drives the plurality of source lines X1 to Xn in parallel with the pixel voltage Vs for the pixel electrode PE of the horizontal pixel line corresponding to the selected gate line, and a driving voltage that generates a driving voltage for the display panel DP A generation circuit 4 and a controller circuit 5 for controlling the gate driver YD and the source driver XD are provided. The gate driver YD is also used to set the storage capacitor lines C1 to Cm to a predetermined potential.

  The driving voltage generation circuit 4 generates a predetermined number of gradation reference voltages VREF used by the source driver XD, and a common voltage generation that generates a common voltage Vcom applied to the common electrode CE. Circuit 7 is included. The controller circuit 5 includes a vertical timing control circuit 11 that generates a control signal CTY for the gate driver YD based on the synchronization signal SYNC input from the external signal source SS, and a source based on the synchronization signal SYNC input from the external signal source SS. A horizontal timing control circuit 12 that generates a control signal CTX for the driver XD and a video processing circuit 13 that performs, for example, black insertion double speed conversion on video information input from the external signal source SS are included. The video information is a plurality of pixel data DI for a plurality of liquid crystal pixels PX, and is updated every frame period (vertical scanning period V). The control signal CTY is supplied to the gate driver YD, and the control signal CTX is supplied from the video processing circuit 13 to the source driver XD together with the pixel data DO of the conversion result. The control signal CTY is used for vertical timing control that causes the gate driver YD to sequentially drive the plurality of gate lines Y as described above. The control signal CTX is a liquid crystal pixel for one row as a conversion result of the video processing circuit 13. The pixel data DO obtained in PX units and output in series is assigned to a plurality of source lines X, and used for horizontal timing control for causing the source driver XD to perform an operation of specifying an output polarity.

  FIG. 3 shows the operation when black insertion driving is performed at a vertical scanning speed of double speed. Here, the gate driver YD sequentially selects a plurality of gate lines Y1 to Ym for video signal writing and black insertion writing (non-video signal writing) in one frame period under the control of the control signal CTY, and A gate pulse for making the thin film transistor T conductive for a predetermined period not exceeding 1/2 of one horizontal scanning period H is supplied to the selection gate line Y. In the video processing circuit 13, the pixel data DI for one row is converted into black insertion (non-video) data B for one row and video signal data S for one row every 1H, and is output as pixel data DO. The video signal data S has the same gradation value as that of the pixel data DI, and the black insertion data B has a gradation value for black display. Each of the black insertion data B for one row and the video signal data S for one row is output in series from the video processing circuit 13 for each H / 2 period. The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 6 to convert the data signals B and S into a black insertion voltage and a video signal voltage, respectively, and outputs a pixel voltage. Vs is output in parallel to the plurality of source lines X1 to Xn. That is, the source driver XD drives the source lines X1 to Xn in parallel so that the black insertion voltage is applied to the pixel electrode PE of one horizontal pixel line in the first half of one horizontal scanning period (1H), and further, one horizontal scanning period. In the second half of (1H), the source lines X1 to Xn are driven in parallel so as to apply the video signal voltages to the pixel electrodes PE of one horizontal pixel line. The pixel voltage Vs is a voltage applied to the pixel electrode PE with reference to the common voltage Vcom of the common electrode CE. For example, the polarity inversion is performed with respect to the common voltage Vcom so that 1H1V inversion driving combining line inversion driving and frame inversion driving is performed. Is done.

  When the charging capability of the thin film transistor in black insertion is insufficient, the gate driver YD and the source driver XD may be operated as shown in FIG. 4, for example, to compensate for this shortage. In this case, two black insertion writes are performed for one video signal write. In order to decrease the driving speed, for example, the gate driver YD and the source driver XD may be operated as shown in FIG. In this case, the gate lines Y1 to Ym are selected two by two in the black insertion write scan and one by one in the video signal write scan. In synchronization with such selection, the black insertion voltage, the video signal voltage, and the video signal voltage are output from the source driver XD every 2H / 3 periods in two consecutive horizontal scanning periods (2H). Here, black insertion writing is performed together for two horizontal pixel lines in the 2H / 3 period, but the number of selection gate lines is further increased, for example, three horizontal pixel lines, four horizontal pixel lines, or more. It may be performed together for horizontal pixel lines.

FIG. 6 shows a waveform of potential change of the pixel electrode PE obtained when the conventional video signal writing is performed on the liquid crystal display panel shown in FIG. 1 following black insertion writing. Here, consider a case where the polarity of the liquid crystal driving voltage is inverted every frame. In the positive polarity frame, the potential of the pixel electrode PE decreases from the + black insertion voltage level toward the + video signal voltage level due to the video signal writing. In the negative frame, the potential of the pixel electrode PE rises from the black insertion voltage level to the video signal voltage level by video signal writing. If the thin film transistor T has insufficient charging capability, the thin film transistor T is maintained in a conductive state by the gate pulse from the gate line Y selected for writing the video signal in both the positive frame and the negative frame. It becomes difficult for the potential of the pixel electrode PE to reach the video signal voltage level during the charging period. That is, when the thin film transistor T is turned off, the potential of the pixel electrode PE does not match the video signal voltage output from the source driver XD to the source line X. The charging error δV ₁ is the difference between the video signal voltage amplitude V ₀ and the potential amplitude V ₁ of the pixel electrode PE at the end of the charging period, and is averaged between the positive frame and the negative frame and δV ₁ = V ₁ −V _{0 = (2V 1 - 2V 0} ) / represented as 2.

When the gate pulse, that is, the gate line potential Vg falls and the charging period ends, the thin film transistor T becomes non-conductive. As a result, the pixel electrode PE enters a floating state in which the pixel electrode PE is electrically disconnected from the source line X, and charge transfer from the pixel electrode PE occurs as a punching phenomenon so as to charge the parasitic capacitance Cgd between the gate and drain of the thin film transistor. . As a result, the potential of the pixel electrode PE slightly decreases from the level at the end of charging. The amount of potential change at this time is called a punch-out voltage. As shown in FIG. 7, if there is a delay in the fall of the gate line potential Vg due to the wiring resistance or the wiring capacity depending on the wiring length of the gate line Y from the gate driver YD to the thin film transistor T, Until the voltage between the source and the drain reaches the threshold value, the thin film transistor T is not completely turned off, and a current Ids flows between the source and the drain so as to eliminate the potential difference between the source and the drain caused by the punching phenomenon. Recharging is performed so as to increase the potential of the pixel electrode PE. The amount of change in the potential of the pixel electrode PE due to this recharging is called a recharge voltage. Accordingly, when the thin film transistor T becomes completely non-conductive, the potential of the pixel electrode PE is a result of superimposing the punch-out voltage due to the parasitic capacitance Cgd and the recharge voltage due to the transition period of the thin film transistor T to the non-conductive state. As determined. The recharging error δV ₂ is the difference between the potential amplitude V ₁ of the pixel electrode PE at the end of the charging period and the holding potential amplitude V ₂ of the pixel electrode PE in the holding period after the time point when the thin film transistor T is completely non-conductive. Thus, it is averaged in the positive frame and the negative frame and expressed as δV ₂ = V ₂ −V ₁ = (2V ₂ −2V ₁ ) / 2. Therefore, the holding potential amplitude V ₂ of the pixel electrode PE is a result of superimposing the charging error δV ₁ and the recharging error δV ₂ on the video signal amplitude V ₀ , and is represented by V ₀ + δV ₁ + δV ₂ .

When characteristics (especially mobility μ and threshold value Vt) of the plurality of thin film transistors T vary due to the manufacturing process of the liquid crystal display panel DP, the charging error δV ₁ and recharging of the pixel electrodes PE corresponding to the thin film transistors T respectively. A difference occurs in the error δV ₂ , which causes the holding potential amplitude V ₂ to vary. Variation of the holding potential amplitude V ₂ would be observed as luminance unevenness on the display screen. The charging error δV ₁ decreases as the charging capability of the thin film transistor T increases, and the charging capability increases as the mobility μ of the thin film transistor T increases and the threshold value Vt decreases. On the other hand, the recharge error δV ₂ also decreases as the charging capability of the thin film transistor T increases. However, since the gate-drain voltage in the negative frame is larger than the gate-drain voltage in the positive frame, the recharge error δV ₂ is more dominant in the negative frame. Therefore, the recharging error δV ₂ (= V ₂ −V ₁ ) decreases as the charging capability of the thin film transistor T increases and the recharging pressure in the negative frame increases. That is, the variation in the charging error δV _{1 and} the variation in the recharging error δV ₂ are superimposed with the same sign, and the luminance unevenness tends to appear remarkably. When the screen size is large, this luminance unevenness appears more remarkably. That is, when the screen size is increased, the CR time constant determined by the wiring resistance and wiring capacitance of the gate line Y also increases, so that the rise and fall of the gate potential Vg are delayed. The rise delay shortens the effective writing time and increases the charge error δV ₁ . Further, the falling delay becomes a rounded waveform, which increases the recharge error δV ₂ .

FIG. 8 shows a waveform of a potential change of the pixel electrode PE obtained by the video signal writing method applied to the liquid crystal display device shown in FIG. In order to realize this video signal writing, the source driver XD has an amplitude exceeding the video signal voltage before the video signal voltage is applied during the period in which the thin film transistor T for one horizontal pixel line is driven for video signal writing. The drive voltage ΔVs is configured to be applied to the pixel electrode PE of one horizontal pixel line. Specifically, the source driver XD is timing-controlled by the controller circuit 5, and outputs an overdrive voltage ΔVs obtained by temporarily setting the amplitude of the video signal voltage to be about 1V smaller to the plurality of source lines X1 to Xn. . When the pixel electrode PE is charged with the overdrive voltage ΔVs within the 1H period, the sign of the charging error δV ₁ is opposite to that in the case of the conventional driving, so that the higher the charging capability of the thin film transistor T, the larger δV ₁ becomes. .

In the present embodiment, during the period in which the thin film transistor T for one horizontal pixel line is driven for video signal writing, the overdrive voltage ΔVs having an amplitude smaller than the video signal voltage is applied to one horizontal pixel prior to the application of the video signal voltage. As a result of being applied to the pixel electrode PE of the line, variations in the charging error δV ₁ and the recharging error δV ₂ are superimposed with opposite signs and cancel each other. Therefore, variations in the holding potential amplitude V ₂ of the pixel electrodes PE decreases, luminance unevenness is reduced.

In fact, and try to simulate the variations in the holding potential amplitude _{V 2} relative to 23-inch OCB liquid crystal display panel DP of WXGA resolution is 2H1V inversion driving using an amorphous silicon thin film transistor T, as shown in FIGS. 9 to 11 Results were obtained. FIG. 9 is a graph showing charging error δV ₁ obtained by applying various overdrive voltages ΔVs, and FIG. 10 is a graph showing recharging error δV ₂ obtained by applying various overdrive voltages ΔVs. FIG. 11 is a graph showing a result of superimposing the charging error δV ₁ shown in FIG. 9 and the recharging error δV ₂ shown in FIG. According to FIG. 11, when the overdrive voltage ΔVs to about 1.0 V, variation in characteristics of the thin film transistor T is understood that the difference between the holding potential amplitude V ₂ in the case of the minimum in the case of the maximum becomes substantially 0 mV.

  In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.

  The overdrive voltage ΔVs described above may be constant regardless of the video signal voltage, or may be changed according to the video signal voltage. Further, the overdrive voltage ΔVs may be set to different values on the positive polarity side and the negative polarity side. Further, the time for applying the overdrive voltage ΔVs may be changed corresponding to the video signal voltage.

It is a figure which shows schematically the circuit structure of the liquid crystal display device which concerns on one Embodiment of this invention. It is a figure which shows roughly the cross-section of the liquid crystal display panel shown in FIG. FIG. 2 is a diagram illustrating an operation when black insertion driving is performed at a double vertical scanning speed in the liquid crystal display panel illustrated in FIG. 1. It is a figure which shows the operation | movement in the case where two black insertion writing is performed with respect to one video signal writing in the liquid crystal display panel shown in FIG. It is a figure which shows the operation | movement in case the some gate line shown in FIG. 1 is selected 2 each in black insertion write scanning. It is a figure which shows the waveform of the electric potential change of the pixel electrode obtained when the video signal writing of a conventional system is performed on the liquid crystal display panel shown in FIG. 1 following black insertion writing. FIG. 2 is a diagram illustrating a delay that occurs in the fall of the gate line potential due to a wiring resistance, a wiring capacity, or the like depending on the wiring length of the gate line from the gate driver to the thin film transistor shown in FIG. It is a figure which shows the waveform of the electric potential change of the pixel electrode obtained by the video signal writing system applied to the liquid crystal display device shown in FIG. 2 is a graph showing charging errors obtained by applying various overdrive voltages from the source driver shown in FIG. 1. FIG. 10 is a graph showing recharge errors obtained by applying various overdrive voltages from the source driver shown in FIG. 11 is a graph showing a result of superimposing the charging error shown in FIG. 9 and the recharging error shown in FIG. 10.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Counter substrate, 3 ... Liquid crystal layer, 5 ... Controller circuit, DP ... Liquid crystal display panel, PE ... Pixel electrode, CE ... Common electrode, Clc ... Liquid crystal capacity, Cst ... Storage capacity, PX ... Liquid crystal pixel , T ... thin film transistor, Y ... gate line, X ... source line, YD ... gate driver, XD ... source driver.

Claims (7)

  A display panel having a plurality of liquid crystal pixels and a plurality of thin film transistors connected to the plurality of liquid crystal pixels; and driving each thin film transistor for non-video signal writing to apply a non-video signal voltage to the corresponding liquid crystal pixels; A driving circuit that drives a thin film transistor for writing a video signal and applies a video signal voltage to the corresponding liquid crystal pixel, and the driving circuit includes the video signal in a period in which the thin film transistor is driven for writing the video signal. A liquid crystal display device configured to apply an overdrive voltage having an amplitude smaller than that of the video signal voltage prior to voltage application.   The liquid crystal display device according to claim 1, wherein the driving circuit is configured to periodically invert the polarity of the non-video signal voltage and the video signal voltage.   The liquid crystal display device according to claim 2, wherein the overdrive voltage changes corresponding to a video signal voltage.   3. The liquid crystal display device according to claim 2, wherein the overdrive voltage is constant regardless of the video signal voltage.   The liquid crystal display device according to claim 2, wherein the overdrive voltage is set to a different value on the positive polarity side and the negative polarity side.   3. The liquid crystal display device according to claim 2, wherein the application time of the overdrive voltage changes corresponding to the video signal voltage.   The liquid crystal display device according to claim 2, wherein the liquid crystal pixel is an OCB liquid crystal pixel.

Images