JP2007201241A - Circuit board and semiconductor device - Google Patents

Circuit board and semiconductor device Download PDF

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Publication number
JP2007201241A
JP2007201241A JP2006018949A JP2006018949A JP2007201241A JP 2007201241 A JP2007201241 A JP 2007201241A JP 2006018949 A JP2006018949 A JP 2006018949A JP 2006018949 A JP2006018949 A JP 2006018949A JP 2007201241 A JP2007201241 A JP 2007201241A
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circuit board
region
semiconductor chip
bonding
bonding pad
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JP4776012B2 (en
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Makoto Tsubonoya
誠 坪野谷
Kiyoshi Mita
清志 三田
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board and a semiconductor device improved in a mounting efficiency of a semiconductor device. <P>SOLUTION: A semiconductor chip 12 is mounted through a die attach film 13. In a circuit board 11 having a through-hole formed by being opened to an end surface and penetrating the circuit board, a first region 1111 is mounted which contacts the end surface of the semiconductor chip 12 prepared at the perimeter of the region on which the semiconductor chip 12. At the same time, the region 1111 is prepared so as to plug the through hole 113, and a bonding pad 111 is provided which extends along the outline of the semiconductor chip 12 without contacting the end surface of the circuit board 11 and has a second region 1112 continuing to the first region 1111. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、回路基板及び半導体装置に関し、とくに半導体装置の実装効率を向上するための技術に関する。   The present invention relates to a circuit board and a semiconductor device, and more particularly to a technique for improving the mounting efficiency of the semiconductor device.

近年、機器の小型化や多機能化に伴い、半導体装置には実装効率のより一層の向上が求められるようになってきている。このため、半導体チップの基板への実装に際しては、回路基板の面積を変えずによりサイズの大きな半導体チップを搭載することが要求されている。
特開２００４−７１８９８号公報 In recent years, with the miniaturization and multifunctionalization of devices, semiconductor devices have been required to further improve mounting efficiency. For this reason, when mounting a semiconductor chip on a substrate, it is required to mount a semiconductor chip having a larger size without changing the area of the circuit substrate.
JP 2004-71898 A

ここで半導体チップ側に設けられた電極パッドと回路基板上に設けられたボンディングパッドとをワイヤーボンディングにより接続するタイプの半導体装置において、回路基板によりサイズの大きな半導体チップを搭載しようとした場合、半導体チップとボンディングパッドとの間隔を狭くせざるを得ない。このため、半導体チップの基板への接合に用いられる液状（ペースト状）の接着剤が半導体チップの周囲に流出し、ボンディングパッド表面の汚染やボンディングワイヤーの接合不良、ボンディングパッド間のショートといった問題を生じやすくなる。   Here, in a semiconductor device of a type in which an electrode pad provided on the semiconductor chip side and a bonding pad provided on the circuit board are connected by wire bonding, when a semiconductor chip having a large size is to be mounted on the circuit board, the semiconductor The distance between the chip and the bonding pad must be narrowed. For this reason, the liquid (paste-like) adhesive used to bond the semiconductor chip to the substrate flows out around the semiconductor chip, causing problems such as contamination of the bonding pad surface, bonding wire bonding failure, and shorting between bonding pads. It tends to occur.

このような接着剤の流出による問題を防ぐため、例えば、特許文献１に記載の技術では、半導体素子が実装される領域を囲むようにダイパッドの表面の周辺部に溝を設け、半導体素子をロウ剤によってダイパッドに実装する際、広がったロウ剤の流出を上記溝により阻止するようにしている。   In order to prevent such a problem due to the outflow of the adhesive, for example, in the technique described in Patent Document 1, a groove is provided in the peripheral portion of the surface of the die pad so as to surround the region where the semiconductor element is mounted, and the semiconductor element is soldered. When the solder is mounted on the die pad by the agent, the spread of the spreading agent is prevented by the groove.

しかしながら、特許文献１に記載の技術では、その製造に際し溝を形成するためのプロセスが別途必要となり製造工程が複雑化してしまう。また、溝を設けることで回路基板に搭載可能な半導体チップのサイズが制約を受けることになる。   However, the technique described in Patent Document 1 requires a separate process for forming a groove in the manufacture thereof, and the manufacturing process becomes complicated. In addition, the provision of the groove restricts the size of the semiconductor chip that can be mounted on the circuit board.

またボンディングパッドが設けられている面とは逆の面に形成されている裏面電極とを電気的に接続する貫通孔が形成されている回路基板の場合、貫通孔の部分にボンディングワイヤーを接合するとボンディングパッド表面の凹凸により接合不良を生じやすくなるため、ワイヤーボンディングは貫通孔が設けられている部分を避けて行う必要がある。また、ボンディングパッドの剥離を防ぐため、ボンディングパッドの断面は回路基板の端面になるべく露出させないようにする必要もある。さらに、ボンディングワイヤーの接合位置が回路基板の端面に近すぎると、ダイシング時におけるボンディングワイヤーの切断や、接合部の脆弱化といった問題を生じるため、ボンディングワイヤー回路基板の端面からなるべく離間させた位置でボンディングパッドに接合する必要もある。   In addition, in the case of a circuit board having a through hole that electrically connects a back electrode formed on the surface opposite to the surface on which the bonding pad is provided, a bonding wire is bonded to the through hole portion. Since bonding defects easily occur due to unevenness on the surface of the bonding pad, it is necessary to perform wire bonding while avoiding portions where through holes are provided. In order to prevent the bonding pad from peeling off, it is necessary to prevent the cross section of the bonding pad from being exposed to the end face of the circuit board as much as possible. Furthermore, if the bonding position of the bonding wire is too close to the end face of the circuit board, problems such as cutting of the bonding wire at the time of dicing and weakening of the bonding section will occur, so at a position as far as possible from the end face of the bonding wire circuit board. It is also necessary to bond to the bonding pad.

本発明は以上のような観点に基づいてなされたもので、半導体装置の実装効率を向上することが可能な回路基板及び半導体装置を提供することを目的とする。   The present invention has been made based on the above viewpoint, and an object thereof is to provide a circuit board and a semiconductor device capable of improving the mounting efficiency of the semiconductor device.

上記目的を達成するための本発明のうちの主たる発明は、半導体チップが搭載される回路基板であって、当該回路基板の端面に開口し当該回路基板を貫通して形成される貫通孔と、前記半導体チップが搭載される領域の周囲に設けられ、当該回路基板の端面に接するとともに前記貫通孔を塞ぐように設けられた第１の領域と、当該回路基板の端面に接することなく前記半導体チップの外形に沿って延出する、前記第１の領域に連続する第２の領域と、を有して形成される前記半導体チップの電極と電気的に接続するためのボンディングパッドと、を備えることとする。   A main invention of the present invention for achieving the above object is a circuit board on which a semiconductor chip is mounted, and has a through-hole formed at an end surface of the circuit board and penetrating the circuit board. A first region provided around the region where the semiconductor chip is mounted, contacting the end surface of the circuit board and closing the through-hole, and the semiconductor chip without contacting the end surface of the circuit substrate A bonding pad for electrically connecting to the electrode of the semiconductor chip formed to have a second region extending along the outer shape of the semiconductor chip and continuing to the first region. And

このように、ボンディングパッドの回路基板の端面に接する部分を第１の領域のみとすることで、ボンディングパッドの回路基板の端面に露出する部分が必要最小限となり、ボンディングパッドの剥がれやボンディングワイヤーの切断などの問題を防ぐことができる。また製造時における貫通孔の穿孔状態によっては、第１の領域にボンディングワイヤーを接合するための領域が充分に確保できない場合があるが、本発明の場合、第２の領域にボンディングワイヤーを接合することができるため、貫通孔の穿孔状態にかかわらずボンディングワイヤーを接合するための領域を確実に確保することができる。またボンディングワイヤーを第２の領域に接合するようにすることで、貫通孔の直上にボンディングワイヤーを接合する必要もなくなり、ボンディングワイヤーをボンディングパッドに確実に接合することができる。   In this way, the portion of the bonding pad that contacts the end surface of the circuit board is only the first region, so that the portion of the bonding pad that is exposed to the end surface of the circuit board is minimized, and the bonding pad is peeled off and the bonding wire is removed. Problems such as disconnection can be prevented. Further, depending on the state of drilling of the through hole at the time of manufacture, there may be a case where a sufficient area for bonding the bonding wire cannot be secured in the first area. In the present invention, the bonding wire is bonded to the second area. Therefore, the region for bonding the bonding wire can be surely ensured regardless of the drilled state of the through hole. Further, by bonding the bonding wire to the second region, it is not necessary to bond the bonding wire directly above the through hole, and the bonding wire can be reliably bonded to the bonding pad.

本発明によれば、半導体装置の実装効率を向上することができる。   According to the present invention, the mounting efficiency of a semiconductor device can be improved.

以下、本発明の一実施形態につき詳細に説明する。図１Ａ乃至図１Ｃに本発明の一実施形態として説明する半導体装置１の構成を示している。このうち図１Ａは半導体装置１の表面側斜視図であり、図１Ｂは半導体装置１の下面側斜視図である。また図１Ｃは半導体装置１の側面図である。これらの図に示すように、半導体装置１は略正方形状の扁平な回路基板１１と、回路基板１１の表面２に搭載される電子デバイスである扁平直方体状の半導体チップ１２（ベアチップ）とを含んで構成されている。   Hereinafter, one embodiment of the present invention will be described in detail. 1A to 1C show a configuration of a semiconductor device 1 described as an embodiment of the present invention. 1A is a perspective view of the front surface side of the semiconductor device 1, and FIG. 1B is a perspective view of the lower surface side of the semiconductor device 1. FIG. 1C is a side view of the semiconductor device 1. As shown in these drawings, the semiconductor device 1 includes a substantially square flat circuit board 11 and a flat rectangular semiconductor chip 12 (bare chip) which is an electronic device mounted on the surface 2 of the circuit board 11. It consists of

半導体チップ１２が搭載される回路基板１１は、エポキシやポリエステル、ポリイミド等の樹脂を素材とするリジッド配線基板又はフレキシブル基板（ＦＰＣ）等の有機基板である。なお、本発明は回路基板１１がセラミック配線基板や金属配線基板などの無機基板である場合にも適用することができる。また本実施形態で説明する回路基板１１は単層構造であるものとするが、回路基板１１は多層構造であってもよい。   The circuit board 11 on which the semiconductor chip 12 is mounted is an organic substrate such as a rigid wiring substrate or a flexible substrate (FPC) made of a resin such as epoxy, polyester, or polyimide. The present invention can also be applied when the circuit board 11 is an inorganic board such as a ceramic wiring board or a metal wiring board. The circuit board 11 described in the present embodiment is assumed to have a single layer structure, but the circuit board 11 may have a multilayer structure.

回路基板１１の表面２には、回路基板１１の端面１１２に沿って複数のボンディングパッド１１１が形成されている。ボンディングパッド１１１は、例えば、Ｎｉ／Ａｕ等の導体を無電解メッキ又は電解メッキすることにより形成されている。   A plurality of bonding pads 111 are formed along the end surface 112 of the circuit board 11 on the surface 2 of the circuit board 11. The bonding pad 111 is formed by, for example, electroless plating or electrolytic plating of a conductor such as Ni / Au.

回路基板１１の端面１１２には、端面１１２に開口する貫通孔１１３（Via Hall）が形成されている。図２に貫通孔１１３の周辺部分の拡大斜視図を示している。同図に示すように、貫通孔１１３の断面は、回路基板１１の端面１１２から所定長さの直線部分を有する扁平略半円状（長孔状）である。なお、貫通孔１１３の内側面には、Ａｕ／Ｎｉ等の導電体によるメッキが施されており、これによりボンディングパッド１１１は回路基板１１の裏面３に形成された裏面電極１１４に電気的に接続されている。   A through hole 113 (Via Hall) that opens to the end surface 112 is formed in the end surface 112 of the circuit board 11. FIG. 2 shows an enlarged perspective view of the peripheral portion of the through hole 113. As shown in the figure, the cross section of the through hole 113 is a flat semicircular shape (long hole shape) having a straight portion having a predetermined length from the end surface 112 of the circuit board 11. The inner surface of the through-hole 113 is plated with a conductor such as Au / Ni, so that the bonding pad 111 is electrically connected to the back electrode 114 formed on the back surface 3 of the circuit board 11. Has been.

図３Ａに回路基板１１の平面図を示している。同図に示すように、回路基板１１の中央には、搭載される半導体チップ１２の平面形状に合わせた形のダイパッド１１５が設けられている。   FIG. 3A shows a plan view of the circuit board 11. As shown in the figure, at the center of the circuit board 11, a die pad 115 having a shape matching the planar shape of the semiconductor chip 12 to be mounted is provided.

ボンディングパッド１１１はダイパッド１１５の周囲に設けられている。同図に示すように、ボンディングパッド１１１は、回路基板１１の端面１１２とその面を一致させるとともに回路基板１１の表面２の貫通孔１１３が形成されている部分を塞ぐように設けられる第１の領域１１１１と、回路基板１１の端面１１２と一致することなく半導体チップ１２の縁に沿って延出して設けられ第１の領域１１１１に連続する第２の領域１１１２とを有している。   The bonding pad 111 is provided around the die pad 115. As shown in the figure, the bonding pad 111 is provided so that the end surface 112 of the circuit board 11 and the surface thereof coincide with each other and the portion where the through hole 113 of the surface 2 of the circuit board 11 is formed is blocked. The region 1111 has a second region 1112 that extends along the edge of the semiconductor chip 12 and does not coincide with the end surface 112 of the circuit board 11 and continues to the first region 1111.

なお、図３Ａにおいて、ボンディングパッド１１１に示している破線は第１の領域１１１１と第２の領域１１１２との境界を表す。但し、図３Ａは本発明の一例に過ぎず、第１の領域１１１１や第２の領域１１１２の形状や大きさは同図に示すものに限られるわけではない。第２の領域１１１２は、必要本数のボンディングワイヤー２０を接合可能な形状及び面積に設定されている。ボンディングパッド１１１は、以上の構成によってその全体が略Ｌ字状を呈する。   In FIG. 3A, a broken line shown on the bonding pad 111 represents a boundary between the first region 1111 and the second region 1112. However, FIG. 3A is merely an example of the present invention, and the shape and size of the first region 1111 and the second region 1112 are not limited to those shown in FIG. The second region 1112 is set to have a shape and an area capable of bonding the required number of bonding wires 20. The bonding pad 111 is generally L-shaped as a whole by the above configuration.

ここでボンディングパッド１１１の端面が回路基板１１の端面１１２と一致しているとボンディングパッド１１１が剥がれ易くなり、また回路基板１１のダイシング時にボンディングワイヤー２０が切断されてしまう可能性がある。しかしながら本実施形態の半導体装置１では、上記のようにボンディングパッド１１１の端面１１２に接する部分を第１の領域１１１１のみとすることでボンディングパッド１１１の端面１１２への露出を必要最小限としているため、ボンディングパッド１１１の剥がれやボンディングワイヤー２０の切断を防ぐことができる。より具体的には、図３Ａに示すＬ字のボンディングパッド１１１は６つの側辺を有しており、このうち半導体チップ１２の外周側辺と平行で、最も外周に設けられている側辺が、半導体チップ１２側に面する半導体チップ１２の外周側辺と平行に設けられている側辺の長に渡って設けられていない事が、ボンディングパッド１１１の剥がれやボンディングワイヤー２０の切断を防ぐ上で重要である。   Here, if the end surface of the bonding pad 111 coincides with the end surface 112 of the circuit board 11, the bonding pad 111 is easily peeled off, and the bonding wire 20 may be cut when the circuit board 11 is diced. However, in the semiconductor device 1 of the present embodiment, since the portion in contact with the end surface 112 of the bonding pad 111 is only the first region 1111 as described above, exposure to the end surface 112 of the bonding pad 111 is minimized. The peeling of the bonding pad 111 and the cutting of the bonding wire 20 can be prevented. More specifically, the L-shaped bonding pad 111 shown in FIG. 3A has six sides, and among these, the side provided on the outermost side is parallel to the outer side of the semiconductor chip 12. In order to prevent peeling of the bonding pad 111 and cutting of the bonding wire 20, it is not provided over the length of the side provided parallel to the outer peripheral side of the semiconductor chip 12 facing the semiconductor chip 12. Is important.

本実施形態の半導体装置１では、ボンディングワイヤー２０は第２の領域１１１２に接合される。すなわち、製造時における貫通孔１１３の穿孔状態によっては、第１の領域１１１１にボンディングワイヤー２０を接合するための領域を確保することができなくなる場合もあるが、第２の領域１１１２を設けていることで、ボンディングワイヤーを接合するための領域が確実に確保されることとなる。また第２の領域１１１２にボンディングワイヤー２０を接合するようにすることで、表面の凹凸により接合強度が充分に確保できない可能性のある貫通孔１１３の直上にボンディングワイヤー２０を接合する必要がなくなり、これによりボンディングパッド１１１にボンディングワイヤー２０を確実に接合することができる。別の表現をすれば、第２の領域１１１２は、これに対応する電極パッド１２１とずれた位置に設けられ、ボンディングワイヤー２０が半導体チップ１２の側辺に対して斜めに交叉するように配置されている。なお、回路基板１１の表面２の角隅部にはインデックスマーク１１６が設けられている。   In the semiconductor device 1 of the present embodiment, the bonding wire 20 is bonded to the second region 1112. That is, depending on the drilled state of the through hole 113 at the time of manufacture, there may be a case where a region for bonding the bonding wire 20 cannot be secured in the first region 1111, but the second region 1112 is provided. By this, the area | region for joining a bonding wire will be ensured reliably. Also, by bonding the bonding wire 20 to the second region 1112, it is not necessary to bond the bonding wire 20 directly above the through hole 113, which may not be able to ensure sufficient bonding strength due to surface irregularities, Thereby, the bonding wire 20 can be reliably bonded to the bonding pad 111. In other words, the second region 1112 is provided at a position shifted from the corresponding electrode pad 121, and the bonding wire 20 is disposed so as to cross obliquely with respect to the side of the semiconductor chip 12. ing. Note that index marks 116 are provided at corners of the surface 2 of the circuit board 11.

図３Ｂに回路基板１１の裏面図を示している。回路基板１１の下面のボンディングパッド１１１の第１の領域１１１１に対向する位置には複数の裏面電極１１４が設けられている。裏面電極１１４は一部切り欠きを有する略長方形状である。   FIG. 3B shows a back view of the circuit board 11. A plurality of back surface electrodes 114 are provided on the lower surface of the circuit board 11 at positions facing the first region 1111 of the bonding pad 111. The back electrode 114 has a substantially rectangular shape with a part of the notch.

以上によって、回路基板１１の端面には、ボンディングパッド１１１の第１の領域１１１１の断面、貫通孔１１３の内側面の断面、及び裏面電極１１４の断面が露出することとなる。   As a result, the cross section of the first region 1111 of the bonding pad 111, the cross section of the inner surface of the through hole 113, and the cross section of the back electrode 114 are exposed on the end surface of the circuit board 11.

ところで、回路基板１１は、例えば、複数の回路基板１１が形成された集合基板１１０から切り出される。この場合の集合基板１１０の平面図を図４Ａに示している。同図に示すように、この例では隣接する位置に形成された回路基板１１のボンディングパッド１１１が連続して形成されている。また図４Ｂは集合基板１１０の裏面図であるが、同図に示すように、隣接する位置に形成された回路基板１１の裏面電極１１４は連続している。このように、集合基板１１０の状態で隣接するボンディングパッド１１１や裏面電極１１４を連続して形成することで、回路パターンが簡素化され、よってパターン形成や貫通孔１１３の穿孔にかかる工数を減らすことができる。   By the way, the circuit board 11 is cut out from the collective board 110 on which the plurality of circuit boards 11 are formed, for example. A plan view of the collective substrate 110 in this case is shown in FIG. 4A. As shown in the figure, in this example, the bonding pads 111 of the circuit board 11 formed at adjacent positions are continuously formed. FIG. 4B is a back view of the collective substrate 110. As shown in FIG. 4B, the back electrodes 114 of the circuit board 11 formed at adjacent positions are continuous. Thus, by continuously forming the bonding pads 111 and the back electrode 114 adjacent to each other in the state of the collective substrate 110, the circuit pattern is simplified, thereby reducing the number of steps for pattern formation and drilling of the through holes 113. Can do.

一方、集合基板１１０自体は、例えば、複数の集合基板１１０が形成された連続回路基板１２０から切り出される。図５に連続回路基板１２０の一例（平面図）を示している。連続回路基板１２０は、例えば、基板樹脂の片面又は両面に銅（Ｃｕ）箔（Resin Coated Copper Foil）をラミネートするラミネート工程、貫通孔１１３が形成される部分のフォトエッチング工程、レーザー光照射等による孔あけ工程、レーザー光照射やプラズマ等のドライデスミア処理あるいは化学的処理によるウェットデスミア処理による樹脂残渣工程、表面に銅（Ｃｕ）メッキ（無電解／電解）等の処理を行う導体層形成工程、フォトエッチングによりパターニングすることにより回路を形成する回路形成工程などの、各種の工程を経ることにより製造される。   On the other hand, the collective substrate 110 itself is cut out from, for example, the continuous circuit substrate 120 on which a plurality of collective substrates 110 are formed. FIG. 5 shows an example (plan view) of the continuous circuit board 120. The continuous circuit board 120 is formed by, for example, a laminating process of laminating copper (Cu) foil (Resin Coated Copper Foil) on one or both sides of a substrate resin, a photo-etching process of a portion where the through hole 113 is formed, laser light irradiation, or the like. A conductor layer forming step for performing a drilling step, a resin residue step by dry desmear treatment such as laser light irradiation or plasma or wet desmear treatment by chemical treatment, copper (Cu) plating (electroless / electrolysis) on the surface, It is manufactured through various processes such as a circuit forming process for forming a circuit by patterning by photoetching.

一方、半導体チップ１２の典型例は半導体基板に熱酸化法やＣＶＤ（Chemical Vapor Deposition）、スパッタ、リソグラフィ、不純物拡散等の各種前工程を行うことにより製造されたＣＭＯＳ（Complementary Metal Oxide Semiconductor）である。しかしながら、ＣＭＯＳに限らず、半導体チップ１２は、例えば、バイＣＭＯＳ、ＭＯＳ、リニア（バイポーラ）ＩＣ等の他の集積回路であってもよい。また半導体チップ１２はトランジスタ、ダイオードなどのディスクリートな素子であってもよい。   On the other hand, a typical example of the semiconductor chip 12 is a complementary metal oxide semiconductor (CMOS) manufactured by performing various pre-processes such as thermal oxidation, CVD (Chemical Vapor Deposition), sputtering, lithography, and impurity diffusion on a semiconductor substrate. . However, the semiconductor chip 12 is not limited to the CMOS, and may be another integrated circuit such as a bi-CMOS, MOS, or linear (bipolar) IC. The semiconductor chip 12 may be a discrete element such as a transistor or a diode.

半導体チップ１２の上面には、その周辺縁部に沿って所定形状の複数の電極パッド１２１が形成されている。各電極パッド１２１は、各電極パッド１２１に近接する位置に形成されているボンディングパッド１１１と、Ａｕ／Ａｌなどの導体線を用いたワイヤーボンディングによって接続されている。なお、ワイヤーボンディングの方法としては、ボールボンディング（Ball Bonding）や超音波接合法などが用いられる。   A plurality of electrode pads 121 having a predetermined shape are formed on the upper surface of the semiconductor chip 12 along the peripheral edge thereof. Each electrode pad 121 is connected to a bonding pad 111 formed at a position close to each electrode pad 121 by wire bonding using a conductor wire such as Au / Al. As a wire bonding method, ball bonding or ultrasonic bonding is used.

ところで、配線されたボンディングワイヤー２０の曲率が大きいと、ボンディングワイヤー２０の不良が生じ易くなる。そこで本実施形態の半導体装置１では、ボンディングパッド１１１の領域のうち電極パッド１２１の直近ではなく、ボンディングワイヤー２０を電極パッド１２１の直近から斜めにずれた位置にある第２の領域１１１２に接合するようにしている。これによりボンディングワイヤー２０の曲率の増大を緩和してボンディングワイヤー２０の過剰変形を防ぐことができる。そしてこれにより本実施形態の半導体装置１は、回路基板１１のサイズにより近いサイズの半導体チップ１２をボンディングワイヤー２０の曲率を増大させることなく搭載することが可能となる。   By the way, if the curvature of the wired bonding wire 20 is large, the bonding wire 20 is likely to be defective. Therefore, in the semiconductor device 1 of the present embodiment, the bonding wire 20 is bonded to the second region 1112 which is not in the immediate vicinity of the electrode pad 121 in the bonding pad 111 region but is obliquely shifted from the immediate vicinity of the electrode pad 121. I am doing so. As a result, an increase in the curvature of the bonding wire 20 can be mitigated and excessive deformation of the bonding wire 20 can be prevented. As a result, the semiconductor device 1 of this embodiment can mount the semiconductor chip 12 having a size closer to the size of the circuit board 11 without increasing the curvature of the bonding wire 20.

本実施形態において、半導体チップ１２は、ダイアタッチフィルム（Die Attach Film）（以下、ＤＡＦ１３という。）を用いて回路基板１１に接合するようにしている。ここでＤＡＦ１３としては、例えば、耐熱性及び接着強度を得るための熱硬化性樹脂としてエポキシ樹脂を７０〜８０％、保持力向上及びテープ製造の適正化を図るためのバインダー樹脂としてアクリルポリマーを１０〜１５％、ピックアップ性及びダイシング性を向上させるためのＵＶ硬化型樹脂としてアクリル樹脂を１０〜１５％を含む組成ものを用いることができる。なお、半導体チップ１２をＤＡＦ１３によりダイパッド１１５に接合するようにした場合、半導体チップ１２を回路基板１１に押圧した際に半導体チップ１２の周囲に接着剤が流出するようなことが無く、ボンディングパッドの汚染やボンディングワイヤー２０の接合不良やボンディングパッド間のショートといった前述の問題を生じない。また回路基板１１表面の状態は個体ごとに異なるため、液状（ペースト状）の接着剤を用いた場合には、接着剤の量のコントロールが難しいが、ＤＡＦ１３ではそのような問題も生じない。さらに、ＤＡＦ１３の厚みは通常は高精度で一定であるため、回路基板１１に接合された半導体チップ１２に殆ど傾きが無く、各電極パッド１２１と各電極パッド１２１が接続されるボンディングパッド１１１との間の距離の精度が確保され、ワイヤーボンディングによる製品間のばらつきが抑えられる。   In the present embodiment, the semiconductor chip 12 is bonded to the circuit board 11 using a die attach film (hereinafter referred to as DAF 13). Here, as the DAF 13, for example, an epoxy resin is 70 to 80% as a thermosetting resin for obtaining heat resistance and adhesive strength, and an acrylic polymer is 10 as a binder resin for improving holding power and optimizing tape production. A composition containing 10 to 15% of an acrylic resin can be used as the UV curable resin for improving the pickup property and the dicing property by 15%. When the semiconductor chip 12 is bonded to the die pad 115 by the DAF 13, the adhesive does not flow out around the semiconductor chip 12 when the semiconductor chip 12 is pressed against the circuit board 11, and the bonding pad The above-mentioned problems such as contamination, bonding failure of the bonding wire 20 and short circuit between bonding pads do not occur. Further, since the state of the surface of the circuit board 11 varies from individual to individual, it is difficult to control the amount of the adhesive when a liquid (paste-like) adhesive is used, but the DAF 13 does not cause such a problem. Furthermore, since the thickness of the DAF 13 is usually highly accurate and constant, the semiconductor chip 12 bonded to the circuit board 11 has almost no inclination, and each electrode pad 121 and the bonding pad 111 to which each electrode pad 121 is connected are connected. The accuracy of the distance between them is ensured, and variation between products due to wire bonding is suppressed.

ＤＡＦ１３によって半導体チップ１２を回路基板１１に接合する場合の工程の一例を図６に示している。同図における（ａ）に示す工程では、ＤＡＦ１３（２０μｍ）を、複数の半導体チップ１２が形成されたダイシング前の半導体基板１５の裏面に透明な基材１６（１００μｍ）とともに貼付している（貼付工程）。続く（ｂ）に示す工程では、ＤＡＦ１３にＵＶ照射を行って、ＤＡＦ１３の弾性率を向上させ、回路基板１１への接着性を向上させている。（ｃ）に示す工程では、ＤＡＦ１３及び基材１６とともに半導体基板１５をダイシングしている。なお、ＤＡＦ１３層が完全に切断されるようにするため、ダイシングはフルカットダイシングで行う。またピックアップ時にＤＡＦ１３を基材１６から剥がしやすくするためにダイシング深度は基材１６が２０〜３０μｍ切り込まれる程度としている。（ｄ）に示す工程では、ダイシング後の半導体チップ１２をＤＡＦ１３ごと基材１６からピックアップし、例えば１２０℃に加温した回路基板１１上のダイパッド１１５に仮マウントしている。（ｅ）に示す工程では、半導体チップ１２が仮マウントされた回路基板１１を例えば１６０℃に昇温（キュア処理）し、半導体チップ１２を回路基板１１に接合している。   FIG. 6 shows an example of a process when the semiconductor chip 12 is bonded to the circuit board 11 by the DAF 13. In the step shown in FIG. 5A, DAF 13 (20 μm) is pasted together with a transparent base material 16 (100 μm) on the back surface of the semiconductor substrate 15 before dicing on which a plurality of semiconductor chips 12 are formed (pasting). Process). In the subsequent step (b), the DAF 13 is irradiated with UV to improve the elastic modulus of the DAF 13 and improve the adhesion to the circuit board 11. In the step shown in (c), the semiconductor substrate 15 is diced together with the DAF 13 and the base material 16. Note that dicing is performed by full-cut dicing so that the DAF 13 layer is completely cut. Further, the dicing depth is set such that the base material 16 is cut by 20 to 30 μm so that the DAF 13 can be easily peeled off from the base material 16 during pick-up. In the step shown in (d), the semiconductor chip 12 after dicing is picked up together with the DAF 13 from the base material 16 and temporarily mounted on the die pad 115 on the circuit board 11 heated to 120 ° C., for example. In step (e), the circuit board 11 on which the semiconductor chip 12 is temporarily mounted is heated to, for example, 160 ° C. (curing process), and the semiconductor chip 12 is bonded to the circuit board 11.

なお、以上の工程を経て製造された回路基板１１、半導体チップ１２、及びボンディングワイヤー２０の全体は、絶縁性樹脂の被覆工程を経て、エポキシ樹脂等の熱硬化性樹脂、又はポリイミド樹脂やポリフェニレンサルファイド等の熱可塑性樹脂によって樹脂封入される。樹脂封入は、例えば、トランスファモールド法やインジェクションモールド法等の金型モールド法、ポッティング法、シート接着法などによって行う。なお、このように通常は樹脂封入が行われるが、樹脂封入は必ずしも行わなくてもよい。   The entire circuit board 11, semiconductor chip 12, and bonding wire 20 manufactured through the above steps are subjected to an insulating resin coating step, and then a thermosetting resin such as an epoxy resin, or a polyimide resin or polyphenylene sulfide. The resin is encapsulated with a thermoplastic resin. The resin encapsulation is performed by, for example, a mold molding method such as a transfer molding method or an injection molding method, a potting method, a sheet bonding method, or the like. In addition, although resin sealing is normally performed as described above, resin sealing is not necessarily performed.

以上の実施形態の説明は、本発明の理解を容易にするためのものであり、本発明を限定するものではない。本発明はその趣旨を逸脱することなく、変更、改良され得ると共に本発明にはその等価物が含まれることは勿論である。   The above description of the embodiment is for facilitating the understanding of the present invention, and does not limit the present invention. It goes without saying that the present invention can be changed and improved without departing from the gist thereof, and that the present invention includes equivalents thereof.

例えば、回路基板１１の形状は、上述したものに限られず、ボンディングパッド１１１の第１の領域１１１１と第２の領域１１１２とが連続する部分に、図１Ａに破線円Ｃで示した如く、第１の領域１１１１及び第２の領域１１１２の幅よりも細幅の括れを形成するようにしてもよい。このようにすることでボンディングパッド１１１とボンディングワイヤー２０を経路とする外部から半導体チップ１２への水分の浸入を防ぐことができる。   For example, the shape of the circuit board 11 is not limited to the above-described one, and the first region 1111 and the second region 1112 of the bonding pad 111 are continuous with each other as shown by a broken line circle C in FIG. A narrower width than the width of the first region 1111 and the second region 1112 may be formed. By doing so, it is possible to prevent moisture from entering the semiconductor chip 12 from the outside through the bonding pad 111 and the bonding wire 20 as paths.

本発明の一実施形態として説明する半導体装置１の表面側斜視図である。It is a surface side perspective view of semiconductor device 1 explained as one embodiment of the present invention. 本発明の一実施形態として説明する半導体装置１を裏面側斜視図である。It is a back surface side perspective view of semiconductor device 1 explained as one embodiment of the present invention. 本発明の一実施形態として説明する半導体装置１の側面図である。It is a side view of the semiconductor device 1 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する半導体装置１の貫通孔１１３周辺部分の拡大斜視図である。It is an expansion perspective view of the peripheral part of the through-hole 113 of the semiconductor device 1 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する回路基板１１の平面図である。It is a top view of the circuit board 11 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する回路基板１１の裏面図である。It is a back view of the circuit board 11 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する集合基板１１０の平面図である。It is a top view of the collective substrate 110 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する集合基板１１０の裏面図である。It is a back view of the collective substrate 110 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する連続回路基板１２０の平面図である。It is a top view of the continuous circuit board 120 demonstrated as one Embodiment of this invention. （ａ）〜（ｅ）は、本発明の一実施形態として説明する半導体チップ１２を回路基板１１に接合する際の工程を示す図である。(A)-(e) is a figure which shows the process at the time of joining the semiconductor chip 12 demonstrated as one Embodiment of this invention to the circuit board 11. FIG.

符号の説明Explanation of symbols

１ 半導体装置
１１ 回路基板
１１１ ボンディングパッド
１１１１ 第１の領域
１１１２ 第２の領域
１１３ 貫通孔
１１４ 裏面電極
１１５ ダイパッド
１１６ インデックスマーク
１２ 半導体チップ
１２１ 電極パッド
１３ ＤＡＦ
１５ 半導体基板
２０ ボンディングワイヤー DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Circuit board 111 Bonding pad 1111 1st area | region 1112 2nd area | region 113 Through-hole 114 Back surface electrode 115 Die pad 116 Index mark 12 Semiconductor chip 121 Electrode pad 13 DAF
15 Semiconductor substrate 20 Bonding wire

Claims (8)

半導体チップが搭載される回路基板であって、
当該回路基板の端面に開口し当該回路基板を貫通して形成される貫通孔と、
前記半導体チップが搭載される領域の周囲に設けられ、当該回路基板の端面に接するとともに前記貫通孔を塞ぐように設けられた第１の領域と、当該回路基板の端面に接することなく前記半導体チップの外形に沿って延出する、前記第１の領域に連続する第２の領域と、を有して形成される前記半導体チップの電極と電気的に接続するためのボンディングパッドと、
を備えたこと
を特徴とする回路基板。 A circuit board on which a semiconductor chip is mounted,
A through hole formed in the end face of the circuit board and penetrating the circuit board;
A first region provided around the region where the semiconductor chip is mounted, contacting the end surface of the circuit board and closing the through-hole, and the semiconductor chip without contacting the end surface of the circuit substrate A bonding pad for electrically connecting to the electrode of the semiconductor chip formed to extend along the outer shape of the semiconductor chip, and a second region continuous to the first region;
A circuit board characterized by comprising: 請求項１に記載の回路基板であって、
前記貫通孔によって、前記ボンディングパッドと、前記回路基板の前記ボンディングパッドが設けられている面とは逆の面に形成されている他の電極とが電気的に接続されていること
を特徴とする回路基板。 The circuit board according to claim 1,
The bonding pad and the other electrode formed on the surface opposite to the surface on which the bonding pad is provided of the circuit board are electrically connected by the through hole. Circuit board. 請求項１に記載の回路基板であって、
前記ボンディングパッドは、前記第１の領域と前記第２の領域とによって全体が略Ｌ字状を呈してなること
を特徴とする回路基板。 The circuit board according to claim 1,
The circuit board according to claim 1, wherein the bonding pad is formed in a substantially L shape by the first region and the second region. 請求項１に記載の回路基板であって、
前記第１の領域と前記第２の領域とが連続する部分に括れが形成されてなること
を特徴とする回路基板。 The circuit board according to claim 1,
A circuit board, wherein a constriction is formed at a portion where the first region and the second region are continuous. 半導体チップと、
前記半導体チップが搭載される回路基板と
を含み、
前記回路基板は、前記回路基板の端面に開口し、前記回路基板を貫通して形成される貫通孔を有し、
前記回路基板は、前記半導体チップが搭載される領域の周囲に設けられ前記回路基板の端面に接するとともに前記貫通孔を塞ぐように設けられた第１の領域と、前記回路基板の端面に接することなく前記半導体チップの外形に沿って延出する、前記第１の領域に連続する第２の領域とから形成される前記半導体チップと電気的に接続するためのボンディングパッドを有すること
を特徴とする半導体装置。 A semiconductor chip;
A circuit board on which the semiconductor chip is mounted,
The circuit board has an opening at an end surface of the circuit board, and has a through hole formed through the circuit board,
The circuit board is provided around a region where the semiconductor chip is mounted, is in contact with an end surface of the circuit board and is in contact with an end surface of the circuit board, and is provided so as to close the through hole. And a bonding pad for extending electrical connection with the semiconductor chip formed from the second region continuous with the first region and extending along the outer shape of the semiconductor chip. Semiconductor device. 請求項５に記載の半導体装置であって、
前記貫通孔によって、前記ボンディングパッドと、前記回路基板の前記ボンディングパッドが設けられている面とは逆の面に形成されている他の電極とが電気的に接続されていること
を特徴とする半導体装置。 The semiconductor device according to claim 5,
The bonding pad and the other electrode formed on the surface opposite to the surface on which the bonding pad is provided of the circuit board are electrically connected by the through hole. Semiconductor device. 請求項５に記載の半導体装置であって、
前記半導体チップは、扁平直方体状であり、
前記半導体チップは、その上面周辺縁部に沿って形成された電極パッドを有し、
一端が前記ボンディングパッドの前記第２の領域に接合され、他端が前記電極パッドに接合されるボンディングワイヤーを含むこと
を特徴とする半導体装置。 The semiconductor device according to claim 5,
The semiconductor chip has a flat rectangular parallelepiped shape,
The semiconductor chip has an electrode pad formed along the peripheral edge of the upper surface,
A semiconductor device comprising: a bonding wire having one end bonded to the second region of the bonding pad and the other end bonded to the electrode pad. 請求項５に記載の半導体装置であって、
前記半導体チップは、ダイアタッチフィルムによって前記回路基板に接合されてなること
を特徴とする半導体装置。

The semiconductor device according to claim 5,
The semiconductor device, wherein the semiconductor chip is bonded to the circuit board by a die attach film.

JP2006018949A 2006-01-27 2006-01-27 Circuit board and semiconductor device Expired - Fee Related JP4776012B2 (en)

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JP2007227462A (en) * 2006-02-21 2007-09-06 Sanyo Electric Co Ltd Circuit board and semiconductor device
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