JP2007201166A - Redundant relief method for semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out redundancy repair by reliably detecting a half-short-circuit fault or a half-open-circuit fault, which is not detected in a conventional manner, concerning a process for inspecting a semiconductor integrated circuit device. <P>SOLUTION: The semiconductor integrated circuit device is constituted with the use of a redundancy repair method so as to allow a circuit 104 to be inspected and a redundant circuit 105, both of which have the same function to be respectively and individually connected to power sources VS1(101) and VS2(102). Then an abnormal current detecting circuit 106 measures still power source current in the respective power sources VS1, VS2. When the measurement value of the still power source current in the circuit 104 to be inspected is abnormal, the fault is determined based on a fact that the still power source current is made to flow more compared with a normal standard value or the redundant circuit 105 when the half-open-circuit fault or the half-short-circuit fault exists in the circuit 104 to be inspected. A power source supply route is disconnected with respect to the circuit 104 to be inspected, which is determined to have the fault, with the use of a fuse circuit 107, so that replacement is performed in the redundant circuit 105. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a redundancy repair method for a semiconductor integrated circuit device, and more particularly, to a technique that enables redundant repair by reliably detecting a half short failure or a half open failure.

  Conventionally, in the inspection of semiconductor integrated circuit devices, stuck-at faults, open faults and short-circuit faults are detected by performing function tests. The repair is realized by replacing the prepared redundant repair circuit. As a replacement method with the redundant relief circuit, there is a method of cutting a fuse by applying a laser or a voltage.

  In particular, in a system LSI in which memory and logic are mixed, a redundant memory cell is usually prepared in advance in a DRAM, but a redundant logic part is not mounted on a logic part. In order to make it possible to repair the defect, there are some which include a fuse circuit that connects a plurality of logic units to a memory, selects only one of them, and disconnects the other logic units. By selecting the logic part after the diffusion step, the defective logic part can be separated and the yield can be improved (for example, see Patent Document 1).

Further, as a technique for facilitating the discovery of defective memory cells for performing redundant memory repair, the memory cell power supply wiring is separated from the power supply lines used in the entire semiconductor memory device, and is individualized for each memory mat. By selectively connecting the cell power supply wiring to the second power supply wiring for memory cell current measurement and measuring the current when various voltages are applied to it, the DC current failure contents in the memory block can be analyzed In some cases, memory cell defect repair is efficiently performed (see, for example, Patent Document 2).
JP 2004-48618 A Japanese Patent No. 3226422

  However, conventional semiconductor integrated circuit device inspections can repair stuck-at faults, open faults, and short fault chips, but cannot reliably detect chips with half-short faults or half-open faults. It was determined as a defective chip in the quiescent power supply current test. As a result, half-short faults and half-open fault chips that can be redundantly remedied are treated as defective products, which is an obstacle to yield improvement. Further, the conventional redundancy repair method for a semiconductor integrated circuit device has a problem that inspection time is increased because a separate inspection process is required, and inspection cost is increased because a dedicated inspection device is required separately. .

  SUMMARY OF THE INVENTION An object of the present invention is to provide a redundant relief method for a semiconductor integrated circuit device capable of reliably detecting a half short failure and a half open failure in a semiconductor integrated circuit device inspection process and enabling redundancy relief.

  According to the redundant relief method of the present invention, a circuit to be inspected and a redundant circuit having the same function mounted on a semiconductor integrated circuit device are connected to individual power supplies, and the measured value of the quiescent power supply current in the individual power supply is abnormal. In such a case, the circuit to be inspected is determined to be faulty, and the circuit to be inspected determined to be faulty is replaced with a redundant circuit. According to the above configuration, if the circuit under test has a half open failure or a half short circuit failure, the quiescent power supply current flows more than usual. This makes it possible to reliably detect a half short failure or a half open failure and perform redundancy relief.

  Furthermore, the present invention provides the above redundancy remedy method in which the circuit under test and the redundant circuit are connected to separate grounds, and the static power supply current is measured in all combinations of the separate power supplies and the separate grounds. It is. According to the above configuration, the quiescent power supply current is measured in all combinations of individual power supplies and individual grounds, so that it is possible to increase the number of inspection target circuits and redundant circuits without increasing individual power supplies.

  The semiconductor integrated circuit device according to the present invention includes a circuit to be tested, a redundant circuit, an individual power supply unit, and a redundant repair unit that replaces the circuit to be tested with a redundant circuit, and implements the above redundant repair method. It is configured to be possible. According to the above configuration, it is possible to reliably detect a half short-circuit failure or a half-open failure by determining an abnormality in the measured value of the quiescent power supply current in the individual power source of the semiconductor integrated circuit device as a failure of the circuit to be inspected. It can be performed.

  Further, according to the present invention, in the semiconductor integrated circuit device having the above-described configuration, one redundant circuit is associated with a plurality of circuits to be inspected. According to the above configuration, the redundant circuit can be reduced and the chip area can be reduced. When two or more circuits to be inspected are determined to be faulty, they are treated as defective products without performing redundancy relief.

  Further, according to the present invention, the semiconductor integrated circuit device having the above-described configuration is equipped with an abnormal current detection circuit that measures a quiescent power supply current and determines an abnormality in a measured value. Further, according to the present invention, in the semiconductor integrated circuit device configured as described above, the abnormal current detection circuit is provided with a standard current circuit for comparing with a measured value of the quiescent power supply current. According to the above configuration, an abnormal current detection circuit having a standard current circuit for comparison with a measured value of the quiescent power supply current is mounted inside, thereby increasing the chip area, but it is necessary to prepare an external abnormal current detection means Therefore, it becomes possible to carry out redundant relief with a single chip.

  Furthermore, according to the present invention, a fuse circuit is used as a redundancy relief means in the semiconductor integrated circuit device having the above configuration. According to the above configuration, the power supply path to the circuit to be inspected determined to be faulty can be disconnected using the fuse circuit and replaced with the redundant circuit, so that redundant relief can be easily performed.

  Furthermore, the present invention provides a semiconductor integrated circuit device having the above-described configuration, comprising means for comparing measured values of the quiescent power supply current of the circuit under test and the redundant circuit in individual power supplies, for the circuit having the larger measured value of the quiescent power supply current. The power supply path is cut off. According to the above configuration, the power supply path can be cut using a fuse circuit for a circuit that is not an abnormal current but has a large current value, and the entire power consumption can be reduced.

  Further, according to the present invention, in the semiconductor integrated circuit device having the above configuration, connection switching means such as a selector circuit is used as redundancy relief means. According to the above configuration, since the circuit under test determined to be faulty can be replaced with a redundant circuit by the connection switching means such as the selector circuit, it is not possible to reduce the power consumption, but it is possible to easily repair the redundancy. It can be carried out.

  The present invention further includes a test mode in which the redundant repair means automatically replaces the circuit under test determined to be faulty in the semiconductor integrated circuit device configured as described above. According to the above configuration, by setting the semiconductor integrated circuit device in the test mode, the redundant repair is automatically performed by the redundant repair means, so that the test time can be shortened and the test cost can be reduced.

  According to the present invention, it is possible to reliably detect and relieve a half-open failure or a half-short failure that could not be reliably detected by the function test. As a result, what was conventionally handled as a defective chip is relieved, and the effect of yield improvement is obtained. Further, by automatically measuring the quiescent power supply current and detecting the abnormality, the relief process in a separate process becomes unnecessary, and the test time can be shortened and the test cost can be reduced.

(Embodiment 1)
FIG. 1 is a configuration diagram of a semiconductor integrated circuit device showing a redundancy repair method according to Embodiment 1 of the present invention. In FIG. 1, reference numerals 101 and 102 denote individual power sources VS1 and VS2 input from a semiconductor inspection apparatus or the like, 103 denotes a ground VSS, 104 denotes an inspection target circuit A, and 105 denotes a redundant circuit having the same function as the inspection target circuit A104. B and 106 are abnormal current detection circuits that individually detect the quiescent power supply currents of the inspection target circuit A104 and the redundant circuit B105 and detect abnormal currents of the inspection target circuit A104, and 107 is an inspection target circuit A104 based on the result of the abnormal current detection circuit 106. The fuse box replaces the redundant circuit B105.

  When there is a half open fault or a half short fault in the circuit A104 to be inspected, the quiescent power supply current flows more than the normal standard value or the redundant circuit B105. Based on this principle, the quiescent power supply current value is measured by the abnormal current detection circuit 106, and when the current flows more than the normal standard value or the redundant circuit B105, it is determined that redundant relief is necessary, and the fuse is disconnected in the fuse box 107. Relief by

  According to the present embodiment, when the static power supply current of the circuit to be inspected becomes an abnormal current, an abnormality detection signal is output, and the fuse is cut using the abnormality detection signal so as to select the redundant circuit, Redundant relief can be performed automatically.

  FIG. 4 is a diagram illustrating a configuration example of the abnormal current detection circuit 106. In FIG. 4, 121 is a test mode in which redundancy relief is performed by a quiescent power supply current test, 122 is a switch that is turned on in the test mode, 123 is a test standard current that determines that the quiescent power supply current is abnormal, and 124 is a quiesce of the circuit to be inspected A comparator for comparing the power supply current value with the inspection standard current 123, 125 is a level shifter for converting the voltage value to a voltage required for cutting the fuse, and 108 is a fuse for enabling the redundant circuit.

  With this configuration of the abnormal current detection circuit, the fuse is not blown except in the test mode where redundancy relief is performed, and in the test mode, when the measured value of the quiescent power supply current is larger than the inspection standard current value, it is automatically Redundant relief can be performed by cutting the fuse.

  FIG. 5 is a diagram illustrating another configuration example of the abnormal current detection circuit 106, in which the comparison circuit 124 in FIG. 4 is replaced with a selection circuit 126 that selects the circuit A104 to be inspected or the redundant circuit B105. With this configuration, it is possible to cut the fuse for a circuit having a large current value but not an abnormal current, thereby reducing the overall power consumption.

  FIG. 6 is a diagram showing a configuration in which the fuse box 107 is replaced with a data storage circuit 109. The data storage circuit 109 is a circuit that stores information on the circuit to be inspected that has become abnormal in the abnormal current detection circuit 106. By storing the information in the flash memory or the initialization memory for each product type and switching the selector circuit, it is possible to perform redundancy relief without using the fuse box 107.

  FIG. 7 is a view showing a semiconductor integrated circuit device after the redundant relief method according to the present invention is assembled. In FIG. 7, 130 is a chip after assembly, 131 is a power supply terminal for VS1, 132 is a power supply terminal for VS2, and 133 is a ground terminal. If the circuit A104 to be inspected is defective, power is not supplied to the defective circuit by not wiring the PAD of the power supply 101 to the VS1 power supply terminal 131 or by not generating the PAD, so that power consumption can be reduced. Become.

  FIG. 8 is a diagram showing a configuration in which the abnormal current detection circuit 106 is placed outside the chip 130 in the semiconductor integrated circuit device that implements the redundancy remedy method of the present invention. In FIG. 8, reference numeral 134 denotes a current value confirmation terminal for each power source for measuring the quiescent power supply current, and 135 denotes a terminal for inputting a fuse cutting signal according to the result of the abnormality detection circuit 106. Thus, the chip area can be reduced by moving the abnormal current detection circuit to the outside of the chip.

  FIG. 10 is a diagram showing an example of an inspection flow in the redundancy repair method of the present invention. In this inspection flow, 201 is a quiescent power supply current measurement, 202 is a determination as to whether the inspection target circuit is normal or abnormal based on the quiescent power supply current measurement result, 203 is a redundant relief performed when the inspection target circuit is abnormal, and 204 is Products A and 205 when the circuit to be inspected is normal are products B in which the circuit to be inspected is abnormal and redundant relief has been performed. Since product B has an abnormal circuit to be inspected, only the redundant circuit can be used. However, since product A has both the circuit to be inspected and the redundant circuit normal, both circuits can be used. By such a redundant repair method, the product A that can use both circuits and the product B that can use only one circuit can be distinguished from each other.

  FIG. 11 is a diagram showing another inspection flow example in the redundancy repair method of the present invention. In this test flow, before performing the function test 212, first, the quiescent power supply current measurement 201 is performed and the redundancy repair 203 is performed, thereby eliminating the redundant repair process after the function test, reducing the test time, Cost reduction can be achieved.

(Embodiment 2)
FIG. 2 is a configuration diagram of a semiconductor integrated circuit device showing a redundancy repair method according to the second embodiment of the present invention. In the present embodiment, the ground VSS 103 of the first embodiment is divided into individual ground VSS1 (111) and VSS2 (112) and combined with individual power supplies 101 and 102. The other components in the present embodiment are the same as those in the first embodiment, and the inspection flow in which the redundancy repair method of the present embodiment is implemented and the technology relating to the assembly of the semiconductor integrated circuit device are also the same as those in the first embodiment. Therefore, explanation is omitted. With this configuration, it is possible to add a test target circuit C114 and a redundant circuit D115 different from the test target circuit A104 without increasing individual power supplies, and increase the number of circuits that automatically perform redundancy relief. Is possible.

  FIG. 3 is a diagram showing a combination of individual power sources and individual grounds in the configuration of FIG. By combining the two power sources VS1 and VS2 and the two grounds VSS1 and VSS2, it is possible to provide two test target circuits A, a test target circuit C, two redundant circuits B, and a redundant circuit D. The test target circuit A And the circuit C to be inspected can be relieved.

  FIG. 9 is a configuration diagram in which the redundant circuit 105 and the redundant circuit 115 in the configuration of FIG. 2 are combined. In FIG. 9, reference numeral 110 denotes an abnormal number detection circuit for selecting the measurement result of the abnormal current detection circuit 106. In this configuration, when one relief circuit and two or more circuits to be inspected are defective, a defect flag is set and treated as defective. Thus, the chip area can be reduced by reducing redundant circuits.

  The redundancy repair method of the present invention is effective for inspections that improve the yield of half-breaks and half-shorts that cannot be repaired only by functional functions as the processing technology of semiconductor integrated circuits is miniaturized.

1 is a diagram showing a configuration of a semiconductor integrated circuit device that performs a redundancy repair method according to a first embodiment of the present invention. The figure which shows the structure of the semiconductor integrated circuit device which implements the redundant relief method which concerns on Embodiment 2 of this invention. The figure which shows the combination of the power supply and ground in the semiconductor integrated circuit device which implements the redundant relief method which concerns on Embodiment 2 of this invention. The figure which shows the structural example of the abnormal current detection circuit in the redundant relief method of this invention. The figure which shows the structural example of the abnormal current detection circuit in the redundant relief method of this invention. The figure which shows the structure which replaced the fuse box of the abnormal current detection circuit with the data storage circuit in the redundancy relief method of this invention. The product assembly drawing of the semiconductor integrated circuit device which implemented the redundant relief method of this invention. 1 is a diagram showing a configuration in which an abnormal current detection circuit is placed outside a chip in a semiconductor integrated circuit device that implements the redundancy repair method of the present invention. FIG. The figure which shows the structure which provided one relief circuit in the some test object circuit in the semiconductor integrated circuit device which implements the redundancy relief method which concerns on Embodiment 2 of this invention. The figure which shows the test | inspection flow example of the semiconductor integrated circuit device which implemented the redundancy relief method of this invention. The figure which shows the test | inspection flow example of the semiconductor integrated circuit device which implemented the redundancy relief method of this invention.

Explanation of symbols

101 First individual power supply VS1
102 Second individual power supply VS2
103 Common ground VSS
104 Circuit A to be inspected
105 Redundant circuit B
106 Abnormal current detection circuit 107 Fuse box 108 Fuse 109 Data storage circuit 110 Abnormal number detection circuit 111 First individual ground VSS1
112 Second individual ground VSS2
114 Circuit C to be inspected
115 Redundant circuit D
121 Static power supply current test mode for performing redundancy relief 122 Switch turned on in test mode 123 Standard current 124 Comparison circuit 125 Level shifter 126 Selection circuit 131 Power supply terminal for VS1 132 Power supply terminal for VS2 133 VSS ground terminal 134 Current value output terminal 135 Abnormal Current result input terminal

Claims (9)

  A redundant relief method for a semiconductor integrated circuit device in which a circuit under test and a redundant circuit having the same function as the circuit under test are connected to individual power supplies, respectively, and the measured value of the quiescent power supply current at the individual power supply is abnormal A redundancy remedy method for a semiconductor integrated circuit device, in which the circuit under test is determined to be faulty in the case of the failure, and the circuit under test determined to be faulty is replaced with the redundancy circuit.   A semiconductor integrated circuit device in which the circuit under test and the redundant circuit are respectively connected to individual grounds, and the quiescent power supply current is measured in all combinations of the individual power sources and the individual grounds. 2. A redundant relief method for a semiconductor integrated circuit device according to 1.   A circuit to be inspected, a redundant circuit having the same function as the circuit to be inspected, means for supplying individual power to the circuit to be inspected and the redundant circuit, and redundancy repair for replacing the circuit to be inspected with the redundant circuit And a semiconductor integrated circuit device configured by associating one redundant circuit with a plurality of circuits to be inspected.   4. The semiconductor integrated circuit device according to claim 3, further comprising an abnormal current detection circuit that measures the quiescent power supply current and determines an abnormality in the measured value.   5. The semiconductor integrated circuit device according to claim 4, wherein the abnormal current detection circuit includes a standard current circuit for comparing with the measured value of the quiescent power supply current.   4. The semiconductor integrated circuit device according to claim 3, wherein the redundancy relief means is a fuse circuit.   Means for comparing the measured value of the static power supply current of the circuit under test and the redundant circuit in an individual power supply, and the fuse circuit cuts off the power supply path to the circuit having the larger measured value of the static power supply current 7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device operates.   4. The semiconductor integrated circuit device according to claim 3, wherein the redundancy relief means is a connection switching means such as a selector circuit.   4. The semiconductor integrated circuit device according to claim 3, wherein the redundancy repair means includes a test mode in which a circuit to be inspected determined to be faulty is replaced with the redundancy circuit.

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