JP2007200930A - Thin film transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor where characteristic deterioration can be suppressed while thinning microfabrication is realized. <P>SOLUTION: An active layer 12 is arranged on a glass substrate 2. A gate insulating film 21 is arranged on the glass substrate 2 by covering the active layer 12. A side wall insulating film 18 whose film thickness is larger than the gate insulating film 21 positioned above the active layer 12 is disposed by surrounding a periphery of the active layer 12. Turn-on in sub-channel TFT at the side of the active layer 12 is delayed, and characteristic deterioration of the thin film transistor 6 can be suppressed even if microfabrication is realized. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a thin film transistor including a gate insulating film covering a semiconductor thin film provided on an insulating substrate, and a gate electrode provided on the semiconductor thin film via the gate insulating film, and a method for manufacturing the same.

  Conventionally, a thin film transistor (TFT) having a so-called mesa structure used for a flat display device such as a liquid crystal display device or an organic EL display device has an active layer as a semiconductor thin film laminated on a glass substrate. The layer has a source region and a drain region located on both sides of the channel region. A gate insulating film is laminated on the glass substrate so as to cover the active layer, and a gate electrode is laminated on the gate insulating film facing the channel region of the active layer.

  Further, an interlayer insulating film is laminated on the gate insulating film so as to cover the gate electrode, contact holes are provided in the interlayer insulating film and the gate insulating film, and the source region and the drain region of the active layer are formed by these contact holes. Is open. Each of the source electrode and the drain electrode is laminated on the contact hole and the interlayer insulating film.

  In such a flat display device, in order to realize SOD (System On Display), it is important to improve a TFT characteristic to manufacture a multi-functional element, and at the time of manufacturing such a multi-functional element. In order to improve the performance of the TFT element, it is necessary to miniaturize the TFT element.

  However, as the TFT element is further miniaturized, the electric field concentrates on the side wall portion of the semiconductor thin film in the mesa type TFT, and therefore, the sub channel TFT on the side wall portion is more easily turned on than the TFT on the surface portion. Become.

  For this reason, in the drain current (Ids) -gate voltage (Vgs) characteristics of the TFT, a bump, that is, a hump accompanying the parasitic characteristics due to the ON of the subchannel TFT appears.

  Then, the occurrence of the hump as described above makes the problem that a desired threshold necessary for the circuit cannot be obtained or the operating point of the circuit is shifted becomes remarkable.

Therefore, a thin film transistor is known in which a gate electrode is disposed so as to surround a source region of an active layer, and a drain region is disposed so as to surround the gate electrode (see, for example, Patent Document 1).
JP 2003-197915 A

  However, in the above-described thin film transistor, it is possible to prevent overlapping of pattern edges in the channel region of the active layer, so that there is a certain effect in suppressing parasitic characteristics by subchannel TFTs on both sides of the channel region, but the source region is not Enclosing the gate electrode and surrounding the gate electrode with the drain region increases the overall structure, which is disadvantageous when miniaturizing the thin film transistor.

  The present invention has been made in view of these points, and an object of the present invention is to provide a thin film transistor and a method for manufacturing the same capable of suppressing characteristic deterioration while enabling miniaturization.

  The present invention includes an insulating substrate, a semiconductor thin film provided on the insulating substrate, a sidewall insulating film provided on the insulating substrate surrounding the semiconductor thin film, and the sidewall insulating film and the semiconductor thin film. A gate insulating film provided so as to cover the gate insulating film and a gate electrode provided on the semiconductor thin film via the gate insulating film are provided.

  Then, a sidewall insulating film is provided surrounding the semiconductor thin film provided on the insulating substrate, and a gate insulating film is provided to cover the semiconductor thin film and the sidewall insulating film.

  According to the present invention, ON at the side of the semiconductor thin film can be suppressed, so that characteristic deterioration can be suppressed even when miniaturization is attempted.

  The configuration of the thin film transistor according to the first embodiment of the present invention will be described below with reference to FIGS.

  In FIG. 3, reference numeral 1 denotes a liquid crystal panel which is a liquid crystal display device as a flat display device. The liquid crystal panel 1 is a liquid crystal display (LCD), and has a substantially rectangular shape having a glass substrate 2 as an insulating substrate. A flat array substrate 3 is provided. On the surface of the glass substrate 2 of the array substrate 3, a plurality of scanning lines (not shown) spaced in parallel at equal intervals along the width direction of the glass substrate 2 and along the vertical direction of the glass substrate 2. A plurality of signal lines spaced in parallel at equal intervals are wired orthogonally and provided in a lattice shape.

  Further, a pixel 5 is provided in each of the regions partitioned and surrounded by these scanning lines and signal lines. These pixels 5 are each provided with a mesa-type top gate type thin film transistor (TFT) 6 as a switching element, a pixel electrode 7, and an auxiliary capacitor (not shown) which is a pixel auxiliary capacitor as a storage capacitor. Here, each pixel electrode 7 is electrically connected to the thin film transistor 6 in the same pixel 5, and is controlled by the thin film transistor 6.

  An undercoat layer (not shown) composed of a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is formed on the surface of the glass substrate 2, and polysilicon (p−) is formed on the undercoat layer. An island-shaped active layer 12 which is a semiconductor layer as a semiconductor thin film made of Si) is provided. The active layer 12 is made of polysilicon which is a polycrystalline semiconductor formed by crystallization of amorphous silicon (a-Si) which is an amorphous semiconductor by excimer laser annealing. A channel region 14 is provided at the center in the width direction of the active layer 12, and a source region 15 and a drain region 16 are provided on both sides of the channel region 14.

  Further, as shown in FIGS. 1 and 2, a sidewall insulating film 18 is provided around the active layer 12 so as to surround the periphery. The sidewall insulating film 18 is, for example, a silicon nitride film, is self-aligned along the side of the active layer 12, and is formed in a frame shape on the surface of the glass substrate 2 along the periphery of the active layer 12 in plan view. The active layer 12 is formed without a gap.

  On the active layer 12 and the sidewall insulating film 18, an insulating gate insulating film 21 is formed over the undercoat layer, and the gate insulating film facing the channel region 14 of the active layer 12 is formed. On the gate 21, a gate electrode 22 is stacked.

  Here, the gate insulating film 21 is, for example, a silicon oxide film, and is formed such that the thickness of the surface of the active layer 12, that is, the portion located at the upper part, is smaller than the thickness of the sidewall insulating film 18. In other words, the thickness of the sidewall insulating film 18 is larger than that of the gate insulating film 21 located above the active layer 12.

  The gate electrode 22 is integrally connected to the scanning line. The gate electrode 22, the gate insulating film 21, the active layer 12, and the sidewall insulating film 18 form a thin film transistor 6 that is a switching element.

  Further, as shown in FIG. 3, an interlayer insulating film 25 is laminated on the gate insulating film 21 of the thin film transistor 6 so as to cover the gate electrode 22. The interlayer insulating film 25 and the gate insulating film 21 have first contact holes 27 and 28 that pass through the interlayer insulating film 25 and the gate insulating film 21 and communicate with the source region 15 and the drain region 16 of the active layer 12. Is provided. A source electrode 31 is stacked on the interlayer insulating film 25 so as to cover the first contact hole 27 penetrating the source region 15 of the active layer 12, and the source electrode 31 is electrically connected to the source region 15 of the active layer 12. It is connected. Further, a drain electrode 32 is laminated on the interlayer insulating film 25 so as to cover the first contact hole 28 penetrating the drain region 16 of the active layer 12, and the drain electrode 32 is electrically connected to the drain region 16 of the active layer 12. It is connected to the.

  Further, a passivation film 33 is laminated on the interlayer insulating film 25 so as to cover the source electrode 31 and the drain electrode 32, and the second passivation film 33 penetrates the passivation film 33 and communicates with the drain electrode 32. A contact hole 34 is provided. Then, the pixel electrode 7 is laminated on the passivation film 33 so as to cover the second contact hole 34, and the pixel electrode 7 is electrically connected to the drain electrode 32 through the second contact hole 34. Furthermore, an alignment film 35 made of alignment-treated polyimide is laminated on the passivation film 33 so as to cover the pixel electrode 7.

  Further, a counter substrate 41 is disposed to face the alignment film 35. The counter substrate 41 includes a glass substrate 42 having a substantially transparent translucency. A color filter layer 43 is laminated on the entire surface of the glass substrate 42 facing the alignment film 35, and a counter electrode 44 is laminated on the color filter layer 43. Further, an alignment film 45 made of alignment-treated polyimide is laminated on the counter electrode 44. A liquid crystal composition 47 is injected into a liquid crystal sealing region 46 between the alignment film 35 of the array substrate 3 and the alignment film 45 of the counter substrate 41 to provide a liquid crystal layer 48 as a light modulation layer. .

  Next, the function and effect of the first embodiment will be described.

  In the mesa-type thin film transistor 6, electrolysis is generally concentrated on the side wall portion of the active layer 12. Therefore, when the thin film transistor 6 is miniaturized to increase the functionality of the thin film transistor 6, it is formed on the side wall portion of the active layer 12. The sub-channel TFT (Sub Channel TFT), which is a parasitic transistor, is more easily turned on than the surface side of the channel region 14 of the active layer 12.

  Since the sub-channel TFT is easily turned on in this way, the drain current (Ids) −gate voltage (Vgs) as in the conventional TFT characteristics shown in FIG. In the characteristics, a bump, that is, a hump occurs.

  Therefore, in the first embodiment, the sidewall insulating film 18 is formed so as to surround the side portion of the active layer 12.

  As a result, the turn-on of the subchannel TFT on the side of the active layer 12 is delayed, and the turn-on on the surface side in the channel region 14 of the active layer 12 is relatively accelerated. The influence of the current is less likely to appear in the TFT characteristics, generation of parasitic characteristics can be suppressed, and characteristic deterioration of the thin film transistor 6 can be suppressed.

  Specifically, by making the thickness of the sidewall insulating film 18 larger than that of the gate insulating film 21 on the surface side of the active layer 12, the influence of the parasitic current due to the ON of the subchannel TFT does not appear in the TFT characteristics (FIG. 4). Further, it is possible to prevent deterioration of characteristics of the thin film transistor 6 and obtain desired TFT characteristics.

  In addition, by obtaining desired TFT characteristics in this way, a threshold necessary for the circuit can be obtained, and the operation point of the circuit is not shifted, and the liquid crystal panel 1 has stable operation and high reliability. Can be obtained.

  Further, since the active layer 12 is simply surrounded by the sidewall insulating film 18, the thin film transistor 6 is not unnecessarily large, which is advantageous when the thin film transistor 6 is miniaturized.

  Next, the configuration of the thin film transistor according to the second embodiment will be described with reference to FIGS. In addition, about the structure and effect | action similar to the said 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  In the thin film transistor 6 of the second embodiment, a sidewall protective film 51 such as a silicon oxide film is formed so as to cover the active layer 12, and the sidewall insulating film 18 surrounds the sidewall protective film 51 and the active layer 12. Is formed.

  Next, a method for manufacturing the thin film transistor of the second embodiment will be described.

  First, as shown in FIG. 6, an amorphous silicon layer is deposited on a glass substrate 2 having an undercoat layer (not shown) formed on the surface thereof by, for example, a plasma CVD (Chemical Vapor Deposition) method. After forming a polysilicon thin film by annealing or the like, the polysilicon thin film is processed by, for example, photoetching to form an active layer 12 (semiconductor thin film forming step).

  Next, as shown in FIG. 7, a protective film M1 which is a silicon oxide film is formed on the glass substrate 2 so as to cover the active layer 12 (protective film forming step).

  Further, as shown in FIG. 8, a sacrificial film M2 which is a silicon nitride film as an insulating film is formed on the glass substrate 2 so as to cover the active layer 12 and the protective film M1 (insulating film forming step). At this time, thermal annealing or the like may be performed to improve the characteristics.

  Further, the entire surface of the sacrificial film M2 is etched by RIE (Reactive Ion Etching), and the sidewall insulating film 18 (FIG. 9) is formed of the sacrificial film M2. At this time, since the selection ratio between the silicon nitride film and the silicon oxide film is as small as 1/2 to 1/3, the protective film M1 on the surface of the active layer 12 is also etched, and the side wall protective film is formed on the side of the active layer 12 51 is formed (side wall forming step).

  Next, as shown in FIG. 10, the active layer 12, the sidewall insulating film 18 and the sidewall protective film 51 are covered, and the gate insulating film 21 is formed by, for example, PE-CVD or ECR (Electron-Cyclotron Resonance) -CVD. Form (gate insulating film forming step). Note that the gate insulating film 21 formed in this gate insulating film forming step is smaller in thickness than the sacrificial film M2 (FIG. 8) for forming the sidewall protective film 51. In other words, the sacrificial film M2 formed in the insulating film forming process has a larger film thickness than the gate insulating film 21 formed in the gate insulating film forming process.

  Then, as shown in FIG. 5, for example, a molybdenum-tantalum alloy (Mo-Ta) or a molybdenum-tungsten alloy (Mo-W) is sputtered on the active layer 12 via the gate insulating film 21. Then, after forming a predetermined metal layer, gate patterning is performed to form the gate electrode 22 (gate electrode forming step).

  Thereafter, as in the conventional method for manufacturing a mesa type top gate TFT, the interlayer insulating film 25, the first contact holes 27, 28, the electrodes 31, 32, the passivation film 33, the second contact hole 34, the pixel electrode 7 and the alignment film 35 are sequentially formed and attached with the alignment film 45 side of the counter substrate 41 facing each other, and then a liquid crystal layer 48 is formed between the alignment film 35 of the array substrate 2 and the alignment film 45 of the counter substrate 41. Insert and seal. Further, the array substrate 2 and the counter substrate 41 are combined with various members such as a system circuit, a polarizing plate, and a backlight (not shown) to complete the liquid crystal panel 1.

  As described above, according to the second embodiment, since the sidewall insulating film 18 is formed so as to surround the active layer 12, the first embodiment has the same configuration as that of the first embodiment. The same operational effects as those of the first embodiment can be obtained.

  Further, by forming the side wall protective film 51 with the protective film M1 provided on the glass substrate 2 so as to cover the active layer 12, the surface of the active layer 12 is beaten during the RIE at the time of forming the side wall insulating film 18. This can be suppressed by the protective film M1, and etching damage at the interface between the sacrificial film M2 to be the sidewall insulating film 18 and the surface side of the active layer 12 can be suppressed.

  In addition, by providing the sidewall protective film 51 so as to surround the active layer 12, it is possible to more reliably prevent the subchannel TFT from being turned on at the side of the active layer 12.

  In each of the above embodiments, if the side wall insulating film 18 can increase the resistance value on the side of the active layer 12 more than the gate insulating film 21 on the surface side of the channel region 14 of the active layer 12, the side wall insulating film 18 is not necessarily required. It is not necessary to make the film thickness larger than that of the gate insulating film 21 on the surface of the active layer 12.

  Further, the flat display device can be applied to an organic EL display device or the like.

  In addition to the array substrate 2, the above configuration can be applied as long as the substrate device forms the thin film transistor 6.

1 is an explanatory cross-sectional view illustrating a thin film transistor according to a first embodiment of the present invention. It is a top view which shows a thin-film transistor same as the above. It is explanatory sectional drawing which shows the flat display apparatus provided with the thin film transistor same as the above. It is a characteristic graph of a thin-film transistor same as the above. It is explanatory sectional drawing which shows the gate electrode formation process of the manufacturing method of the thin-film transistor of the 2nd Embodiment of this invention. It is explanatory sectional drawing which shows the semiconductor thin film formation process of the manufacturing method of a thin-film transistor same as the above. It is explanatory sectional drawing which shows the protective film formation process of the manufacturing method of a thin-film transistor same as the above. It is explanatory sectional drawing which shows the insulating film formation process of the manufacturing method of a thin-film transistor same as the above. It is explanatory sectional drawing which shows the side wall formation process of the manufacturing method of a thin-film transistor same as the above. It is explanatory sectional drawing which shows the gate insulating film formation process of the manufacturing method of a thin-film transistor same as the above.

Explanation of symbols

2 Glass substrate as an insulating substrate 6 Thin film transistor
12 Active layer as a semiconductor thin film
18 Side wall insulating film
21 Gate insulation film
22 Gate electrode
51 Side wall protective film
M1 protective film
M2 Sacrificial film as insulating film

Claims (6)

An insulating substrate;
A semiconductor thin film provided on the insulating substrate;
A sidewall insulating film provided on the insulating substrate so as to surround the semiconductor thin film;
A gate insulating film provided to cover these sidewall insulating films and the semiconductor thin film;
A thin film transistor, comprising: a gate electrode provided on the semiconductor thin film through the gate insulating film. The thin film transistor according to claim 1, wherein the sidewall insulating film is formed to be thicker than the gate insulating film on the semiconductor thin film. A sidewall protective film is formed by a protective film provided on an insulating substrate so as to cover the semiconductor thin film, and at least surrounds the periphery of the semiconductor thin film.
The thin film transistor according to claim 1, wherein the sidewall insulating film is provided so as to surround the sidewall protective film and the semiconductor thin film. A semiconductor thin film forming step of forming a semiconductor thin film on an insulating substrate;
An insulating film forming step of covering the semiconductor thin film and forming an insulating film on the insulating substrate;
A sidewall forming step of etching the insulating film to form a sidewall insulating film surrounding the semiconductor thin film; and
Forming a gate insulating film covering the semiconductor thin film and the sidewall insulating film; and
And a gate electrode forming step of forming a gate electrode on the semiconductor thin film through the gate insulating film. The method for manufacturing a thin film transistor according to claim 4, wherein the side wall forming step forms an insulating film having a larger film thickness than the gate insulating film formed in the gate insulating film forming step. A protective film forming step of covering the semiconductor thin film and forming a protective film on the insulating substrate between the semiconductor thin film forming step and the insulating film forming step;
The insulating film forming step forms an insulating film covering the semiconductor thin film and the protective film,
6. The method of manufacturing a thin film transistor according to claim 4, wherein the side wall forming step forms the side wall insulating film by etching the insulating film, and forms the side wall protective film by etching the protective film.

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