JP2007200496A5 - - Google Patents

Claims (15)

A semiconductor memory device in which memory cells are arranged,
An internal voltage generation circuit for generating a voltage signal used in the memory cell;
A plurality of program circuits for outputting a signal for adjusting a voltage value of a voltage signal generated by the internal voltage generation circuit;
A select circuit for selecting a signal output from each of the program circuits according to a selection signal;
And the internal voltage generation circuit generates a voltage signal having a voltage value corresponding to the signal selected by the selection circuit.   2. The semiconductor memory device according to claim 1, wherein the internal voltage generation circuit is a boost voltage generation circuit.   The semiconductor memory device according to claim 1, wherein the program circuit includes a nonvolatile memory element. 4. The semiconductor memory device according to claim 1, wherein a plurality of the program circuits adjust a voltage value of a voltage signal generated in the internal voltage generation circuit to a first voltage value. A semiconductor memory device comprising: a program circuit with programmed settings; and a program circuit with programmed settings for adjusting a voltage value of a voltage signal generated by the internal voltage generating circuit to a second voltage value .   4. The semiconductor memory device according to claim 1, wherein an internal voltage for adjusting a voltage value of a voltage signal generated by the internal voltage generation circuit to a voltage value according to a control signal input from the outside. A semiconductor memory device further comprising an internal voltage setting circuit for outputting a voltage setting signal, wherein the select circuit further has a function of selecting a signal output from the internal voltage setting circuit in accordance with a selection signal.   6. The semiconductor memory device according to claim 5, wherein the internal voltage setting circuit includes a register circuit for setting the internal voltage setting signal, and the register circuit is configured to allow serial input of the control signal. A semiconductor memory device.   5. The semiconductor memory device according to claim 4, further comprising an external terminal for inputting a selection signal from the outside.   5. The semiconductor memory device according to claim 4, further comprising a test mode circuit for decoding a test mode signal input from the outside and generating a selection signal.   7. The semiconductor memory device according to claim 5, further comprising an external terminal for inputting a selection signal from the outside.   7. The semiconductor memory device according to claim 5, further comprising a test mode circuit that decodes a test mode signal input from the outside and generates a selection signal. 8. The method of testing a semiconductor memory device according to claim 7, wherein a setting for adjusting a voltage value of a voltage signal generated by the internal voltage generation circuit to the second voltage value is programmed from the external terminal. A test of a semiconductor memory device, wherein a test signal is input using a voltage signal of the second voltage value by inputting a selection signal that causes the selection circuit to select a signal from any of the program circuits Method. 9. The method of testing a semiconductor memory device according to claim 8, wherein a setting for adjusting a voltage value of a voltage signal generated by the internal voltage generation circuit to the second voltage value is programmed. A semiconductor memory, wherein a test mode signal for causing the select circuit to select a signal from a program circuit is input to the test mode circuit, and a test is performed using the voltage signal of the second voltage value How to test the equipment.   10. The method of testing a semiconductor memory device according to claim 9, wherein a control signal for adjusting a voltage value of a voltage signal generated by the internal voltage generation circuit to a desired voltage value is input to the internal voltage setting circuit. In addition, a semiconductor memory is characterized in that a test signal is inputted from the external terminal and a selection signal for selecting the signal from the internal voltage setting circuit to the selection circuit is used to perform a test using a voltage signal having a desired voltage value. How to test the equipment.   11. The method of testing a semiconductor memory device according to claim 10, wherein a control signal for adjusting a voltage value of a voltage signal generated by the internal voltage generation circuit to a desired voltage value is input to the internal voltage setting circuit. A test mode signal for causing the select circuit to select a signal from the internal voltage setting circuit is input to the test mode circuit, and a test is performed using a voltage signal having a desired voltage value. A method for testing a semiconductor memory device.   15. The method of testing a semiconductor memory device according to claim 11, wherein the test to be performed is a burn-in test.