JP2007189553A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing an area of a semiconductor chip in which wiring is simplified. <P>SOLUTION: The semiconductor integrated circuit comprises a switch circuit network providing a plurality of pairs in which one of switch elements 12a to 12l for switching signal paths and one of memory elements 11a to 11l for holding open close controlling signals of the switch elements 12a to 12l are made to be one pair. Each of the memory elements 11a to 11l has a latch circuit, and is linked mutually so as the open close controlling signals to be transmitted sequentially between the memory elements 11a to 11l. Further, in each of the adjacent memory elements 11a to 11l, writing signal lines different from each other are to be connected alternatively. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit that performs function selection by controlling a large number of switch elements and switching signal paths.

  Conventionally, a plurality of circuit blocks constituted by a plurality of functional elements are built in a semiconductor substrate. Each input signal and output signal of the circuit block is guided to a switch matrix comprising switch elements that can electrically control the open / close state. The switch element can change the connection state of each circuit block. A semiconductor integrated circuit that realizes such a plurality of functions with one semiconductor chip has been proposed.

  However, in such a semiconductor integrated circuit, in a circuit configuration that individually designates the open / close state of the switch element, in addition to the circuit and wiring necessary for the original operation, many circuits are used for controlling the open / close state of the switch element. And wiring is required. Therefore, there is a problem that the area of the semiconductor chip is increased, and the area of the semiconductor integrated circuit including the semiconductor chip is increased. In addition, there is a disadvantage that the cost of a semiconductor chip having a large area increases.

  As means for solving this problem, for example, in Patent Document 1, as shown in FIG. 8, the memory element 110 and the switch element 120 are integrally arranged, and the set of the memory element 110 and the switch element 120 is illustrated in FIG. As shown in FIG. 9, by arranging in a matrix, the memory element 110 is connected to the signal lines 101 and 102 so that the switching control information is sequentially transmitted between the memory elements 110 (hereinafter referred to as shift register operation). A semiconductor integrated circuit 100 is disclosed. As a result, the connection of the memory element 110 that allows the shift register operation to be performed can be simplified, and an increase in the area of the semiconductor chip can be suppressed.

In the invention disclosed in Patent Document 2, as shown in FIG. 10, the setting of the open / close control information for the memory element 210 is set by signal lines 201 and 202 by individual wiring conductors, and the memory elements 210. The memory elements 210 are connected so that a shift register operation is performed between the 210.
Japanese Patent Publication No. 7-3836 (announced on January 18, 1995) JP 61-147699 A (published July 5, 1986)

  However, in the configuration of the conventional semiconductor integrated circuit as disclosed in Patent Document 1, a D-type flip-flop that holds data at an input terminal in synchronization with a clock is used as a memory element. As shown in FIG. 8, the memory element 110 composed of such a D-type flip-flop generally includes two latch circuits 112 and 112 each composed of two inverters 111 and 111, and four transfer gate MOSFETs 113. -Since it is comprised by 113 * 113 * 113, there exists a problem that the number of parts increases and the area of a semiconductor chip becomes large.

  Furthermore, as the number of switch elements 120 increases, the number of memory elements 110 for holding the opening / closing control signals of the switch elements 120 also increases, resulting in a further increase in the area of the semiconductor chip. ing.

  Further, in the configuration of the conventional semiconductor integrated circuit as disclosed in Patent Document 2, in order for the memory elements 210 to hold the opening / closing control information, signals that are individual wiring conductors for each memory element 210. Lines 201 and 202 are required. For this reason, there is a disadvantage that the area of the semiconductor chip increases due to the wiring.

  The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a semiconductor integrated circuit in which wiring is simplified and the area of a semiconductor chip can be reduced.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention is provided with a plurality of sets of switch elements for switching signal paths and memory elements for holding switching control signals for the switch elements. In the semiconductor integrated circuit having the switch circuit network, each of the memory elements has one latch element, and is connected to each other so that the switching control information can be sequentially transmitted between the memory elements. The memory element is characterized in that different write signal lines are alternately connected.

  According to the above invention, the memory elements are connected to each other so that the switching control information can be sequentially transmitted between the memory elements. For this reason, the memory element does not need to have two latch elements as in the prior art, and only needs to have one latch element. As a result, the area of the memory element can be reduced, and as a result, an increase in the area of the semiconductor chip can be suppressed. Therefore, the switch circuit network can be formed on a large scale without increasing the area of the semiconductor chip.

  Further, although the memory element has a simple configuration including one latch element, shift register operations can be performed between the memory elements by alternately connecting different write signal lines in adjacent memory elements. It is possible to perform the same operation as that of the configuration. Further, conventionally, two write signal lines are required for each memory element. However, in the present invention, one write signal line is sufficient for each memory element, so that wiring is crowded. Can be prevented.

  In the semiconductor integrated circuit of the present invention, the switch element having an open / close logic that matches the input logic of the memory element is adjacent to the input circuit of the next-stage memory element to which an output signal from the memory element is input. It is more preferable that they are arranged.

  As a result, the wiring of the next-stage memory element to which the output signal from the memory element is input and the switch element can be arranged closer to each other.

  Therefore, wiring for the shift register operation is sufficient for wiring between the switch element and the input circuit of the memory element at the next stage. In addition, the wiring layer to the switch element to which the output signal from the memory element is input can be utilized as a wiring for connecting the switching control information to each other so that the switching control information can be sequentially transmitted between the memory elements.

  As a result, the wiring for the shift register operation can be further reduced, and the wiring layer can be used more efficiently.

  In the semiconductor integrated circuit of the present invention, it is more preferable that the switch element is composed of a semiconductor switch element in which two types of switch elements of an N-type MOSFET and a P-type MOSFET are combined.

  Thus, the switch element is a combination of one type of switch element having switching logic that matches the input logic of the memory element and the other type of switch element having switching logic that does not match the input logic of the memory element. ing.

  As a result, one type of switching element having switching logic that matches the input logic of the memory element and the input circuit of the next-stage memory element to which the output signal from the memory element is input are arranged closer to each other. be able to.

  As a result, it is always possible to further reduce the wiring for the shift register operation, and the wiring layer can be used more efficiently.

  In the semiconductor integrated circuit of the present invention, the switching circuit input / output control signal input circuit and the input circuit of the next memory element to which the output signal from the memory element is input form the gate of the MOSFET. More preferably, wiring is performed using layers.

  As a result, the wiring of the input circuit is performed using the layer constituting the gate of the MOSFET, not the wiring layer formed separately, and the wiring layer can be effectively used for other purposes.

  In the semiconductor integrated circuit of the present invention, as described above, each memory element has one latch element, and is connected to each other so that switching control information can be sequentially transmitted between the memory elements, and further adjacent to each other. In each memory element, different write signal lines are alternately connected.

  Therefore, it is possible to provide a semiconductor integrated circuit in which the wiring is simplified and the area of the semiconductor chip can be reduced.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. 1 to 4 as follows.

  First, the configuration of the switch circuit network of the semiconductor integrated circuit according to the present embodiment will be described.

  As shown in FIG. 1, the switch circuit network of the semiconductor integrated circuit according to the present embodiment includes memory elements 11a to 11l, switch elements 12a to 12l as semiconductor switch elements, signal lines 13a to 13c, Lines 14a to 14d.

  For convenience of explanation, the signal lines 13, the signal lines 14, the memory elements 11, and the switch elements 12 as semiconductor switch elements are collectively referred to as the component parts.

  As shown in FIG. 1, the signal line 13 and the signal line 14 are signal lines for analog signals or digital signals located in different wiring layers. Further, the signal line 13 and the signal line 14 are not electrically connected to each other in a normal state.

  Further, the switch elements 12 are arranged in a matrix as shown in FIG. When the switch function is turned on, the switch element 12 uses a switch element 12 having a low level resistance that does not cause a problem in electrical connection. Therefore, the signal line 13 and the signal line 14 can be electrically connected by the switch element 12.

  Specifically, the switch element 12a can connect the signal line 13a and the signal line 14a, and the switch element 12g can connect the signal line 13b and the signal line 14c.

  On the other hand, like the switch element 12, the memory element 11 is also arranged in a matrix and connected to the switch element 12, as shown in FIG. The memory element 11 can hold an open / close control signal for the switch element 12.

  In the present embodiment, as shown in FIG. 1, each of the memory elements 11... Is connected to each other in series, and sequentially holds the open / close control signal to the next memory element 11 (hereinafter “the next stage”). The shift register is sent to the memory element 11)).

  A more detailed configuration of the memory element 11 will be described with reference to FIG. As shown in the figure, the memory element 11 is assumed to be manufactured by a CMOS (Complementary Metal Oxide Semiconductor) process, and includes an inverter 20 and a latch circuit 29 as a latch element. Yes.

  The inverter 20 is configured by connecting a P-type MOSFET (MOS Field-Effect Transistor) 27 and an N-type MOSFET 26. The latch circuit 29 is configured by connecting a P-type MOSFET 21a, an N-type MOSFET 22a, a P-type MOSFET 21b, and an N-type MOSFET 22b.

  On the other hand, the switch element 12 is configured by connecting an N-type MOSFET 24 and a P-type MOSFET 25 in parallel.

  As shown in FIG. 1, the switch circuit network of the semiconductor integrated circuit of the present embodiment is configured by arranging the memory element 11 and the switch element 12 as a set and arranging a plurality of sets in a matrix. Yes.

  Further, as shown in FIG. 3, the pair of memory elements 11 and the switch element 12 are connected to each other by electrically connecting the P-type MOSFET 25 of the switch element 12 and the input circuit of the memory element 11 of the next stage. It is configured so that it can be electrically connected to the next-stage memory element 11 and the next-stage switch element 12.

  Next, the operation of the switch circuit network of the semiconductor integrated circuit will be described.

  As shown in FIG. 1, the output signal of the memory element 11a is inputted to the memory element 11b at the same time as being inputted to the switch element 12a, and the output signal of the memory element 11b is inputted to the switch element 12b at the same time. 11c is input.

  Therefore, as shown in FIG. 1, if columns of memory elements 11 arranged in series with each other can perform a shift register operation, for example, the memory element 11d holds desired data (opening / closing control signal). For this, desired data may be input to the input signal 17a of the memory element 11a. As a result, a write signal 15 and a write signal 16 which will be described later are controlled, and an operation of sequentially sending the data to the next memory element 11 is performed until the desired data reaches 11d.

  The latch state of the latch circuit 29 shown in FIG. 2 is changed by, for example, inputting the write signal 15 to the memory element 11, turning on the N-type MOSFET 23, and further outputting the output signal from the inverter 20 to the latch circuit 29. This is done by inputting.

  Next, the output signal of the inverter 20 is input to the switch element 12.

  Specifically, when the P-type MOSFET 21a included in the latch circuit 29 is on, the N-type MOSFET 22a is off, the P-type MOSFET 21b is off, and the N-type MOSFET 22b is on, the latch circuit 29 maintains a balance. Stable state.

  On the other hand, when both the N-type MOSFET 24 and the P-type MOSFET 25 included in the switch element 12 are in an off state, that is, when the switch element 12 is in an open state, first, a signal set to a low level voltage is applied to the inverter 20 of the memory element 11. Then, a signal in which the write signal 15 is set to a high level voltage is input to the N-type MOSFET 23. As a result, the N-type MOSFET 23 is turned on, and the input signal to the P-type MOSFET 21a and the N-type MOSFET 22a is set to a high level voltage.

  As a result, the P-type MOSFET 21a is turned off, the N-type MOSFET 22a is turned on, the P-type MOSFET 21b is turned on, and the N-type MOSFET 22b is turned off. The latch state of the latch circuit 29 is inverted and the switch element 28 is closed. Changed to

  That is, when the input signal to the inverter 20 of the memory element 11 is set to a low level voltage and the write signal 15 to the N-type MOSFET 23 is set to a high level voltage, the switch element 12 is turned on (closed state). On the other hand, when the input signal to the inverter 20 of the memory element 11 is set to a high level voltage and the write signal 15 to the N-type MOSFET 23 is set to a high level voltage, the switch element 12 is turned off (opened). .

  In order to operate the memory element 11 as shown in FIG. 2 as a shift register, as shown in FIGS. 1 and 3, two kinds of write signal 15 and write signal 16 are prepared, and N of the memory element 11 is alternately arranged. It is necessary to connect to the type MOSFET 23.

  Here, the operations of the write signal 15 and the write signal 16 will be described with reference to FIG. 4A schematically shows the state of the input signal 17a to the memory element 11a. Similarly, (b) schematically shows a write signal 15, and (c) schematically shows an output signal from the memory element 11a, that is, an input signal to the memory element 11b. Further, (d) schematically shows the state of the write signal 16, and (e) schematically shows the state of the output signal from the memory element 11b, that is, the state of the input signal to the memory element 11c. is there.

  Here, as shown in FIG. 4, the write signal 15 is synchronized with the data D1 to D5 of the input signal 17a of the memory element 11a. Thereby, the memory element 11a outputs the data D1 to D5 at a timing synchronized with the write signal 15. The output signal from the memory element 11a output at such timing is input to the memory element 11b. When the write signal 16 is further synchronized with the data D1 to D5 input to the memory element 11b, the memory element 11b outputs the data D1 to D5 at a timing synchronized with the write signal 16. In FIG. 4, only the memory element 11b is described, but this operation is repeated for all the memory elements 11 in the next stage so that the data D1 to D5 are sequentially transferred by the shift register operation.

  As described above, by using the memory element 11 as described above, the number of MOSFETs in the switch circuit network of the semiconductor integrated circuit can be significantly reduced as compared with the D-type flip-flop.

  In addition, if two types of write signals 15 and 16 are prepared and the above-described control is performed while greatly reducing the number of MOSFETs, the switching control signal for the switch element can be set by a shift register operation. Therefore, the wiring for setting the switching control signal for the switch element can be reduced to the same extent as when the D-type flip-flop is used.

  Here, if the input logic and switching logic of the next-stage memory element 11 and the switch element 12 are appropriately used, the area of the switch circuit network of the semiconductor integrated circuit in this embodiment can be further reduced.

  For example, as shown in FIG. 3, when the write signal 15 set to a low level voltage is input to the memory element 11, the switch element 12 is designed to be turned on. In this case, a switch element having such a characteristic that the switch element 12 is turned on by the write signal 15 set to a low level voltage is arranged adjacent to the input circuit of the memory element 11 in the next stage. Since the write signal 16 is input to the memory element 11 at the next stage, the switch open / close control signal can be sequentially transmitted to the next memory element 11 by the shift register operation.

  On the other hand, when the write signal 15 set to a high level voltage is input to the memory element 11, the switch element 12 can be designed to be turned on. In this case, a switch element having such a characteristic that the switch element 12 is turned on by the write signal 15 set to a high level voltage is arranged adjacent to the input circuit of the memory element 11 in the next stage. Since the write signal 16 is input to the memory element 11 at the next stage, a switch open / close control signal can be sequentially transmitted to the memory element 11 at the next stage by a shift register operation.

  Thereby, by making the input logic of the memory element 11 coincide with the opening / closing logic of the switch element 12, the wiring for performing the shift register operation can be made very short.

  As described above, when an element is actually formed on a semiconductor substrate, the switch element having the same logic of the positive logic or the negative logic is arranged in the vicinity of the input circuit of the memory element 11 at the next stage, The area of the switch circuit network of the semiconductor integrated circuit can be further reduced.

  Here, the logic is as described below.

  Information processing in digital circuits is generally performed by logical operations or the like. This is a binary representation of the “high level (high)” and “low level (low)” of the voltage in the circuit, corresponding to “1” and “0” respectively, and logical operations such as AND, OR, NOT, etc. Is to do. The binary value used for this logical operation is called logic.

  Corresponding positive voltage pulses to “1” and negative voltage pulses to “0” is called positive logic, and conversely, positive voltage pulses to “0” and negative voltage pulses to “1”. This is called negative logic.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 are given the same reference numerals, and explanation thereof is omitted.

  FIGS. 5A and 5B are cross-sectional views showing an example of the N-type MOSFET 47 and the P-type MOSFET 48 formed by the CMOS process in the present embodiment.

  As shown in FIG. 5A, the N-type MOSFET 47 is configured by forming an N-type diffusion region 42 on a P-type semiconductor substrate 41 and forming a gate 43a across an insulating film 46. .

  Further, as shown in FIG. 5B, the P-type MOSFET 48 is formed by forming an N-type well 45 on the P-type semiconductor substrate 41, further forming a P-type diffusion region 44, and sandwiching the insulating film 46 therebetween. It is comprised by forming 43b. The gates 43a and 43b are usually formed of a polysilicon layer, but the polysilicon layer has a larger resistance value than a metal layer for wiring. However, since the gate input impedance is very large, there is no particular problem even if it is used for wiring as long as the short distance gates are connected.

In the present embodiment, the switch element 12 is not a switch element as a semiconductor switch element in which an N-type MOSFET and a P-type MOSFET are connected in parallel as in the first embodiment, but the N-type MOSFET 47 or the P-type MOSFET 48. Is used alone as a switch element.

  In the present embodiment, since the memory element 11 has negative logic input logic, as shown in FIG. 6, a P-type MOSFET 25 having negative logic switching logic is used alone as the switch element 12. It may be arranged adjacent to the input circuit of the memory element 11 at the next stage.

  Thereby, by making the input logic of the memory element 11 coincide with the opening / closing logic of the switch element 12, the wiring for performing the shift register operation can be made very short.

  Further, in the case where the switch element 12 is designed to be turned on when the input signal of the memory element 11 is set to a high level voltage, there is no inverter 20 of the memory element 11 or the inverter 20 has two stages. There is a case where it is configured, or a case where the connection to the switch element 12 is reversed. In this case, the N-type MOSFET 26 may be used as the switch element 12 and the input circuit of the memory element 11 at the next stage may be disposed adjacently.

  Also, the wiring between the P-type MOSFET 25 and the input circuit of the memory element 11 at the next stage may be wired using a polysilicon layer (layer forming the gate of the MOSFET).

  Thereby, since the metal layer which is a wiring layer is not consumed, a wiring layer can be used effectively for another use.

  Further, the switch matrix composed of the switch elements configured as described above is applied to a circuit as shown in FIG. 7, for example. In the circuit shown in FIG. 7, signals from other blocks and circuit blocks 62, 63, 64 and 65 are connected to a switch matrix 66 composed of a plurality of switch elements 61, and necessary signals and circuit blocks are selectively connected. As a result, a circuit function according to need is realized.

  Further, the circuit shown in FIG. 7 is not limited to the application in the second embodiment described above, and can be applied to the first embodiment and an embodiment obtained by appropriately combining the respective technical means disclosed.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  The present invention is applicable to a semiconductor integrated circuit having a configuration in which a large number of switch elements are provided on a semiconductor substrate to switch signal paths.

1 is a wiring diagram schematically showing an embodiment of a semiconductor integrated circuit according to the present invention. It is a circuit diagram which shows the structure of the memory element and switch element of the said semiconductor integrated circuit. It is a circuit diagram which shows the connection state of the memory element and switch element in the said semiconductor integrated circuit. 3 is a timing chart showing an operation of a write signal in the semiconductor integrated circuit. (A) shows other embodiment of the semiconductor integrated circuit in this invention, and is sectional drawing which shows an example of N type MOSFET, (b) is sectional drawing which shows an example of P type MOSFET. It is a circuit diagram which shows the connection state of the memory element and switch element in the said semiconductor integrated circuit. It is a circuit diagram which shows an example of the circuit using the said semiconductor integrated circuit. It is a circuit diagram which shows typically the memory element and switch element in the conventional semiconductor integrated circuit. It is a wiring diagram which shows typically the wiring of the memory element and switch element in the said conventional semiconductor integrated circuit. It is a circuit diagram which shows typically the memory element and switch element in another conventional semiconductor integrated circuit.

Explanation of symbols

11 Memory Element 12 Switch Element (Semiconductor Switch Element, Switch Element)
13 signal line 14 signal line 15 write signal 16 write signal 17a input signal of memory element 11a 20 inverter 21a P-type MOSFET
21b P-type MOSFET
22a N-type MOSFET
22b N-type MOSFET
23 N-type MOSFET
24 N-type MOSFET (switch element)
25 P-type MOSFET (switch element)
26 N-type MOSFET
27 P-type MOSFET
29 Latch circuit (latch element)
41 P-type semiconductor substrate 42 N-type diffusion region 43a Gate 43b Gate 44 P-type diffusion region 45 N-type well 46 Insulating film 47 N-type MOSFET (switch element)
48 P-type MOSFET (switch element)
61 Switch element (semiconductor switch element, switch element)
62 circuit block 63 circuit block 64 circuit block 65 circuit block 66 switch matrix

Claims (4)

In a semiconductor integrated circuit comprising a switch circuit network in which a plurality of sets of switch elements for switching signal paths and memory elements for holding switching control signals of the switch elements are provided as a set,
Each memory element is
It has one latch element and is connected to each other so that switching control information can be sequentially transmitted between the memory elements, and different adjacent write signal lines are alternately connected to each adjacent memory element. A semiconductor integrated circuit.   The switch element having an open / close logic that matches the input logic of the memory element is disposed adjacent to an input circuit of a next-stage memory element to which an output signal from the memory element is input. The semiconductor integrated circuit according to claim 1.   3. The semiconductor integrated circuit according to claim 2, wherein the switch element is composed of a semiconductor switch element in which two types of switch elements of an N-type MOSFET and a P-type MOSFET are combined.   The input circuit for the switching control signal for the switch element and the input circuit for the next-stage memory element to which the output signal from the memory element is input are wired using a layer that forms the gate of the MOSFET. 4. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is characterized in that:

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