JP2007189095A - Method of manufacturing silicon multilayer wiring board, and method of evaluating silicon multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate film peeling and to appropriately make Al wiring into multiple layers when a photosensitive organic film is used for an interlayer insulating film. <P>SOLUTION: When multilayer wiring is manufactured on a silicon substrate by using the photosensitive organic film in the interlayer dielectric of an Al wiring layer 13, either of depositing pressure, substrate heating or heat treatment after depositing as a depositing condition of the Al film by sputtering when forming the Al wiring layer 13 is controlled so that the surface of the Al film becomes roughness of an unevenness shape, where a surface area increases. When the photosensitive organic film is formed on the Al wiring layer 13, both contact areas are increased, and both adhesivenesses are improved. Thus, film peeling of the photosensitive organic film is eliminated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a silicon multilayer wiring substrate using a photosensitive organic film as an interlayer insulating film of an integrated circuit using a silicon substrate typified by the semiconductor field and a silicon interposer substrate for SiP (System in Package), and silicon. The present invention relates to a method for evaluating a multilayer wiring board.

  In recent years, SiP has been realized by incorporating passive elements such as resistors, capacitors, and diodes in a printed circuit board, and in a functional LSI (Large Scale Integrated circuit), such as a conventional QFP (Quad Flat Package). The development of small components such as CSP (Chip Size Package) has progressed from large components, and miniaturization has been achieved from both printed circuit boards and mounted components.

However, in order to achieve further miniaturization, new technologies are required due to the limitations of photo accuracy and etching processes. For this reason, a technique for mounting a functional LSI on a silicon interposer substrate in a CSP or bare chip state instead of a conventional printed circuit board has been developed.
Since the silicon interposer substrate is manufactured in the same process as the LSI process, it is possible to mount resistors, capacitors, and diodes. Al (aluminum) -based conductive material is used for the wiring, and SiO ₂ (silicon oxide film) formed by plasma CVD (Chemical Vapor Deposition) is used for the interlayer insulating film.

Si0 ₂ is also referred to as P-Si0 _2. However, since P-Si0 ₂ is the relative dielectric constant εr is as large as 4.0 to 4.2, mounting and the RF (Radio Frequency) coil as high Q (Quality Factor) value is obtained as a mainstream future, few It is difficult to apply to a 10 GHz band high frequency device.
As a countermeasure, generally, SiOX whose dielectric constant is reduced to 2.9 to 3.5 by adding N (nitrogen atom), F (fluorine atom), or C (carbon atom) to the silicon oxide film. System materials are used.

Conventional P-SiO ₂ and SiOX-based materials have the advantage of being easily fitted to existing LSI processes, but can be broadly divided into (a) as shown in the manufacturing process diagram of the conventional silicon multilayer wiring board in FIG. Three processes are required: a film forming process of (c), a photo process of (d), and an etching process of (e) to (h). This manufacturing process will be described.
First, in the film forming process, (a) is an interlayer film forming process, in which a T-SiO ₂ layer 12, an Al wiring layer 13, and a CVD-SiO ₂ layer 14 are sequentially stacked on a Si substrate 11. (B) is a resist coating step, in which a resist is coated on the CVD-SiO ₂ layer 14 and prebaked in the prebaking step (c). Then, in the photo process, exposure / development is performed at a predetermined position 16 of the resist layer 15 in the exposure / development process in (d).

Next, in the etching step, (e) post-baking is performed in the post-baking step, and wet etching is performed up to a predetermined depth 17 on the CVD-SiO ₂ layer 14 in the interlayer film wet etching step (f). (G) In the interlayer film dry etching step, dry etching 18 is performed on the portion 17 of the wet etching process of the CVD-SiO ₂ layer 14, and the resist layer 15 is peeled off in the resist ashing step (h).

Since many processes are required in this way, the application of a photosensitive organic film (photosensitive polyimide film) that can be manufactured with existing equipment and can shorten the manufacturing process as shown in FIG. 8 was examined.
First, in the interlayer film coating step (a), the T-SiO ₂ 12 and the Al wiring layer 13 are sequentially laminated on the Si substrate 11, and the photosensitive organic film 21 is coated thereon. Then, pre-baking is performed in the pre-baking step (b), exposure / development is performed on the predetermined position 22 of the photosensitive organic film 21 in the photo step (c), and curing is performed by heat treatment in the curing step (d). .

Photosensitive organic films have been used as LSI surface protective films, but due to their superior material properties, in recent years, surface protective films for Si functional devices centered on MEMS (Mechan1ca1 E1ectric Machining System). More and more examples are applied as interlayer insulating films.
In addition, the photosensitive organic film can be applied to a thick film because the relative dielectric constant εr is as low as 2.6 to 2.9 and the stress is an order of magnitude lower than that of conventional P-SiO ₂ . Further, as shown in FIG. 7 above, the number of steps can be reduced to about 1/2 compared with the conventional P-SiO ₂ step, so that it is possible to reduce the number of layers between high-frequency devices and multilayer wiring devices with high functionality and low cost. It is a material that can be expected to be applied as a film.

As a method for manufacturing this type of conventional silicon multilayer wiring substrate, for example, there is a method described in Patent Document 1.
JP-A-5-304362

However, the photosensitive organic film used for manufacturing the above-described conventional silicon multilayer wiring board has much worse adhesion to the metal surface than P-SiO _2, and this point will be explained as follows. This is a problem in manufacturing a silicon multilayer wiring board using a conductive organic film.
The photosensitive organic film 21 is in close contact with the substrate of the Al wiring layer 13 as shown in FIGS. 9A-1 and 9A-2 in the photo process shown in FIG. 8C. In the curing process shown in FIG. 8 (d), moisture and photosensitive group components generated by the dehydration reaction are removed, and depending on the material, the photosensitive organic film 21 contracts by 10 to 50% (film reduction). ) Occurs.

Due to this film shrinkage, particularly at the interface between the metal surface and the organic film in the thin contact hole 32 of the Al wiring layer 13, as shown in FIGS. 9B-1 and 9B-2. Film peeling as indicated by gap is likely to occur.
In this portion, when there is no peeling, the interlayer insulating film (photosensitive organic film) 21 is covered when the Al wiring layer 33 is formed on the photosensitive organic film 21 as shown in FIG. It is possible.

  However, as shown in FIG. 10B, when peeling occurs at the interface, when the Al wiring layer 33 is formed, the Al to the interlayer insulating film 21 is formed at the step portion of the contact hole 32 as indicated by. The coverage of the wiring deteriorates, and a disconnection or loose contact state occurs. For this reason, since the contact resistance is open or in a high resistance state, the Al wiring cannot be multilayered.

  The present invention has been made in view of such problems, and when a photosensitive organic film is used as an interlayer insulating film, a silicon multilayer capable of appropriately multilayering Al wiring without the film peeling. An object of the present invention is to provide a method for manufacturing a wiring board and a method for evaluating a silicon multilayer wiring board.

In order to achieve the above object, a method for manufacturing a silicon multilayer wiring board according to claim 1 of the present invention is a silicon multilayer manufacturing method in which a multilayer wiring is manufactured on a silicon substrate using a photosensitive organic film as an interlayer insulating film of a metal wiring layer. In the method of manufacturing a wiring board, the surface of the metal film is subjected to any one of film formation pressure, substrate heating, and heat treatment after film formation, which are film formation conditions of the metal film by sputtering when forming the metal wiring layer. It is characterized by controlling the roughness so as to increase the surface area.
According to this method, the surface area of the base metal film when forming the photosensitive organic film is increased by a large number of irregularities, so that the contact area with the metal film is increased when the photosensitive organic film is formed on the metal film. In addition, the adhesion between both films is improved. As a result, the conventional photosensitive organic film does not peel off.

According to a second aspect of the present invention, there is provided a method for evaluating a silicon multilayer wiring board, wherein a multilayer wiring is produced on a silicon substrate using a photosensitive organic film as an interlayer insulating film of the metal wiring layer. In the evaluation method of the silicon multilayer wiring board for evaluating the appropriateness of the unevenness of the surface, the characteristic curve between the reflectance obtained by irradiating the surface with light and the wavelength of the light, and the roughness of the surface From the relationship, the appropriateness of the roughness of the surface is evaluated.
According to this method, the surface of the metal wiring layer is irradiated with light without using a metal surface roughness meter as in the prior art, and the reflectance is measured to evaluate whether the surface roughness is good or bad. Since the measurement time is significantly shorter than in the prior art and no defects in the metal wiring layer due to surface contact occur, evaluation can be performed in a short time without making the product defective.

  As described above, according to the present invention, when a photosensitive organic film is used as an interlayer insulating film, there is an effect that the film can be appropriately removed and the Al wiring can be appropriately multilayered. Also, the evaluation of good / bad surface roughness of the metal wiring layer can be evaluated in a short time without making the evaluation product a defective product.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, parts corresponding to each other in all the drawings in this specification are denoted by the same reference numerals, and description of the overlapping parts will be omitted as appropriate.
FIG. 1 shows in cross section the roughness of the surface of an Al wiring layer formed under various conditions by the method for manufacturing a silicon multilayer wiring board according to the embodiment of the present invention. It is sectional drawing of Al wiring layer obtained on (b) predetermined pressure conditions, (c) predetermined annealing conditions, and (d) predetermined substrate heating conditions.

The feature of the present invention is that the surface of the Al wiring layer 13 which is a base metal film when forming the photosensitive organic film 21 in the interlayer coating process shown in FIG. To do. By optimizing the surface roughness due to the irregularities, the anchor effect of increasing the contact area between the Al wiring layer 13 and the photosensitive organic film 21 is used to improve the adhesion of the photosensitive organic film 21. .
As a method for improving the Al film surface roughness for generating the anchor effect, under the conditions of Al sputtering (also abbreviated as sputtering), a change in film formation pressure and addition of substrate heating, and a heat treatment process after film formation are performed. Additions were made and their effects were verified.

In the present embodiment, the first Al wiring layer 13 is formed under the Al sputtering experimental conditions as shown in FIG. At this time, the sample name of the condition when the pressure is 0.2 Pa is “Nomal”, the condition when the pressure is 0.5 Pa is “Presure”, and the condition when the substrate heating temperature is 75 ° C. is “Sub.- The condition when the substrate heating temperature is 150 ° C. is “Sub.-heating 2”, and the condition when the annealing temperature is 350 ° C. is “Annealed”.
Further, the condition without substrate heating at a pressure of 0.2 Pa was set as a standard condition (current optimum condition) in which the Al film quality and the wiring film thickness variation were optimized.

In order to increase the roughness of the Al surface, two methods described in the following (1) and (2) can be considered.
(1) A method using change in Al crystal grains by heating.
This is a method that utilizes the phenomenon that crystal grains become coarse when an abnormal growth is performed by applying thermal energy during the growth of an Al film. If the substrate is heated during the formation of the Al layer, when the sputtered Al atoms reach the substrate, the substrate receives thermal energy from the substrate.
Compared with the case where the substrate is not heated, the diffusion length of the substrate surface is increased by the amount of thermal energy, so that the probability of adhesion of Al atoms to the crystal nuclei increases and the crystal grains become coarse. Using this mechanism, an uneven surface is formed and an anchor effect is obtained.

Further, the abnormal growth of crystals is utilized by applying thermal energy after Al film formation. When the Al film is annealed after film formation, crystals in the film recrystallize with neighboring crystals. Depending on the conditions of temperature and temperature gradient, not only the crystal grains become coarse, but also the residual stress in the film is absorbed, and the crystals grow abnormally in irregularities (hillocks).
By utilizing this mechanism, an uneven surface is formed and an anchor effect is obtained. In order to verify these effects, the substrate heating temperature was set to 75 ° C. and 150 ° C. as shown in FIG. The annealing temperature after film formation was set to 350 ° C.

(2) A method of forming an uneven surface by realizing a dense needle-like or columnar crystal structure during Al film formation.
When the film forming pressure is increased, the number of Ar (argon) ions increases, so that the voltage applied to each Ar ion becomes lower from the relationship of power = voltage × current under the condition that the film forming power is constant.
That is, since the kinetic energy per Ar ion is reduced and the number of Ar ions is increased, the sputtered Al atoms have a low energy and a large number. This phenomenon is the reverse of the above substrate heating, and the growth in the film thickness direction proceeds before the crystal nucleus grows. As a result, a dense needle-like or columnar crystal film is formed. In this case, a very fine uneven surface is formed. Further, as shown in FIG. 2, the film forming pressure was set to 0.2 Pa (no pressure change) and 0.5 Pa.

FIG. 3 shows the surface roughness of the sample of the Al wiring layer 13 created under each of the above conditions.
The surface roughness is Ra (arithmetic average roughness), Ry (maximum height), Rz (10-point average roughness), Sm (average interval of unevenness), S (average interval of local peaks) according to JIS standards. , 6 items of Tp (load length ratio) were measured with an optical three-dimensional surface shape measuring instrument at two points for each sample. The measurement distance is 70 μm, and the main wavelength of light of the applied measuring instrument is 408 nm.

The surface structure of each sample expressed based on the measurement results of FIG. 3 is each model shown in FIG. However, in FIG. 1, the dimension positions of Ry and Sm are shown as a representative of (a).
In the standard condition of FIG. 1A expressed based on the measurement result of “Nomal”, Ra, Ry, and Rz are small regardless of the measurement location, and Sm is large, so that the unevenness is small and the unevenness interval is periodically. It turns out that it has the surface state which exists widely.

In the film forming conditions with a pressure of 0.5 Pa in FIG. 1B expressed based on the measurement result of “Presure”, Ra, Ry, and Rz are relatively large regardless of the measurement location, and the unevenness interval is longer than the normal conditions. It can be seen that it has a surface state that exists narrowly.
In the annealing after film formation shown in FIG. 1C expressed based on the measurement result of “Annealed”, Ra, Ry, and Rz are different depending on the position, and Sm is large, so that the unevenness is large and the unevenness interval is large. It has a non-periodically wide surface.

In the substrate heating during film formation shown in FIG. 1D expressed based on the measurement results of “Sub.-heating 1 and 2,” Ra, Ry, and Rz are relatively large, but there is no difference depending on the location, and Sm is small. It can be seen that the unevenness is larger than the normal condition and the surface where the unevenness interval is periodically narrow is present.
Next, these samples were evaluated using the reflectance of light on the Al surface. In this case, a surface roughness meter is not used.
In the reflectance measurement of the Al surface, the wavelength of the incident light source is 230 nm to 800 nm (ultraviolet and visible light region), unlike the above-described single wavelength optical measuring instrument. This is considered to be applicable as an evaluation of the surface roughness because the light energy is different in each wavelength band, and particularly, the light in the high energy band is easily scattered and attenuated by the unevenness of the surface.

In FIG. 4, the curve of the measurement result of the reflectance 0-1 in each wavelength range 100nm -900nm of each sample is shown.
Sa1 is “Nomal”, Sa2 is “Annealed”, Sa3 is “Sub.-heating1”, Sa4 is “Sub.-heating2”, and Sa5 is a curve of reflectance measurement results.
It can be seen that the standard condition of Sa1 has a high reflectance in almost any wavelength band and the surface roughness is small.

When the pressure of Sa5 is 0.5 Pa, the low energy side has a somewhat high reflectivity. However, as the energy increases, the scattering / attenuation with low unevenness occurs, and thus the reflectivity decreases.
In the annealing after the formation of the Sa2 film, the low energy side has a large and high reflectance, but as the energy increases, the scattering / attenuation with large unevenness occurs, and thus the reflectance decreases.

In the substrate heating of Sa3 and Sa4, the linear reflectivity is attenuated at a constant rate with respect to light of low energy to high energy due to a certain level of unevenness and a narrow interval in both conditions. There is a drop in
From these measurement results, it was found that in the reflectance measurement, a result related to the difference in unevenness of the Al surface roughness and the interval between the unevennesses was obtained.

With conventional optical surface roughness measuring instruments, it takes several tens of minutes to measure surface roughness, in other words, it takes a long time to measure, and with contact type surface roughness measuring instruments, sample defects due to contact occur. It was happening.
However, in the measurement using the reflectance of the light according to the present embodiment, the measurement time is short, and since there is no contact, a sample defect due to contact does not occur.

In addition, since the usage of the evaluation method based on such measurement is not evaluation based on actual measurement values, application to process inspection is being considered.
Also, as described above, we obtained a method to control the surface roughness necessary for using the anchor effect from the experiment, reflecting the result and actually preventing film peeling at the contact hole portion of the photosensitive organic film The effect was also verified as follows. The presence or absence of film peeling can be evaluated by measuring the resistance value that varies depending on the Al film coverage state at the end of the contact hole.

Therefore, contact resistance was evaluated using a test pattern model as shown in FIG. However, FIG. 5A is a perspective view of the model, and FIG. 5B is a B1-B2 cross-sectional view shown in FIG.
A photosensitive organic film 21 is formed on the first Al solid film (Al wiring layer) 13 whose surface roughness is controlled, and contact holes 32a and 32b are opened at two locations. A second Al wiring layer 33 and electrodes 34a and 34b were formed thereon, and the resistance value between the two electrodes 34a and 34b was measured.

However, the dimensions of the two electrodes 34a and 34b are vertical and horizontal L1, L2 = 300 μm, and the center interval L3 of each contact hole 32a, 32b = 1000 μm.
The first Al wiring layer 13 is solidly formed under each film forming condition, and then the resistance value for the electrode distance L3 is measured in advance, and the resistance value is found to be 31 to 39 mΩ. Yes. The ideal resistance value of the test pattern model was calculated from the resistance value of the solid film 13 and the dimensions of the test pattern model, and this ideal resistance value was used as a comparison target. The ideal resistance value is 381 mg.

In this test pattern model, since the first layer is a solid film, the resistance value of only the first layer from one contact hole 32a to the other contact hole 32b is as low as 31 to 39 mΩ, which is almost negligible. Yes.
In measuring the resistance value, as shown in FIG. 6A, the resistance values of the first to ninth samples P1 to P9 formed on the silicon wafer were measured, and the results are shown in FIG. Expressed in a table as shown. However, No. shown in the table. 1 is a resistance value at the time of Al film formation under the standard conditions shown in FIG. 2 shows the resistance value under the condition of annealing after film formation shown in FIG. 3 is a resistance value during film formation at a pressure of 0.5 Pa shown in FIG. 4 is a resistance value under the condition of annealing after film formation shown in FIG.

As shown in FIG. Samples P1 to P9 that were deposited under the conventional conditions shown in FIG. The resistance values of the annealed samples P1 to P9 after film formation shown in FIG. 2 are as high as 68Ω (minimum value) to 611Ω (maximum value) as a whole, and the wiring connection in the contact holes 32a and 32b is high. The state is bad.
That is, since the surface roughness shown in FIG. 1A having a small surface roughness and the surface having large irregularities and a wide space shown in FIG. It is considered that the adhesion between Al and the Al wiring layer 13 is poor.

No. Samples P1 to P9, which were formed at a pressure of 0.5 Pa shown in FIG. 3, have a resistance value of 730 mΩ to 126Ω, which is lower than the previous two samples. As shown in FIG. 1 (b), it is considered that when the unevenness is relatively small and the interval is narrow, the contact area is substantially increased and the adhesion is improved.
No. Samples P1 to P9 subjected to substrate heating during film formation shown in FIG. Compared to 3, the surface roughness resistance value was low at 410 mΩ to 560 mΩ and the best results were obtained with less variation when the difference in unevenness was increased as shown in FIG. .

From these results, it was confirmed that the unevenness difference and the interval of the Al wiring layer 13 are important parameters for improving the anchor effect.
As described above, according to the method for manufacturing a silicon multilayer wiring substrate of the present embodiment, it is possible to control the Al surface roughness by optimizing the Al film formation conditions, and thereby the film of the photosensitive organic film 21 is obtained. Since peeling can be prevented, multilayering of Al wiring can be realized.

In particular, when the substrate is heated during the Al film formation, the unevenness of the Al surface is larger than the standard condition and the unevenness interval is periodically narrow, so that the photosensitive organic film 21 is prevented from peeling off. can do.
Further, in the evaluation method of the silicon multilayer wiring board, the Al surface roughness meter is not used as in the prior art, and the reflectivity of the Al surface is measured to evaluate good / bad. In the measurement of the Al surface using the reflectance of light at the time of this evaluation, the measurement time is short and no sample defects due to surface contact occur. Therefore, the measurement target product should be evaluated in a short time without making it a defective product. Can do.
Conventionally, it is possible to avoid the problem of measurement time that has been several tens of minutes with an optical surface roughness measuring instrument and the problem of sample defects caused by contact with a contact type surface roughness measuring instrument.

The surface roughness of the Al wiring layer formed under various conditions by the method for manufacturing a silicon multilayer wiring board according to the embodiment of the present invention is shown in cross section, (a) is a standard condition, (b) predetermined It is sectional drawing of the Al wiring layer obtained on pressure conditions, (c) predetermined annealing conditions, and (d) predetermined substrate heating conditions. It is a figure which shows the experimental conditions of Al sputtering at the time of film-forming of Al wiring layer of a silicon multilayer wiring board. It is a figure which shows the surface roughness of Al wiring layer of each sample created on the said experimental conditions. It is a figure which shows the curve of the measurement result of the reflectance of the light in the wavelength range of each sample. The test pattern model of a silicon | silicone multilayer wiring board is shown, (a) is a perspective view of a model, (b) is B1-B2 sectional drawing shown to (a). (A) It is a figure which shows each sample collection position of the silicon multilayer wiring board formed on the silicon wafer, (b) It is a figure which shows the totalization table of the measured resistance value of each sample. It is a manufacturing process figure of the conventional silicon multilayer wiring board. It is a manufacturing-process figure of the silicon multilayer wiring board to which the conventional photosensitive organic film is applied. It is sectional drawing of the contact hole vicinity of the silicon multilayer wiring board which applied the conventional photosensitive organic film, (a-1) and (a-2) are a metal surface (Al wiring layer) and an organic film (photosensitive organic film) (B-1) and (b-2) are diagrams showing a state in which film peeling occurs between the metal surface and the organic film interface. (A) It is a figure which shows the state in which the 2nd Al wiring layer was formed appropriately on the photosensitive organic film, and (b) the state formed improperly.

Explanation of symbols

11 Si substrate 12 T-SiO ₂ layer 13 First Al wiring layer 14 CVD-SiO ₂ layer 15 Resist layer 21 Photosensitive organic film 32, 32a, 32b Contact hole 33 Second Al wiring layer 34a, 34b Electrode

Claims (2)

In a method for manufacturing a silicon multilayer wiring board, in which a multilayer wiring is manufactured on a silicon substrate using a photosensitive organic film as an interlayer insulating film of a metal wiring layer,
Any of the deposition pressure, substrate heating, and post-deposition heat treatment, which is the deposition condition of the metal film by sputtering when forming the metal wiring layer, is applied to the surface of the metal film so that the surface area increases. A method of manufacturing a silicon multilayer wiring board, wherein the control is performed so as to be rough. Evaluation of the silicon multilayer wiring board that evaluates the appropriateness of the roughness of the surface of the metal wiring layer when manufacturing multilayer wiring on the silicon substrate using a photosensitive organic film as the interlayer insulating film of the metal wiring layer In the method
Silicon multilayer wiring characterized by evaluating the appropriateness of the roughness of the surface from the relationship between the reflectance obtained by irradiating the surface with light and the characteristic curve of the wavelength of the light and the roughness of the surface Evaluation method of substrate.

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