JP2007188017A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device in which the incidence of external light on a pixel transistor is prevented and the influence on image, due to light leakage of the pixel transistor, can be suppressed. <P>SOLUTION: The display device 1 is equipped with a first substrate 2, having a plurality of photodetecting elements 11 and a plurality of the pixel transistors 12A, a second substrate 19 provided to made to face the pixel transistors 12A separated by a spacing with respect to the first substrate 2, a display layer 20 provided between the first substrate 2 and the second substrate 19, a plurality of light-shielding layers 14A, respectively provided between the first substrate 2 and the plurality of the pixel transistors 12A, and a light source 22 provided to face the second substrate 19 so as to make the display layer 20 irradiate with the light from the second substrate 19 side. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device that displays an image, and more particularly, to a display device having a photodetection element and a pixel transistor.

  A display device such as a liquid crystal display has a great advantage that it is thin and lightweight and has low power consumption, and is widely used as a display for computers and mobile phones. Furthermore, by adding input functions such as a touch panel and pen input to these display devices, the applications of the display devices have been expanded (see, for example, Patent Document 1).

  In such a display device, in addition to a display function for displaying an image, a light detection element (photosensor element) incorporated in a pixel, for example, a photoelectric conversion element reflects light from a light pen or backlight light by an object. It detects light and realizes reading functions for various purposes. However, in order to add these functions to the display device, it is necessary to add the accompanying parts, which increases the total cost of the display device.

On the other hand, in this type of display device, a drive circuit which is an external component is usually incorporated into a translucent substrate on which pixel transistors are integrated, for example, a main surface of a glass substrate, thereby reducing the total cost of the display device Technology has been developed. By using this technique and incorporating a reading function on the surface of the glass substrate, the total cost of the display device can be suppressed, and at the same time, the added value can be improved.
JP 2005-10690 A

  However, in order to increase the amount of light incident on the light detection element, it is necessary to dispose the glass substrate on which the light detection element is integrated on the display surface, that is, the side exposed to external light. In this case, like the photodetecting element, the pixel transistor is also exposed to outside light. For this reason, strong external light hits the pixel transistor, the pixel transistor leaks light, and video data written to the pixel cannot be held.

  The present invention has been made in view of the above, and an object of the present invention is to provide a display device that can prevent the external light from entering the pixel transistor and suppress the influence on the image due to the light leakage of the pixel transistor. is there.

  A feature of the embodiment of the present invention is that a display device is provided with a first substrate having a plurality of photodetecting elements and a plurality of pixel transistors, and spaced apart from the first substrate so as to face the plurality of pixel transistors. A second substrate, a display layer provided between the first substrate and the second substrate, a plurality of first light-shielding layers respectively provided between the first substrate and the plurality of pixel transistors, and a second And a light source provided to face the second substrate so as to irradiate the display layer with light from the substrate side.

  In the feature according to the embodiment of the present invention, since the first light shielding layer is provided between the first substrate and the plurality of pixel transistors, the external light is shielded by the first light shielding layers. It is possible to prevent the incidence of external light on the.

  ADVANTAGE OF THE INVENTION According to this invention, the display apparatus which can prevent the incidence | injection of the external light with respect to a pixel transistor, and can suppress the influence with respect to the image by the light leak of a pixel transistor can be provided.

  An embodiment of the present invention will be described with reference to the drawings.

  As shown in FIG. 1, a display device 1 according to an embodiment of the present invention drives a display unit 3 provided on a first substrate 2 that is a light-transmitting substrate such as a glass substrate, and the display unit 3. Drive circuits 4 and 5 are provided.

  The display unit 3 has a display function for displaying an image based on video data, and a reading function (input function) for capturing an image of an external object B approaching the display screen. The drive circuits 4 and 5 are circuits that drive the display unit 3 by supplying various signals to the display unit 3 in accordance with control signals supplied from the outside.

  As shown in FIG. 2, the display unit 3 includes a plurality of photodetecting elements 11 provided on the first substrate 2 for each pixel and a plurality of pixel transistors 12A provided on the first substrate 2 for each pixel. Etc. The drive circuits 4 and 5 include a plurality of drive transistors 12B and the like provided as various switch elements on the first substrate 2, respectively.

  As the light detection element 11, for example, a photoelectric conversion element such as a PIN type photodiode is used. For example, thin film transistors (TFTs) are used as the pixel transistors 12A and the drive transistors 12B.

  In the display unit 3, for example, a plurality of scanning lines and a plurality of signal lines are provided in a lattice shape so as to intersect each other. Further, the display unit 3 is provided with a plurality of control lines in parallel with the respective scanning lines. A pixel transistor 12A and a pixel electrode 13 are disposed at the intersection between the scanning line and the signal line. The pixel transistor 12A has a gate connected to the scanning line, a source connected to the signal line, and a drain connected to the pixel electrode 13 and the auxiliary capacitor. Further, the light detection element 11 is connected to the control line via a control switch element.

  The driving circuit 4 includes a scanning line driving circuit that outputs a scanning signal to each scanning line, a control line driving circuit that outputs a control signal to each control line, and the like. The drive circuit 5 includes a signal line drive circuit that outputs a video signal to each signal line, a detection circuit that receives a sensor output signal from each photodetecting element 11, and the like.

  Between the 1st board | substrate 2 and each pixel transistor 12A, the 1st light shielding layer 14A which shields light is provided corresponding to each pixel transistor 12A, respectively. Similarly, a second light shielding layer 14B that blocks light is also provided between the first substrate 2 and each driving transistor 12B so as to correspond to each driving transistor 12B.

  Specifically, each first light shielding layer 14A is provided on the first substrate 2 so as to oppose each pixel transistor 12A, and each first light shielding layer 14B is opposed to each driving transistor 12B. It is provided above. Each first light shielding layer 14A prevents external light from entering the corresponding pixel transistor 12A, and each second light shielding layer 14B prevents external light from entering the corresponding drive transistor 12B. .

  On the first substrate 2, an insulating layer 15 having electrical insulation is provided so as to cover each pixel transistor 12 </ b> A, each drive transistor 12 </ b> B, and each photodetecting element 11. A polarizing plate 16 is provided on the outer surface of the first substrate 2.

  A second substrate 19 having a counter electrode 17 such as a common electrode and a color filter 18 is provided separately from the first substrate 2. As the second substrate 19, for example, a counter substrate such as a glass substrate is used. A display layer 20 such as a liquid crystal layer made of a liquid crystal material is provided between the first substrate 2 and the second substrate 19. A polarizing plate 21 is provided on the outer surface of the second substrate 19.

  A light source 22 such as a backlight is disposed outside the second substrate 19 (downward in FIG. 2). The light source 22 is provided to face the second substrate 19 so as to irradiate the display layer 20 with light from the outer surface of the second substrate 19.

  Here, the light detection element 11 is incident on the display layer 20 from the backlight surface emitted from the light source 22 and reflected by the object B such as a finger and from the outer surface (that is, the display surface) of the first substrate 2. Receiving external light (that is, external light that has passed through the first substrate 2). The first light shielding layer 14A blocks external light incident on the pixel transistor 12A from the outer surface of the first substrate 2 and prevents direct external light incident on the pixel transistor 12A. Similarly, the second light shielding layer 14B blocks external light incident on the driving transistor 12B from the outer surface of the first substrate 2 and prevents direct incidence of external light on the driving transistor 12B.

  Next, the structure of the light detection element 11 will be described.

  As shown in FIG. 3, the light detection element 11 is a PIN type photodiode. The light detection element 11 is formed on a first substrate 2 made of a substantially transparent rectangular flat plate-like insulating substrate, for example, a glass substrate. On the surface which is one main surface of the first substrate 2, an undercoat layer 41 made of a silicon nitride film (SiNx), a silicon oxide film (SiOx) or the like is formed and laminated. This undercoat layer 41 prevents the diffusion of impurities to various elements formed on the first substrate 2.

  The photodetecting element 11 includes a channel part 42 and a source / drain part 43 formed of polysilicon which is a polycrystalline semiconductor. The channel part 42 is constituted by a p− region, and the source / drain part 43 is constituted by a p + region and an n + region. Source / drain portions 43 are electrically connected to both ends of the channel portion 42. The channel part 42 and the source / drain part 43 are stacked on the undercoat layer 41.

  On the undercoat layer 41 on which the channel part 42 and the source / drain part 43 are laminated, a gate insulating film 45 is formed and laminated as a first insulating layer. A gate electrode 46 is stacked on a part of the gate insulating film 45 facing the channel portion 42. The gate electrode 46 has a width dimension that is smaller than the width dimension of the p− region that is the channel portion 42, and is made of, for example, a second metal (second metal).

  On the gate insulating film 45 on which the gate electrode 46 is stacked, an interlayer insulating film 47 is formed and stacked as a second insulating layer which is a silicon oxide film having electrical insulating properties. The gate insulating film 45 and the interlayer insulating film 47 are provided with a plurality of contact holes 48 opened as conductive portions penetrating the gate insulating film 45 and the interlayer insulating film 47, respectively. These contact holes 48 are provided on the source / drain part 43 and communicate with the source / drain part 43.

  In the contact hole 48 communicating with the source / drain portion 43, a source / drain electrode 49 made of a third metal (third metal) is laminated and provided. The source / drain electrode 49 is electrically connected to the source / drain portion 43 through the contact hole 48.

  On the interlayer insulating film 47 on which the source / drain electrodes 49 are stacked, a passivation film 50 is formed and stacked so as to cover the source / drain electrodes 49 as a protective film made of a silicon nitride film.

  Next, the structure of the pixel transistor 12A and the drive transistor 12B will be described.

  As shown in FIG. 4, the pixel transistor 12A is an n-channel thin film transistor (hereinafter referred to as an n-channel TFT), and as shown in FIGS. 4 and 5, the drive transistor 12B is an n-channel TFT or a p-channel. Type thin film transistor (hereinafter referred to as p-channel TFT).

  As shown in FIG. 4, the n-channel TFT is formed on a substantially transparent rectangular flat plate-like insulating substrate, for example, a first substrate 2 of a glass substrate. On the surface which is the main surface of the first substrate 2, a first light shielding layer 14A made of, for example, a first metal (first metal) is formed to face the n-channel TFT. The first light shielding layer 14A shields the light so that external light does not enter the n-channel TFT.

  On the first light shielding layer 14A, an undercoat layer 41 made of a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is formed and laminated. This undercoat layer 41 prevents the diffusion of impurities to various elements formed on the first substrate 2.

  The n-channel TFT includes a channel portion 42, a source / drain portion 43, and an LDD (Lightly Doped Drain) portion 44 formed of polysilicon which is a polycrystalline semiconductor. The channel part 42 is constituted by a p− region, the source / drain part 43 is constituted by an n + region, and the LDD part 44 is constituted by an n− region. An LDD portion 44 is electrically connected to both ends of the channel portion 42, and a source / drain portion 43 is electrically connected to the outside of the LDD portion 44. The channel part 42, the source / drain part 43 and the LDD part 44 are stacked on the undercoat layer 41.

  On the undercoat layer 41 on which the channel portion 42, the source / drain portion 43, and the LDD portion 44 are laminated, a gate insulating film 45 is formed and laminated as a first insulating layer. A gate electrode 46 is stacked on a part of the gate insulating film 45 facing the channel portion 42. The gate electrode 46 has a width dimension substantially equal to the width dimension of the p− region which is the channel portion 42, and is made of, for example, a second metal (second metal).

  On the gate insulating film 45 on which the gate electrode 46 is stacked, an interlayer insulating film 47 is formed and stacked as a second insulating layer which is a silicon oxide film having electrical insulating properties. The gate insulating film 45 and the interlayer insulating film 47 are provided with a plurality of contact holes 48 opened as conductive portions penetrating the gate insulating film 45 and the interlayer insulating film 47, respectively. These contact holes 48 are provided on the source / drain part 43 and communicate with the source / drain part 43.

  In the contact hole 48 communicating with the source / drain portion 43, a source / drain electrode 49 made of a third metal (third metal) is laminated and provided. The source / drain electrode 49 is electrically connected to the source / drain portion 43 through the contact hole 48.

  On the interlayer insulating film 47 on which the source / drain electrodes 49 are stacked, a passivation film 50 is formed and stacked so as to cover the source / drain electrodes 49 as a protective film made of a silicon nitride film.

  Similarly, as shown in FIG. 5, the p-channel TFT is formed on a substantially transparent rectangular flat plate-like insulating substrate, for example, a first substrate 2 of a glass substrate. It is formed on a first substrate 2 of a substantially transparent rectangular flat plate-like insulating substrate, for example, a glass substrate. On the surface which is the main surface of the first substrate 2, a second light shielding layer 14B made of, for example, a first metal (first metal) is formed. The second light shielding layer 14B shields the light so that external light does not enter the p-channel TFT.

  On the second light shielding layer 14B, an undercoat layer 41 made of a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is formed and laminated. This undercoat layer 41 prevents the diffusion of impurities to various elements formed on the first substrate 2.

  The p-channel TFT includes a channel portion 42 and a source / drain portion 43 formed of polysilicon which is a polycrystalline semiconductor. The channel part 42 is constituted by a p− region, and the source / drain part 43 is constituted by a p + region. Source / drain portions 43 are electrically connected to both ends of the channel portion 42. The channel part 42 and the source / drain part 43 are stacked on the undercoat layer 41.

  On the undercoat layer 41 on which the channel part 42 and the source / drain part 43 are laminated, a gate insulating film 45 is formed and laminated as a first insulating layer. A gate electrode 46 is stacked on a part of the gate insulating film 45 facing the channel portion 42. The gate electrode 46 has a width dimension substantially equal to the width dimension of the p− region which is the channel portion 42, and is made of, for example, a second metal (second metal).

  On the gate insulating film 45 on which the gate electrode 46 is stacked, an interlayer insulating film 47 is formed and stacked as a second insulating layer which is a silicon oxide film having electrical insulating properties. The gate insulating film 45 and the interlayer insulating film 47 are provided with a plurality of contact holes 48 opened as conductive portions penetrating the gate insulating film 45 and the interlayer insulating film 47, respectively. These contact holes 48 are provided on the source / drain part 43 and communicate with the source / drain part 43.

  In the contact hole 48 communicating with the source / drain portion 43, a source / drain electrode 49 made of a third metal (third metal) is laminated and provided. The source / drain electrode 49 is electrically connected to the source / drain portion 43 through the contact hole 48.

  On the interlayer insulating film 47 on which the source / drain electrodes 49 are stacked, a passivation film 50 is formed and stacked so as to cover the source / drain electrodes 49 as a protective film made of a silicon nitride film.

  Next, a manufacturing process (manufacturing process) in the case where the n-channel TFT and the p-channel TFT are manufactured in the same process will be described. In this embodiment, the n-channel TFT and the p-channel TFT, that is, the pixel transistor 12A and the drive transistor 12B are formed by the same process. The photodetecting element 11 can also be manufactured in the same process.

  First, as shown in FIG. 6, a first metal layer (first metal layer) 51 is formed on a first substrate 2 which is an insulating substrate such as a glass substrate using Mo-Ta, Mo-W, or the like. The first metal layer 51 is patterned in a pattern corresponding to each n-channel TFT and p-channel TFT. The first metal layer 51 becomes the first light shielding layer 14A or the second light shielding layer 14B.

  Next, as shown in FIG. 6, an undercoat layer 41 is formed by CVD (Chemical Vapor Deposition) using SiNx, SiOx or the like on the first substrate 2 on which the first metal layer 51 is formed. This prevents impurities from diffusing into the element formed on the first substrate 2. Next, an amorphous silicon film 52 is deposited on the first substrate 2 by about 500 mm by PECVD (Plasma Enhanced CVD) method, sputtering method or the like. Thereafter, in order to crystallize the amorphous silicon, the amorphous silicon film 52 is irradiated with a laser. Thereby, the amorphous silicon film 52 becomes a polysilicon film.

  Further, as shown in FIG. 7, a low concentration of boron is ion-doped on the entire surface of the polysilicon film to form a p− layer 52a. The p− layer 52a becomes the channel portion 42 of the n-channel TFT and the channel portion 42 of the p-channel TFT.

  Next, as shown in FIG. 8, a gate insulating film 45 is formed as a first insulating layer by a PECVD method, an ECR-CVD (Electron cyclotron resonance CVD) method or the like so as to cover the p-layer 52a using SiOx or the like.

  Further, as shown in FIG. 9, using a resist 53 as a mask, high concentration phosphorus is ion-doped in a region for forming a source / drain region of an n-channel TFT to form an n + layer 52b. This n + layer 52b becomes each source / drain part 43 of the n-channel TFT.

  Thereafter, as shown in FIG. 10, the resist 53 is removed, and a second metal layer (second metal layer) 54 is formed on the gate insulating film 45 using Mo—Ta, Mo—W, or the like. This second metal layer 54 becomes the gate electrode 46 of the n-channel TFT and the gate electrode 46 of the p-channel TFT.

  Next, as shown in FIG. 11, the second metal layer 54 is patterned so that the source / drain region of the p-channel TFT is opened, and high-concentration boron is ion-doped into the source / drain region of the p-channel TFT, and p + Layer 52c is formed.

  At this time, the second metal layer 54 serves as a mask, and the p + layer 52c is formed in the source / drain region of the p-channel TFT. This p + layer 52c becomes the source / drain portion 43 of the p-channel TFT. Further, the second metal layer 54 of the p-channel TFT becomes the gate electrode 46 of the p-channel TFT.

  Further, as shown in FIG. 12, after patterning the second metal layer 54 so that the n− region of the n-channel TFT is opened, low concentration phosphorus is ion-doped in the LDD region of the n-channel TFT, and the n− layer is formed. 52d is formed.

  At this time, the second metal layer 54 serves as a mask, and an n− layer 52d is formed in the LDD region of the n-channel TFT. This n− layer 52d becomes the LDD portion 44 of the n-channel TFT. Further, the second metal layer 54 of the n-channel TFT becomes the gate electrode 46 of the n-channel TFT.

  Next, in order to activate the implanted impurities, the first substrate 2 in the above-described stacked state is annealed at about 500 ° C. (thermal activation step), and then hydrogenated by exposure to hydrogen plasma (hydrogenation step). ). Next, as shown in FIG. 13, the resist 55 is removed, and an interlayer insulating film 47 is formed as a second insulating layer on the gate insulating film 45 using SiOx or the like again in the same CVD apparatus.

  Further, as shown in FIG. 14, each contact hole 48 is provided in the gate insulating film 45 and the interlayer insulating film 47 to expose each n + layer 52b of the n-channel TFT, and each p + layer 52c of the p-channel TFT is similarly formed. Expose. Next, a third metal layer (third metal layer) 55 is formed in these exposed regions and patterned as source / drain electrodes 49.

  As a result, the third metal layer 55 becomes the source / drain electrode 49 of the n-channel TFT and the source / drain electrode 49 of the p-channel TFT. In the n-channel TFT, the p− layer 52 a becomes the channel portion 42, each n + layer 52 b becomes the source / drain portion 43, and each n− layer 52 d becomes the LDD portion 44. In the n-channel TFT, the p− layer 52 a becomes the channel portion 42, and each p + layer 52 c becomes the source / drain portion 43.

  Finally, a passivation film 50 (see FIGS. 4 and 5) is formed as a protective film on the interlayer insulating film 47 using SiN or the like, thereby completing an n-channel TFT and a p-channel TFT.

As a result, an n-channel TFT as shown in FIG. 4 and a p-channel TFT as shown in FIG. 5 are obtained.

  As described above, according to the display device 1 according to the present embodiment, the first light shielding layer 14A is provided corresponding to each pixel transistor 12A, that is, between the first substrate 2 and each pixel transistor 12A. Accordingly, since the external light is shielded by the first light shielding layer 14A, it is possible to prevent the external light from entering each pixel transistor 12A, and to suppress the influence on the image due to the light leak of each pixel transistor 12A. be able to. As a result, the video data written to the pixels can be held, and the display device 1 having both a high-performance reading function and a high-quality display function can be realized.

  Further, by providing the second light shielding layer 14B corresponding to each driving transistor 12B, that is, by providing the second light shielding layer 14B between the first substrate 2 and each driving transistor 12B, the external light is shielded by the second light shielding layer 14B. Therefore, it is possible to prevent the external light from entering each driving transistor 12B, and the influence of the light leakage of each driving transistor 12B on the image can be suppressed.

  Each pixel transistor 12A is provided on the display layer 20 side on the first substrate 2, and the first light shielding layer 14A is provided between the first substrate 2 and the pixel transistor 12A. External light incident on the transistor 12A from the outer surface of the first substrate 2 can be reliably blocked. Furthermore, the first light-shielding layer 14A is stacked on the first substrate 2, and the pixel transistor 12A is formed on the first light-shielding layer 14A, whereby the first light-shielding layer 14A is easily formed corresponding to the pixel transistor 12A. can do.

  Further, each driving transistor 12B is provided on the display layer 20 side on the first substrate 2, and the second light shielding layer 14B is provided between the first substrate 2 and the driving transistor 12B. External light incident on the transistor 12B from the outer surface of the first substrate 2 can be reliably blocked. Further, the second light-shielding layer 14B is laminated on the first substrate 2, and the drive transistor 12B is formed on the second light-shielding layer 14B, so that the second light-shielding layer 14B is easily formed corresponding to the drive transistor 12B. can do.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the first light shielding layer 14A is provided between the first substrate 2 and the pixel transistor 12A. However, the present invention is not limited to this. The first light shielding layer 14A may be provided on the outer surface of the substrate 2 so as to face the pixel transistor 12A. Similarly, in the above-described embodiment, the second light shielding layer 14B is provided between the first substrate 2 and the driving transistor 12B. However, the present invention is not limited to this. The second light shielding layer 14B may be provided on the outer surface of the substrate 2 so as to face the driving transistor 12B.

  In the above-described embodiment, the n-channel TFT is used as the pixel transistor 12A. However, the present invention is not limited to this. For example, a p-channel TFT may be used.

  In the above-described embodiment, the display layer 20 is formed as a liquid crystal layer from a liquid crystal material. However, the present invention is not limited to this. For example, the display layer 20 is formed from a light emitter and the display device 1 is formed as an organic EL display. You may do it.

It is a top view which shows schematic structure of the display apparatus which concerns on one Embodiment of this invention. It is AA sectional view taken on the line which shows schematic structure of the display apparatus shown in FIG. It is sectional drawing which shows the photon detection element with which the display apparatus shown in FIG.1 and FIG.2 is provided. FIG. 3 is a cross-sectional view showing an n-channel TFT included in the display device shown in FIGS. 1 and 2. FIG. 3 is a cross-sectional view illustrating a p-channel TFT included in the display device illustrated in FIGS. 1 and 2. FIG. 10 is a first process cross-sectional view for explaining a manufacturing process when an n-channel TFT and a p-channel TFT are manufactured in the same process. It is 2nd process sectional drawing. It is 3rd process sectional drawing. It is a 4th process sectional view. FIG. 10 is a fifth process cross-sectional view. It is 6th process sectional drawing. It is 7th process sectional drawing. It is 8th process sectional drawing. It is 9th process sectional drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 1st board | substrate 11 Photodetection element 12A Pixel transistor 12B Drive transistor 14A 1st light shielding layer 14B 2nd light shielding layer 19 2nd board | substrate 20 Display layer 22 Light source

Claims (2)

A first substrate having a plurality of photodetecting elements and a plurality of pixel transistors;
A second substrate provided opposite to the plurality of pixel transistors and spaced from the first substrate;
A display layer provided between the first substrate and the second substrate;
A plurality of first light shielding layers respectively provided between the first substrate and the plurality of pixel transistors;
A light source provided facing the second substrate so as to irradiate the display layer with light from the second substrate side;
A display device comprising: The first substrate includes a plurality of driving transistors respectively connected to the plurality of photodetecting elements or the plurality of pixel transistors and provided on the display layer side on the first substrate,
The display device according to claim 1, further comprising a plurality of second light shielding layers provided between the first substrate and the plurality of driving transistors.

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