JP2007183957A - Multiprocessor system and its data transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system and its data transmission method. <P>SOLUTION: The multiprocessor system includes a plurality of masters, at least one first type slave that operates with a first clock frequency, and at least one second type slave that operates with a second clock frequency higher than the first clock frequency. The arbiter is adjusted the access between the master and the slave through single readout/writing bus path between the arbiter and the first type slave, and through a plurality of readout bus paths and/or a plurality of writing bus paths between the arbiter and the second type slave. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system that increases an effective bus bandwidth in order to operate a slave at a high clock frequency in a multiprocessor system.

  FIG. 1 shows a block diagram of a multiprocessor system 100 having a master block 102 and a slave block 104. The master block 102 has a plurality of masters including a first master 112, a second master 114, an mth master 116, and the like. Each master 112, 114... 116 is a data processor, for example, a central processing unit (CPU) or a digital signal processor (DSP).

  The slave block 104 has a plurality of slaves including a first slave 122, a second slave 124, and an nth slave 126. Each slave 122, 124 ... 126 is accessed by at least one master 112, 114 ... 116. For example, each slave 122, 124 ... 126 is a memory device.

  The bus arbiter 130 arbitrates between the masters 112, 114,... 116 through the first bus 132 and the second bus 134 to access the slaves 122, 124,. In general, one of the masters 112, 114... 116 accesses one of the slaves 122, 124.

  For example, the first and second masters 112 and 114 transmit respective request signals to the bus arbiter 130 in order to write data to the second slave 124. The bus arbiter responds to the first master 112 with a first authorization success. In this case, the first master 112 transmits control, address, and data signals to the bus arbiter through the first bus 132. Thereafter, the bus arbiter 130 transmits control, address, and data signals to the slave block 104 through the second bus 134. The second slave 124 corresponding to the decoded address signal responds to the memory core with the write data.

  The bus arbiter 130 then responds to allow access to the second master 114 that transmits control, address, and data signals to the bus arbiter through the first bus 132. The second slave 124 corresponding to the decoded address signal responds to the memory core with the write data.

  FIG. 2 shows an address and control (address and control, AC) multiplexer (multiplexer, 142), a write (write, WR) multiplexer (multiplexer, 144), a read (read, RD) multiplexer (multiplexer, 146), and a multiplexer controller ( 1 shows an embodiment for a bus arbiter 130 having multipleplexer controller 148). A first bus 132 between the master block 102 and the bus arbiter 130 includes an AC (address and control) master bus 152 for communication of an address (control and AC) signal, a WR (write) master bus 154 for communication of write data, and An RD (read) master bus 156 is used for communication of read data. Further, the second bus 134 between the bus arbiter 130 and the slave block 104 includes an AC (address and control) slave bus 162 for communication of AC signals, a WR (write) slave bus 164 for communication of write data, and It is composed of an RD (read) slave bus 166 for communication of read data.

  Masters 112, 114... 116 transmit address and control signals ACM 1, ACM 2... ACMm to AC multiplexer 142 through AC master bus 152, respectively. Masters 112, 114... 116 transmit write data WRM 1, WRM 2... WRMm to write WR multiplexer 144 via write master bus 154. The masters 112, 114... 116 receive the read data RDM1, RDM2... RDMm from the RD multiplexer 146 through the RD master bus 156, respectively.

  The slaves 122, 124,... 126 receive the address and control signals ACS1, ACS2,..., ACSn from the AC multiplexer 142 through the AC slave bus 162, respectively. The slaves 122, 124... 126 receive the write data WRS1, WRS2... WRSn from the WR multiplexer 144 via the WR slave bus 164, respectively. The slaves 122, 124... 126 transmit read data RDS1, RDS2,... RDSn to the RD multiplexer 146 through the RD slave bus 166, respectively.

  The multiplexer controller 148 controls the AC multiplexer 142 to control the address and control from one of the masters 112, 114... 116 having access as address and control signals ACM1, ACM2. A first control signal AC_SEL for selecting one of the signals ACM1, ACM2,... ACMm is generated. The selected address signal indicates one of the accessed slaves 122, 124... 126, and the selected slave responds to a data read or data write operation.

  Multiplexer controller 148 also controls WR multiplexer 144 to write signal WRM1 from one of masters 112, 114 ... 116 having access as write data WRS1, WRS2 ... WRSn coupled to slaves 122, 124 ... 126, respectively. , WRM2... WRMm is selected to generate a second control signal WR_SEL. Multiplexer controller 148 controls RD multiplexer 146 to read data RDS1, RDS2 from one of slaves 122, 124 ... 126 accessed as read signals RDM1, RDM2 ... RDMm connected to masters 112, 114 ... 116, respectively. ... a third control signal RD_SEL for selecting one of RDSn is further generated.

  The read operation in the multiprocessor system 100 will be described with reference to the timing chart of FIG. 2 and 3, at time T0, the second slave 124 receives the address and control signal ACM1 generated by the first master 112 for a first request signal for reading data from the second slave 124. . The multiplexer controller 148 controls the AC multiplexer 142 to select the address and control signal ACM1 from the first master 112 output by the respective address and control signals ACS1, ACS2... ACSn connected to the slaves 122, 124. An AC_SEL signal is generated.

  The second slave 124 corresponding to the address signal designated by the ACM1 signal responds by preparing the first read data corresponding to the ACM1 signal during the time T2-T4. After the interface time T2-T3, the second slave 124 begins to output the first read data as RDS2 on the RD slave bus 166.

  Currently used memory devices have higher performance than before, so the second slave 124 operates at a higher clock frequency than the buses 164,166. At the interface time T2-T3, the read data is switched from the high clock frequency of the second slave 124 to the low clock frequency of the RD slave bus 166.

  The second slave 124 has first read data prepared during a relatively short time period T2-T4. This is because the second slave 124 operates at a higher clock frequency. However, since the read slave bus 166 operates at a lower clock frequency, the first read data is output to the RD slave bus 166 during a relatively long time period T3-T6.

  Further, at time T1 in FIG. 3, the address generated by the second master 114 and the control signal ACM2 for the second request signal are input to the second slave 124, and data is read from the second slave 124. Multiplexer controller 148 generates an AC_SEL signal. The AC_SEL signal controls the AC multiplexer 142 to select the address output from the second master 114 and the control signal ACM2. The address and control signal SCM2 is provided to the slaves 122, 124... 126 as address and control signals ACS1 to ACSn.

  The second slave 124 corresponding to the address signal specified by the ACM2 signal prepares the first read data in advance, and then responds by preparing the second read data corresponding to the ACM2 signal during the period T4-T5. . Such second read data is prepared to be output to the read slave bus 166 at time T5. However, the RD slave bus 166 is used to output the first read data for the first master 112 until time T6. At time T6, the second read data is output to the RD slave bus 166 as RDS2 during the time T6-T7.

  For the second read data, since the second slave 124 operates at a high clock frequency, the second slave 124 has the second read data prepared for a relatively short time period T4 to T5. However, since the RD slave bus 166 operates at a low clock frequency, the second read data is output to the RD slave bus 166 during a relatively high time period T6-T7.

  Such a long time of T3-T6 and T6-T7 for outputting the first and second read data to the RD slave bus 166 disadvantageously slows the operation of the multiprocessor system 100.

  FIG. 4 is a timing diagram illustrating an example of a write operation in the multiprocessor system 100. 2 and 4, at time T0, the second slave 124 is generated by the first master 112 so that the first request signal is written to the second slave 124, so that the address and control signal ACM1. Receive. The multiplexer controller 148 controls the AC multiplexer 142 to select the address and control signal from the first master 112 output as the respective address and control signals ACS1, ACS2... ACSn connected to the slaves 122, 124. Generate a signal.

  The second slave 124 corresponding to the address signal specified by the ACM1 signal responds by inputting the first data to be written from the WR slave bus 164 for the time T2-T4. Further, after the interface time of T2-T3, the second slave 124 starts to write the first write data of WRS2 into the memory core.

  Since the second slave 124 operates at a high clock frequency, the second slave 124 writes the first write data into the memory core for a relatively short time T3-T5. However, since the WR slave bus 164 operates at a low clock frequency, the first write data is input from the WR bus 164 for a relatively long period of time T2-T4.

  Further, at time T1 in FIG. 4, the second slave 124 receives the address and control signal ACM2 generated by the second master 114 for a second request signal for writing data to the second slave 124. The multiplexer controller 148 controls the AC multiplexer 142 to select the address and control signal ACM2 from the second master 114 output to the respective address and control signals ACS1, ACS2... ACSn connected to the slaves 122, 124. An AC_SEL signal is generated.

  The second slave 124 corresponding to the address signal specified by the ACM2 signal responds by inputting the second write data from the WR slave bus 164 for the time T4-T7. Further, the second slave 124 starts to write the second write data of WRS2 into the memory core after the interface time of T4-T6.

  Since the second slave 124 operates at a high clock frequency, the second slave 124 writes the second write data into the memory core during a relatively short time period T6-T8. However, since the WR slave bus 164 operates at a low clock frequency, the second write data is input from the WR slave bus 164 during a relatively long time period T4-T7.

  Such a long time of T2-T4 and T4-T7 for inputting the first and second write data from the WR bus 164 disadvantageously slows the operation of the multiprocessor system 100.

  One way to overcome this shortcoming is to increase the operating speed of the buses 164,166. Another solution is to shorten the interface time of T2-T3 of FIG. 3 and T2-T4 and T4-T6 of FIG. However, the solution is very expensive.

  As such, a low cost mechanism is desirable to prevent that low operation of the multiprocessor system 100 when the bus 162, 164 operates at a lower clock frequency in one of the slaves 122, 124 ... 126.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multiprocessor system and a data transmission method thereof that can increase the operation speed without increasing the clock frequency of the bus. is there.

  Thus, in a general aspect of the invention, a plurality of read and / or write bus paths are formed for slaves operating at a high clock frequency.

  A multiprocessor system according to an embodiment of the present invention includes a plurality of masters, at least one first type slave operating at a first clock frequency, and at least one second type operating at a second clock frequency higher than the first clock frequency. Including slaves. The multiprocessor system also includes an arbiter for coordinating access between the master and the slave, and includes a single read / write bus path between the arbiter and the first type of slave. The multiprocessor system further includes a plurality of read bus paths and / or a plurality of read bus paths between the arbiter and the second type slave.

  In particular, when the bus path operates at a low clock frequency, the second type slave outputs read data on the multiple read bus path with time overlap and / or inputs write data from the multiple write bus path with time overlap. The arbiter includes a multiplexer and a multiplexer controller for coordinating data transmission with such time overlap between a plurality of masters and a plurality of slaves.

  In this way, data is transmitted over multiple bus paths in a time-overlapping manner, so a slow clock frequency on the bus path does not slow down the operation of a multiprocessor system having a slave operating at a high clock frequency.

  The multiprocessor system according to the present invention can minimize the latency in data processing without using a high-speed slave and increasing the clock frequency of the bus.

  Other features and advantages of the present invention will be more specifically described in the detailed description of the invention with reference to the accompanying drawings.

  FIG. 5 shows a block diagram of a multiprocessor system 200 according to an embodiment of the invention. Multiprocessor system 200 includes a master block 202, a slave block 204, and a bus arbiter 206. The master block 202 has a plurality of masters including a first master 212, a second master 214, and an m-th master 216. Each master 212, 214... 216 is, for example, a data processor such as a central processing unit (CPU) or a digital signal processor (DSP).

  The slave block 204 has a plurality of slaves including a first slave 222, a second slave 224, and an nth slave 226. Each slave 222, 224... 226 is accessed by at least one of the masters 212, 214. For example, each slave 222, 224,... 226 is a memory device.

  The n-th slave 226 is a first type that operates at a first clock frequency, and the first and second slaves 222 and 224 are a second type that operates at a second clock frequency higher than the first clock frequency. In the embodiment of the present invention, the remaining slaves such as the nth slave 226 excluding the fast slaves 222 and 224 in the slave block 204 are the first type that operates at a lower clock frequency.

  The bus arbiter 206 mediates access between the masters 212, 214... 216 and the slaves 222, 224. The bus arbiter 206 includes an address and control multiplexer (address and control multiplexer 232), a first write (write, WR) multiplexer 234, a second WR '(write) multiplexer 236, a first read (read, RD) multiplexer 238, and a second RD. A plurality of multiplexers including a '(read) multiplexer 240 are included.

  The bus arbiter 206 also includes a single selector 242 composed of m multiplexers including a first selector multiplexer 244, a second selector multiplexer 246, and an mth selector multiplexer 248. Multiplexer controller 250 generates an adjustment signal for adjusting multiplexers 232, 234, 236, 240, 244, 246.

  The masters 212, 214... 216 transmit address and control (AC) signals ACM1, ACM2,... ACMm to the AC multiplexer 232 through the address and control AC master bus 252 respectively. The masters 212, 214... 216 write the write data WRM 1, WRM 2... WRMm and transmit them to the first WR multiplexer 234 through the master bus 254. The masters 212, 214... 216 receive read data RDM1, RDM2,... RDMm from a single selector 242 through a read master bus 256.

  The slaves 222, 224... 226 receive address and control signals ACS 1, ACS 2, ACSn from the AC multiplexer 234 through the AC slave bus 258. .. 226 receive first write data WRS1, WRS2,... WRSn from the first WR multiplexer 234 through the first write (WR) slave bus 260, respectively. Fast slaves 222, 224 operating at a higher clock frequency receive second write data WRS1 ′, WRS2 ′ from the second WR ′ multiplexer via the second write WR ′ slave bus 262, respectively.

  226 transmits the first read data RDS1, RDS2,... RDSn to the first RD multiplexer 238 through the first read (read, RD) slave bus 264. The fast slaves 222 and 224 operating at a higher clock frequency transmit the second read data RDS1 ′ and RDS2 ′ to the second RD ′ multiplexer 240 through the second read RD ′ slave bus 266, respectively.

  In this manner, fast slaves 222, 224 operating at higher clock frequencies have two write bus paths through WR and WR ′ slave buses 260, 262 and WR and WR ′ multiplexers 234, 236, respectively. Similarly, faster slaves 222, 224 have two read bus paths through RD and RD ′ slave buses 264, 266 and RD and RD ′ multiplexers 238, 240, respectively.

  On the other hand, a slow slave 226 operating at a lower clock frequency has a single single bus path through the first WR slave bus 260 and the first WR multiplexer 234. Similarly, the slow slave 226 has a single read bus path through the first RD slave bus 264 and the first RD multiplexer 238.

  The read operation in the multiprocessor system 200 will be described with reference to the timing chart of FIG. 5 and 6, at time T0, the second slave 224 receives the address and control signal ACM1 generated for the first request signal for reading data from the second slave 224 by the first master 212. . The multiplexer controller 250 controls the AC multiplexer 232 to select the address and control signal ACM1 from the first master 212 output to the respective address and control signals ACS1, ACS2... ACSn connected to the slaves 222, 224. Generate a signal.

  The second slave 224 corresponding to the address signal specified in the ACM1 signal responds by preparing the first read data RDS2 corresponding to the ACM1 signal for the time T2-T4. After the interface time of T2-T3, the second slave 224 starts to output the first read data of RDS2 on the first RD slave bus 264.

The multiplexer controller 250 controls the first RD multiplexer 238 and generates an RD_SEL signal for selecting the first read data RDS2 from the second slave 224 as its output. The multiplexer controller 250 also controls the first selector multiplexer 224 to generate an S ₁ signal that selects the output of the first RD multiplexer 238 as the read data RDM 1 connected to the first master 212. With this method, the first read data RDS2 from the second slave 224 is directed to the first master 212.

  The second slave 224 operates at a slave clock frequency that is higher than the bus clock frequency for the first RD slave bus 264. The interface time T2-T3 is the time when the high clock frequency of the second slave 224 is switched to the low clock frequency of the first RD slave bus 264.

  Since the second slave 224 operates at a high clock frequency, the second slave 224 has the first read data RDS2 prepared during a relatively short time period T2-T4. However, since the first RD slave bus 264 operates at a low clock frequency, the first read data RDS2 is output to the first RD slave bus 264 during a relatively long time period T3-T7.

  6, the second slave 224 receives the address and control signal ACM2 generated for the second request signal for reading data from the second slave 224 by the second master 214. The multiplexer controller 250 generates an AC_SEL signal. The AC_SEL signal controls the AC multiplexer 232 to select the address output from the second master 214 and the control signal ACM2. The address and control signal ACM2 is provided to the slaves 222, 224... 226 as address and control signals ACS1, ACS2.

  The second slave 224 corresponding to the address signal specified in the ACM2 signal responds by preparing the second read data RDS2 ′ corresponding to the ACM2 signal for a time period T4-T6. After the interface time of T4-T5, the second slave 224 begins to output the second read data RDS2 ′ on the second RD ′ slave bus 266.

The multiplexer controller 250 controls the second RD ′ multiplexer 240 to generate an RD′_SEL signal for selecting the second read data RDS′2 from the second slave 224 that is the output thereof. The multiplexer controller 250 also controls the second selector multiplexer 246 to generate an S ₂ signal that selects the output of the 2RD ′ multiplexer 240, which is the second data RDM 2 coupled to the second master 214. With this method, the second read data RDS2 ′ of the second slave 224 is directed to the second master 214.

  Since the second slave 224 operates at a high slave clock frequency, the second slave 224 has the second read data RDS2 ′ prepared during a relatively short period of time T4-T6. However, since the second RD ′ slave bus 266 operates at a low bus clock frequency, the second read data RDS2 ′ is output to the second RD ′ slave bus 266 during a relatively long time period T5-T8.

  Nevertheless, the second slave 224 outputs the first and second read data RDS2 and RDS2 ′ on the first and second RD and RD ′ read slave buses 264 and 266 with the time overlap of T5 to T7 in FIG. As described, it has two read bus paths. FIG. 6 is a diagram for outputting the first and second read data RDS2 and RDS2 ′ from the second slave 224 as compared with the general time of the prior art (T3-T7 in FIG. 3). Reduce the overall time of T3-T8.

  FIG. 7 is a timing diagram showing an example of a write operation in the multiprocessor system 200. Referring to FIGS. 5 and 7, at the time of TO, the second slave 224 receives the address and control signal ACM1. The address and control signal ACM1 is generated from the first master 212. The address and control signal ACM1 is a first request signal for requesting the second slave 224 to write data. Multiplexer control 250 generates an AC_SEL signal. The AC_SEL signal controls the AC multiplexer 232 to select the address output from the first master 212 and the control signal ACM1. Address and control signal ACM1 is provided to slaves 222, 224,... 226 as address and control signals ACS1, ACS2,.

  Further, the multiplexer 250 generates a WR_SEL signal. The WR_SEL signal controls the first WR multiplexer 234 to select the first write data WRM1 output from the first master 212. The first write data WRM1 is provided to the slaves 222, 224,... 226 via the first WR slave bus 260 as the first write data WRS1, WRS2,. The second slave 224 corresponding to the address signal specified by the ACM1 signal responds by inputting the first write data WRS2 from the first WR slave bus 260 during the time T2-T5. Furthermore, after the interface time of T2-T4, the second slave 224 starts to write the first write data WRS2 to its memory core.

  Since the second slave 224 operates at a high clock frequency, the second slave 224 writes the first write data WRS2 into the memory core during a relatively short time period T4-T6. However, since the first WR slave bus 260 operates at a low clock frequency, the first write data WRS2 is input from the first WR slave bus 260 for a relatively long time period T2-T5.

  Further, at time T1 in FIG. 7, the second slave 224 receives the address and the control signal ACM2. The address and input signal ACM 2 are generated from the second master 214. The address and control signal ACM2 is a second request signal for requesting the second slave 224 to write data. The multiplexer controller 250 generates an AC_SEL signal. The AC_SEL signal controls the AC multiplexer 232 to select the address output from the second master 214 and the control signal ACM2. Address and control signal ACM2 is provided to slaves 222, 224,... 226 as address control signals ACS1, ACS2,. (Indicated as “AC switching” in FIG. 7)

  Further, the multiplexer controller 250 generates a WR′_SEL signal. The WR′_SEL signal controls the second WR ′ plexer 236 to select the second write data WRM2 output from the second master. The second write data WRM2 is provided to the fast slaves 222 and 224 via the second WR ′ slave bus 262 as WRS1 ′ and WRS2 ′. The second slave 224 corresponding to the address signal specified by the ACM2 signal responds by inputting the second write data WRS2 ′ from the second WR ′ slave bus 262 for the time T3-T8. Further, the second slave 224 starts to write the second write data WRS2 ′ in the memory core after the interface time T3-T7.

  Since the second slave 224 operates at a high clock frequency, the second slave 224 writes the second write data WRS2 ′ into the memory core during a relatively short time T7-T9. However, since the second WR ′ slave bus 262 operates at a low clock frequency, the second write data WRS2 ′ is input from the second WR ′ slave bus 262 during a relatively long time period T3-T8.

  Nevertheless, the second slave 224 receives the first and second write data WRS2 and WRS2 ′ from the first and second WR and WR ′ write slave buses 260 and 262 in FIG. There are two write bus paths. Such time overlap is represented by T2- in FIG. 7 for inputting the first and second write data WRS2, WRS2 ′ to the second slave 224 compared to the general time of the prior art (T2-T7 in FIG. 4). Reduce T8 overlap time.

  FIG. 8 shows a block diagram of an embodiment of slaves 222, 224 that operate at a high clock frequency, such as second slave 224. The second slave 224 includes a memory core 270 and a slave interface 272. The slave interface includes a first write data register 274, a second write data register 276, a first read data register 278, and a second read data register 280. The write selector 282 is connected between the write data registers 274 and 276 and the memory core 270. The read selector 284 is connected between the read data registers 278 and 280 and the memory core 270.

  Referring to FIGS. 6 and 8, the read selector 284 routes the first read data RDS2 from the memory core 270 to the first read data register 278 during the time T2-T4, and during the time T4-T6. The second read data RDS2 ′ is routed from the memory core 270 to the second read data register 280. Such read data transmission from the memory core 270 is synchronized with the high clock frequency of the memory core 270, and such read data transmission is sequentially performed to the read data registers 278 and 280.

  6 and 8, the first read data register 278 outputs the first read data RDS2 on the second RD slave bus 264 during a time period T3-T7. The second read data register 280 outputs the second read data RDS2 ′ onto the second read RD ′ slave bus 266 during the time period T5-T8. The first and second read data registers 278 and 280 output the first and second read data RDS2 and RDS2 ′ on the first and second RD and RD ′ slave buses 264 and 266, respectively, with a time overlap of T5 to T7. . Such read data transmission from the read data registers 278, 280 onto the RD and RD ′ slave buses 264, 266 is synchronized at the low clock frequency of the slave buses 264, 266.

  Referring to FIGS. 7 and 8, the write selector 282 routes the first write data WRS2 from the first write data register 274 to the memory core 270 during the time T4-T6, and during the time T7-T9. The second write data WRS2 ′ is routed from the second write data register 276 to the memory core 270. Such write data transmission to the memory core 270 is synchronized with the high clock frequency of the memory core 270, and such write data transmission is performed sequentially from the write data registers 274 and 276.

  7 and 8, the first write data register 274 inputs the first write data WRS2 from the first WR slave bus 260 during a time period T2-T5. The second write data register 276 receives the second write data WRS2 ′ from the second WR ′ slave bus 262 during the time T3-T8. The first and second write data registers 274 and 276 receive the first and second write data WRS2 and WRS2 ′ from the first and second WR and WR ′ slave buses 260 and 262, respectively, with a time overlap of T3 to T5. Such write data transmission in the write data registers 272, 276 from the WR and WR ′ slave buses 260, 262 is synchronized at the low clock frequency of the slave buses 260, 262.

  In this way, using X write bus paths and X read bus paths for slaves with a fast bus clock frequency, even when the slave clock frequency is lower than the slave clock frequency, latency can be transmitted on the bus or from the bus for data transmission. (Latency) is minimized. In an embodiment of the present invention, the clock frequency of the slave bus (260, 262, 264, or many up to 266, X) is greater than the clock frequency of the fast slave (222 or 224). Such multiple write bus paths and multiple read paths allow time overlap when reading data from a slow bus or writing data to a slow bus. Accordingly, the multiprocessor system 200 according to the present invention can minimize latency when processing data.

  Although the above-described embodiment is shown as an example, the present invention is not limited to this. For example, the embodiment as described above is a method. The present invention is defined and limited not only by the claims but also by the equivalent scope.

1 shows a block diagram of a typical multiprocessor system according to the prior art. 1 shows a block diagram of a multiprocessor system having a single read bus path and a single write bus path between each slave and bus arbiter according to the prior art. FIG. 3 shows a timing diagram for a read operation in the multiprocessor of FIG. 2 according to the prior art. FIG. 3 shows a timing diagram for a write operation in the multiprocessor of FIG. 2 according to the prior art. FIG. 2 shows a block diagram of a multiprocessor system having multiple read and write bus paths for each slave operating at a high clock frequency according to an embodiment of the present invention. 6 shows a timing diagram for a read operation in the multiprocessor system of FIG. 5 according to an embodiment of the present invention. FIG. 6 shows a timing diagram for a write operation in the multiprocessor system of FIG. 5 according to an embodiment of the present invention. FIG. 6 shows a block diagram of a slave interface for a slave operating at a high clock frequency in the multiprocessor system of FIG. 5 according to an embodiment of the present invention.

Claims (30)

Multiple masters,
At least one first type slave operating at a first clock frequency;
At least one second type slave operating at a second clock frequency higher than the first clock frequency;
An arbiter for coordinating access between the master and slave;
A single read / write bus path between the arbiter and the first type of slave;
A multiprocessor system comprising a plurality of read bus paths or a plurality of write bus paths between the arbiter and the second type slave.   2. The multiprocessor system according to claim 1, further comprising a plurality of read bus paths and a plurality of write bus paths between the arbiter and the second type slave. A single read bus path between the arbiter and the first type of slave;
A pair of read bus paths between the arbiter and the second type slave;
The arbiter is for selecting one of the single read bus path and the pair of read bus paths, and for transmitting read data from one of the slaves to one of the masters. The multiprocessor system of claim 1, further comprising: a first read multiplexer. Including a plurality of said second type slaves;
Each of the second type slaves has a pair of read bus paths,
The arbiter is for selecting one bus path for each pair of read bus paths, and for transmitting read data from one of the second type slaves to one of the masters. The multiprocessor system of claim 3, further comprising a second read multiplexer. A single write bus path between the arbiter and the first type of slave;
A pair of write paths between the arbiter and the second type slave;
The arbiter is for selecting one of the single write bus path and the pair of write bus paths, and for transmitting write data from one of the slaves to one of the masters. The multiprocessor system of claim 1, further comprising: a first write multiplexer. Including a plurality of said second type slaves;
Each of the second type slaves has a pair of write bus paths,
The arbiter selects one bus path for each pair of write bus paths, and transmits write data from one of the masters to one of the second type of slaves. 6. The multiprocessor system according to claim 5, further comprising a second write multiplexer. A pair of read bus paths between the arbiter and the second type slave;
The second type slave includes a pair of read data registers for storing read data transmitted in order from the slave core in synchronization with a slave clock,
The multiprocessor system according to claim 1, wherein the read data stored in the read data register is transmitted in a time-overlapping manner via the read bus path in synchronization with a bus clock.   The multiprocessor system according to claim 7, wherein the slave clock is faster than the bus clock. A pair of write bus paths between the arbiter and the second type slave;
The second type slave includes a pair of write data registers for storing write data input from the write bus path in a time-overlapping manner in synchronization with a bus clock;
2. The multiprocessor system according to claim 1, wherein the write data output from the write register is stored in the slave core in order in synchronization with a slave clock.   The multiprocessor system according to claim 9, wherein the slave clock is faster than the bus clock. A pair of read bus paths between the arbiter and the second type slave;
2. The multiprocessor system according to claim 1, wherein the pair of read bus paths are time-overlapped from the second type slave to the arbiter to transmit respective read data. A pair of write bus paths between the arbiter and the second type slave;
2. The multiprocessor system according to claim 1, wherein the pair of write bus paths are time-overlapped from the arbiter to the second type slave to transmit respective write data. Multiple masters,
With multiple slaves,
An arbiter for coordinating access between the master and the slave;
And a plurality of write bus paths between each of the at least one slave and the arbiter. Including a single write bus path in one of the arbiter and the slave;
Including a pair of write bus paths in one of the arbiter and the slave;
The arbiter is for selecting one of the single write bus path and the pair of write bus paths, and for transmitting write data from one of the masters to one of the slaves. 14. The multiprocessor system of claim 13, further comprising a first write multiplexer. Each includes a pair of write bus paths for at least two slaves;
The arbiter is configured to select one write bus path for each of the pair of write bus paths, and to transmit write data from one of the masters to one of the slaves. The multiprocessor system of claim 14 including a two-write multiplexer. Including a pair of write bus paths between the arbiter and the slave;
One of the slaves includes a pair of write data registers for storing write data input from the write bus path, time-overlapped in synchronization with a bus clock,
14. The multiprocessor system according to claim 13, wherein the write data output from the write register is sequentially stored in the slave core in synchronization with the slave clock.   The multiprocessor system according to claim 16, wherein the slave clock is faster than the bus clock. Including a pair of write bus paths between the arbiter and the slave;
The multiprocessor system according to claim 13, wherein the pair of write bus paths are time-overlapped from the arbiter to one of the slaves to transmit respective write data. In a data transmission method of a multiprocessor system,
Operating at least one first type slave at a first clock frequency;
Operating at least one second type slave at a second clock frequency higher than the first clock frequency;
Coordinating access between multiple masters and slaves;
Transmitting data from or to the first type of slave through a single read / write bus path;
Transmitting data from the second type slave to or to the second type slave through a plurality of read bus paths or a plurality of write bus paths.   The data transmission method of claim 19, further comprising transmitting data from or to the second type slave through a plurality of read bus paths and a plurality of write bus paths. Transmitting read data from the first type of slave through a single read bus path;
Transmitting read data from the second type slave through a pair of read bus paths;
Selecting one of the single read bus path and the pair of read bus paths, and transmitting read data from one of the slaves to one of the masters. The data transmission method according to claim 19. Transmitting respective read data for each of a plurality of second type slaves through each of a pair of read bus paths;
Selecting one read bus path for each of the pair of read bus paths and transmitting read data from one of the second type slaves to one of the masters. 20. The data transmission method according to claim 19, wherein: Transmitting write data to the first type of slave through a single write bus path;
Transmitting write data to the second type slave via a pair of write bus paths;
Selecting one of the single write bus path and a pair of write bus paths and transmitting write data from one of the masters to one of the slaves. The data transmission method according to claim 19. Transmitting each write data to each of a plurality of second type slaves through each of a pair of write bus paths;
Selecting one write bus path for each of the pair of write bus paths and transmitting write data from one of the masters to one of the second type of slaves. 20. The data transmission method according to claim 19, wherein: Transmitting read data from the second type slave through a pair of read bus paths;
In synchronization with the slave clock, sequentially transmitting the read data from the slave core to a pair of read data registers;
20. The data transmission method according to claim 19, further comprising the step of transmitting the read data stored in the read data register to the pair of read bus paths in a time-overlapping manner in synchronization with a bus clock. .   The data transmission method according to claim 25, wherein the slave clock is faster than the bus clock. Transmitting write data to the second type slave via a pair of write bus paths;
Transmitting the write data from the pair of write bus paths to the pair of write data registers in time overlap in synchronization with the bus clock;
20. The data transmission method according to claim 19, further comprising transmitting the write data in order from the write data register to a slave core in synchronization with a slave clock.   28. The data transmission method according to claim 27, wherein the slave clock is faster than the bus clock.   The data transmission method of claim 19, further comprising the step of transmitting the respective read data from the second type of slave through the pair of read bus paths in a time-overlapping manner.   20. The data transmission method of claim 19, further comprising the step of transmitting the respective write data to the second type slave through the pair of write bus paths in a time-overlapping manner.

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