JP2007180134A - Semiconductor integrated circuit and method for designing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for preventing breakdown by the antenna effects of a gate insulating film of a transistor, provided inside a circuit for selecting a row of a memory cell array. <P>SOLUTION: A word line decoding circuit 5 is provided with a wire GL0 of a first group to which internal address signals A0 to A3 are supplied, wires GL1, GL2 of a second group and a third group to which internal address signals A4 to A11 are supplied, a wire GL3 of a fourth group, a wire GL4 of a fifth group formed on an upper layer of the wires of the first to fourth groups for connecting between the wires of the first group and the fourth group, a word line drive circuit WL47 connected to each wire of each group of the wires of the first to third groups to activate word lines WL0 to WL47, and a word line drive circuit WL48 connected to each wire of each group of the wires of the second to fourth groups for activating a word line WL48. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a memory cell array including a plurality of memory cells arranged in a matrix and a design method thereof.

  In manufacturing a semiconductor integrated circuit, a process of depositing a wiring layer or an insulating layer and forming a predetermined pattern by etching is frequently used, and plasma etching is often used as one of typical etching processes. Here, when the wiring layer is etched by plasma etching to form a wiring having a predetermined pattern, an electric charge is given to the wiring pattern at the top when the etching is performed. When the wiring pattern is connected to the gate of the transistor and there is no leakage path, the gate insulating film of the transistor may be broken by an abnormal voltage generated by the applied charge. Such a phenomenon is called an antenna effect.

  In recent years, with the miniaturization of the LSI manufacturing process, the gate insulating film of the transistor becomes thinner, the breakdown breakdown voltage is lowered, and the antenna effect tends to occur. In order to prevent such an antenna effect, it has been proposed to provide a bypass wiring in an upper layer than a wiring that may cause the antenna effect (for example, see Patent Document 1 below).

  In Patent Document 1, in a semiconductor integrated circuit in which a plurality of circuit blocks each including a transistor and a wiring are incorporated in one chip, a wiring straddling two adjacent circuit blocks constitutes each circuit block. Before reaching the transistor, at least once in each circuit block, it is a wiring via the uppermost wiring layer used for wiring in these two circuit blocks or a higher wiring layer. Semiconductor integrated circuits are listed.

  By the way, in recent years, in order to cope with a small variety of products and a short delivery time, a plurality of circuit blocks such as a CPU (sometimes called a core, IP (which is derived from intellectual property)) A semiconductor integrated circuit called a system LSI housed in the same chip has been widely used. In a system LSI, in order to store data necessary for a circuit block, a memory circuit called an embedded memory is often mounted in the circuit block.

While the circuit configuration of the general-purpose memory circuit is fixed, the circuit configuration of the embedded memory is determined according to the needs of the mounted circuit block. Therefore, the embedded memory is often designed (generated) by a program (software) called a memory compiler. Further, the number of memory cell rows (generally corresponding to the number of words) and the number of memory cell columns (generally corresponding to the bit width per word) of the general-purpose memory circuit are 2 ^N (N is a natural number). In many cases, the number of rows and columns of memory cells of the embedded memory is not 2 ^N (N is a natural number).

  FIG. 7 is a diagram illustrating an example of a circuit configuration of a conventional embedded memory. As shown in FIG. 7, this embedded memory has a memory cell array 51 including (32 × 49) memory cells arranged in a matrix of 49 rows in the Y direction and 32 columns in the X direction. Each column of memory cells in the memory cell array 51 is connected to 32 pairs of bit lines BL100, BL100 bar to BL131, BL131 bar. Each row of memory cells in the memory cell array 51 is connected to 49 word lines WL100 to WL148.

  The bit lines BL100, BL100 bar to BL131, BL131 bar are connected to the sense amplifier circuit 52, and the sense amplifier circuit 52 is connected to the I / O circuit 53. Under the control of the control circuit 54, the I / O circuit 53 outputs data input from the external circuit to the sense amplifier circuit 52, and outputs data input from the sense amplifier circuit 52 to the external circuit. The sense amplifier circuit 52 writes the data input from the I / O circuit 53 to the memory cell and outputs the data read from the memory cell to the I / O circuit 53 under the control of the control circuit 54.

  The word lines WL100 to WL148 are connected to the word line decoding circuit 55, and the word line decoding circuit 55 is connected to the address input circuit 56. The address input circuit 56 is based on 6-bit address signals A0 to A5 (here, A0 is MSB and A5 is LSB) input from an external circuit under the control of the control circuit 54. The word line decode circuit 55 is caused to drive the lines WL100 to WL148.

  The word line decode circuit 55 includes first to third group wirings GL50 to GL52 arranged along the Y direction. The first group wiring GL50 includes four wirings L100 to L103, the second group wiring GL51 includes four wirings L104 to L107, and the third group wiring GL52 includes four wirings L108 to L111. , Each included. Here, it is assumed that the wirings L100 to L111 are wirings of the second metal layer. The wiring L100 and the address input circuit 56 are connected by a wiring L140. Here, it is assumed that the wiring L140 is a wiring of the first metal layer.

  The address input circuit 56 decodes the upper 2 bits (A0 and A1) of the address signals A0 to A5, and outputs a 4-bit signal as a decoding result onto the first group of wirings GL50 (wirings L100 to L103). To do. Signals output on the wirings L100 to L103 are assumed to be internal address signals IA0 to IA3.

  The address input circuit 56 decodes the middle 2 bits (A2 and A3) of the address signals A0 to A5, and outputs a 4-bit signal as a decoding result to the second group of wirings GL51 (wirings L104 to L107). Output above. Signals output on the wirings L104 to L107 are internal address signals IA4 to IA7.

  Further, the address input circuit 56 decodes the lower 2 bits (A4 and A5) of the address signals A0 to A5, and outputs a 4-bit signal as a decoding result on the third group wiring GL52 (wirings L108 to L111). Output to. Signals output on the wirings L108 to L111 are set as internal address signals IA8 to IA11.

  In this conventional example, the address input circuit 56 decodes the address signals A0 to A5 and outputs the internal address signals IA0 to IA11 as shown in the truth table of FIG.

  Referring to FIG. 7 again, the word line decoding circuit 55 has 49 word line driving circuits WD100 to WD148. Each of the word line driving circuits WD100 to WD148 includes a three-input NAND gate circuit and an inverter that inverts an output signal of the NAND gate circuit and outputs the inverted signal to the word line. That is, the word line driving circuits WD100 to WD148 perform an operation equivalent to that of a 3-input AND gate circuit. The wiring L100 and the word line driving circuit WD148 are connected by a wiring L150. Here, it is assumed that the wiring L150 is a wiring of the first metal layer.

  Word line driving circuits WD100 to WD148 include one signal among internal address signals IA0 to IA3, one signal among internal address signals IA4 to IA7, and one signal among internal address signals IA8 to IA11. AND operation is performed.

  For example, the word line drive circuit WD100 performs an AND operation on the internal address signal IA3, the internal address signal IA7, and the internal address signal IA11. That is, the word line driving circuit WD100 drives (activates) the word line WL100 when the value of the address signals A0 to A5 is “0b111111” (see FIG. 3). The word line driving circuit WD101 performs an AND operation on the internal address signal IA3, the internal address signal IA7, and the internal address signal IA10. That is, the word line drive circuit WD101 drives the word line WL101 when the value of the address signals A0 to A5 is “0b111110” (see FIG. 3).

  The word line driving circuit WD147 performs an AND operation on the internal address signal IA1, the internal address signal IA4, and the internal address signal IA8. That is, the word line drive circuit WD147 drives the word line WL147 when the value of the address signals A0 to A5 is “0b010000” (see FIG. 3). Further, the word line driving circuit WD148 performs an AND operation on the internal address signal IA0, the internal address signal IA7, and the internal address signal IA11. That is, the word line driving circuit WD148 drives the word line WL148 when the value of the address signals A0 to A5 is “0b001111” (see FIG. 3).

When the number of rows of memory cells in the memory cell array 51 is not 2 ^N (N is a natural number) (49 in this conventional example), the most significant bit IA0 of the internal address signal is supplied as shown in FIG. The wiring L100 may be connected to the input terminal of one NAND gate (in this conventional example, the NAND gate in the word line driving circuit WD148).

  8 shows impurities in the output transistor Tr3 in the address input circuit 56, the wiring L140, the wiring L100, the wiring L150, and the transistor Tr4 which is one of the input transistors of the NAND gate circuit in the word line driving circuit WD148. It is a figure which shows the outline | summary of the hierarchical structure of a diffusion region and wiring. As shown in FIG. 8, the impurity diffusion region 61 constituting the drain of the transistor Tr3 in the address input circuit 56 is connected to the wiring L140 via the tungsten plug W11. The wiring L140 is connected to the wiring L100 via the tungsten plug W12. The wiring L100 is connected to the wiring L150 via the tungsten plug W13. The wiring L150 is connected to the gate electrode 62 of the transistor Tr4 via the tungsten plug W14. A gate insulating film 63 is formed below the gate electrode 62.

  In the manufacturing process of the semiconductor integrated circuit, a large amount of charges may be accumulated in the relatively long wiring L100. In this case, the charge accumulated in the wiring L100 is discharged from the drain of the transistor Tr3, and the possibility that the gate insulating film 63 in the transistor Tr4 is deteriorated or destroyed is considered to be relatively low although not zero.

  However, as the process becomes finer, the wiring in the word line decoding circuit 55 or the wiring in the address input circuit 56 becomes dense, and the wiring L140 is formed in the first metal layer as shown by the dotted line in FIG. It is conceivable that the third metal layer must be formed. In this case, there is no path through which the charge accumulated in the wiring L100 is discharged in the manufacturing process, and there is a high possibility that the gate insulating film 63 in the transistor Tr4 is deteriorated or destroyed.

If the number of rows of memory cells in the memory cell array 51 is, for example, 64 (= 2 ⁶ ), 16 NAND gate input transistors are connected to the wiring L100. In this case, since the charge accumulated in the wiring L100 is distributed to the gates of the 16 input transistors, it is considered that the possibility that the gate insulating film is deteriorated or destroyed is reduced. However, as described above, in the embedded memory, the number of rows of memory cells is determined according to the needs of the circuit block. Therefore, as shown in this conventional example, the gate electrode 62 of one input transistor may be connected to the wiring L100, and as a result, the gate electrode 63 may be deteriorated or destroyed.

  In the conventional example shown in FIG. 7, it is conceivable to apply the technique disclosed in Patent Document 1 and form a bypass wiring in the upper layer of the wirings L100 to L103. However, the length of the memory cells in the Y direction has been shortened due to miniaturization of the process, and accordingly, the interval between the word line drive circuits WD100 to WD148 has also been narrowed. For this reason, the periphery of the wirings L100 to L103 is becoming dense, and it is not easy to arrange the detour wiring in the upper layer of the wirings L100 to L103.

  In a general-purpose memory circuit, a skilled design engineer can optimize the circuit and arrange detour wiring by taking time and effort. However, the embedded memory is often designed by a memory compiler according to the needs of the circuit block, and there is a strong demand for quick delivery, so the design engineer optimizes the circuit and places detour wiring. It is difficult.

  On the other hand, in a memory, a technique for crossing bit lines to reduce the influence of noise is known (for example, see Patent Documents 2 and 3 below).

  U.S. Pat. No. 6,057,049 describes a type of semiconductor memory having a pair of bit lines associated with a plurality of storage cells for transmitting memory signals in connection with a read or write operation, wherein the bit lines have a first predetermined distance. Extending approximately parallel to each other, the bit lines intersect each other at the intersection at the end of the predetermined distance, and the intersected bit lines are substantially separated from each other from the intersection so that the differential level of undesirable noise is reduced. A semiconductor memory characterized by extending a second predetermined distance in parallel is published.

  In Patent Document 3, a plurality of memory cells capable of reading and writing data, and a first bit line pair composed of first and second bit lines arranged in parallel on both sides in the arrangement direction of the memory cells, A second bit line pair consisting of third and fourth bit lines arranged in parallel to the first and second bit lines of the first bit line pair, and a first bit line pair; A first word line for selecting a memory cell provided correspondingly, and a second word line for selecting a memory cell provided corresponding to a second bit line pair, each memory cell comprising: Connected to the first word line and the second word line, and when the first word line is selected and activated, it is connected to the first bit line pair so that data can be read or written. When the second word line is selected and activated, the second bit A semiconductor memory device connected to a line pair so as to be able to read or write data, wherein the first and second bit lines of the first bit line pair are crossed in the middle, and the arrangement is arranged In the region where the arrangement of the first bit line pair is exchanged, the connection between each memory cell and the first and second bit lines is exchanged corresponding to the exchange. Semiconductor memory devices are listed.

  Even in such a memory in which bit lines are crossed, it is necessary to prevent the gate insulating film of the transistor in the circuit for selecting a row in the memory cell array from being deteriorated or destroyed by the antenna effect. .

JP 2003-163274 A (first page, FIG. 3) JP 63-66792 A (first page, FIG. 2) JP 2003-78036 A (first page, FIG. 1)

  Accordingly, in view of the above points, the present invention is a semiconductor integrated circuit having a memory cell array in which bit lines are crossed, and the gate insulating film of a transistor in the circuit for selecting a row in the memory cell array has an antenna effect. An object of the present invention is to provide a semiconductor integrated circuit capable of preventing deterioration or destruction due to the above.

  In order to solve the above problems, a semiconductor integrated circuit according to a first aspect of the present invention includes first to H-th columns (H is a natural number) in a first direction and first to J-th rows in a second direction. A plurality of memory cells arranged in a matrix (where J is a natural number of 2 or more), and the memory cells between the memory cells in the Lth row (L is a natural number smaller than J) and the memory cells in the (L + 1) th row A memory cell array in which one dummy region is provided, and first to H-th bit line pairs connected to memory cells in the first to H-th columns, each bit line pair being a first dummy region 1st to Hth bit line pairs crossing each other, 1st to Jth word lines connected to the 1st to Jth rows of the memory cell array, and a multi-bit address signal inputted from an external circuit To output a multi-bit internal address signal And a second circuit for activating the first to Jth word lines based on an internal address signal, the second circuit comprising: 1st to Jth third circuits arranged along the second direction, wherein the Lth third circuit of the first to Jth third circuits and the first to Jth circuits The first to Jth third circuits in which the second dummy region is provided between the third circuit and the (L + 1) th third circuit, along the second direction The first group of wirings extending to the second dummy area, the upper bits of the internal address signal being supplied from the first circuit, and extending along the second direction, except for the upper bits of the internal address signal Of the second to Mth groups (M is a natural number of 2 or more) supplied from the first circuit, and the second bit extending from the second dummy region along the second direction The (M + 1) th group wiring, and a group of detour wirings connecting between the first group wiring and the (M + 1) th group wiring, in the second dummy area and in the first group wiring And a group of detour wirings arranged above the (M + 1) th group wiring, wherein the first to Lth third circuits of the first to Jth third circuits are , Connected to one of each of the first to M-th group wirings, and based on signals on the connected M wirings, the first to L-th of the first to J-th word lines. The word line is activated, and the (L + 1) th to Jth third circuits of the first to Jth third circuits are one in each group of the second to (M + 1) th group wirings. And the (L + 1) th to Jth word lines among the first to Jth word lines are activated based on signals on the M connected wirings.

In this semiconductor integrated circuit, H dummy memory cells are arranged in the first direction in the first dummy area, and a dummy third circuit is arranged in the second dummy area. It is good to be. Further, L = 2 ^N +2 ^{N + 1} and L <J ≦ 2 ^{N + 2} (N is a natural number) may be used.

  In addition, the semiconductor integrated circuit according to the second aspect of the present invention includes the first to H-th columns (H is a natural number) in the first direction, and the first to J-th rows (J is 2 or more) in the second direction. A plurality of memory cells arranged in a (natural number) matrix, and a first dummy region is provided between the memory cells in the Kth row (K is a natural number) and the memory cells in the (K + 1) th row. , A memory cell array in which a second dummy region is provided between a memory cell in the Lth row (L is a natural number greater than K and smaller than J) and a memory cell in the (L + 1) th row; First to H-th bit line pairs connected to memory cells in a column, each bit line pair intersecting each other in the first and second dummy regions; , First to Jth word lines connected to the first to Jth rows of the memory cell array; A first circuit for decoding a multi-bit address signal input from an external circuit and outputting a multi-bit internal address signal, and activating the first to J-th word lines based on the internal address signal A second integrated circuit, and the second circuit is a first to Jth third circuit arranged along the second direction, and A third dummy is provided between the Kth third circuit of the first to Jth third circuits and the (K + 1) th third circuit of the first to Jth third circuits. And an Lth third circuit of the first to Jth third circuits and a (L + 1) th third circuit of the first to Jth third circuits. Extending from the first to Jth third circuits provided with the fourth dummy area between the first and second dummy areas along the second direction to the third dummy area. The first group of wires to which the upper bits of the source signal are supplied from the first circuit, and the bits other than the upper bits of the internal address signal are supplied from the first circuit, extending in the second direction. Wiring of the second to Mth groups (M is a natural number of 2 or more), wiring of the (M + 1) th group extending from the fourth dummy region along the second direction, and wiring of the first group A group of detour wirings connected to the (M + 1) th group wirings, extending from the third dummy region to the fourth dummy region in the second direction, And a group of detour wirings arranged above the (M + 1) th group wiring, and the first to Kth third circuits among the first to Jth third circuits are , Connected to one of each of the first to M-th group wirings, and the first to J-th word lines among the first to J-th word lines based on signals on the connected M wirings. The K word lines are activated, and the (K + 1) th to Lth third circuits of the first to Jth third circuits are connected to the second to Mth group wirings and the first group detour wirings. The first (K + 1) th to Lth word lines of the first to Jth word lines are activated on the basis of signals on the M connected wirings one by one in each group, and the first The (L + 1) th to Jth third circuits of the Jth third circuit are connected to one of each group of the second to (M + 1) th group wirings and connected to M The (L + 1) -th to J-th word lines among the first to J-th word lines are activated based on the signal on the book wiring.

In this semiconductor integrated circuit, H dummy memory cells are arranged along the first direction in the first and second dummy regions, and dummy third cells are arranged in the third and fourth dummy regions. These circuits may be arranged. Alternatively, K = ^2N , L = K + ^{2N + 1} , and L <J ≦ ^{2N + 2} (N is a natural number).

  In the semiconductor integrated circuit according to the first and second aspects of the present invention, J = L + 1 may be satisfied. In addition, first to Jth memory cell arrangement regions are provided in the memory cell array, first to Jth row memory cells are arranged in the first to Jth memory cell arrangement regions, and the second The first to Jth circuit arrangement areas may be provided in the circuit, and the first to Jth second circuit arrangement areas may be arranged in the first to Jth circuit arrangement areas.

  In addition, each of the first group of contact portions connecting the first group of bypass wirings and the first group of wirings is formed so as to be displaced in the second direction from the adjacent contact portion in the first direction. Each of the second group of contact portions connecting the first group of detour wires and the (M + 1) th group of wires is formed so as to be displaced in the second direction from the adjacent contact portion in the first direction. You may do it.

  In addition, a plurality of wirings that connect between the first circuit and the first group of wirings may be formed in an upper layer than the first group of wirings.

  A semiconductor integrated circuit design method according to a first aspect of the present invention is a method executed by a computer to design a semiconductor integrated circuit, wherein the first to H-th columns (H is the first direction) in the first direction. Natural number), a plurality of memory cells arranged in a matrix of first to Jth rows (J is a natural number of 2 or more) in the second direction, and memory cells in the Lth row (L is a natural number smaller than J) And a step (a) of disposing a memory cell array in which a first dummy region is provided between the memory cells in the (L + 1) th row and the first to Hth column memory cells. A step (b) of arranging H-th bit line pairs, each bit line pair intersecting each other in the first dummy region, and first to first memory cell arrays; First to Jth word lines connected to the Jth row A step (c) of arranging, a step (d) of arranging a first circuit for decoding a multi-bit address signal input from an external circuit and outputting a multi-bit internal address signal, and an internal address signal And (e) disposing a second circuit for activating the first to Jth word lines, wherein the step (e) is disposed along the second direction. The first to Jth third circuits, the Lth third circuit of the first to Jth third circuits, and the first of the first to Jth third circuits. A step (e1) of arranging the first to Jth third circuits provided with the second dummy regions between the (L + 1) third circuit and the second direction along the second direction; A first group of wirings extending to the dummy area of the upper address bit of the internal address signal supplied from the first circuit. Step (e2), and the second to Mth groups (M is equal to or greater than 2) extending in the second direction and in which bits other than the upper bits of the internal address signal are supplied from the first circuit A step (e3) of arranging a (natural number) wiring, a step (e4) of arranging a (M + 1) th group of wirings extending from the second dummy region along the second direction, and a first group of wirings And a (M + 1) -th group wiring, which is a group of detour wirings arranged in the second dummy region and above the first group wiring and the (M + 1) -th group wiring A step (e5) of arranging one group of detour wirings, and the first to Lth third circuits of the first to Jth third circuits are connected to each group of the first to Mth group wirings. A step (e6) of arranging a plurality of wirings so as to be connected one by one, and (L + 1) of the first to Jth third circuits And a step (e7) of arranging a plurality of wirings so that the J-th third circuit is connected to each one of the groups of the second to (M + 1) th group wirings. The first to Lth third circuits of the Jth third circuit are connected to the first to Mth circuits based on signals on one wiring in each group of the first to Mth group wirings. The first to Lth word lines of the J word lines are activated, and the (L + 1) th to Jth third circuits of the first to Jth third circuits are connected to the second to second circuits. The (L + 1) -th to J-th word lines among the first to J-th word lines are activated based on a signal on each wiring of each group of (M + 1) -group wirings. To do.

  A semiconductor integrated circuit design method according to a second aspect of the present invention is a method executed by a computer to design a semiconductor integrated circuit, wherein the first to H columns (H is the first direction) in the first direction. Natural number), including a plurality of memory cells arranged in a matrix of first to Jth rows (J is a natural number of 2 or more) in the second direction, and the memory cells of the Kth row (K is a natural number) and the ( A first dummy region is provided between the memory cells in the (K + 1) th row and between the memory cells in the Lth row (L is a natural number greater than K and smaller than J) and the memory cells in the (L + 1) th row. (A) disposing a memory cell array provided with a second dummy region in the first to H-th bit line pairs connected to the memory cells in the first to H-th columns, Bit line pairs are connected to each other in the first and second dummy regions. A step (b) of arranging intersecting first to Hth bit line pairs, a step (c) of arranging first to Jth word lines connected to the first to Jth rows of the memory cell array, A step (d) of arranging a first circuit for decoding a multi-bit address signal input from an external circuit and outputting a multi-bit internal address signal; and first to first based on the internal address signal And (e) disposing a second circuit for activating the J word line, wherein the step (e) includes the first to J-th elements disposed along the second direction. 3, the Kth third circuit of the first to Jth third circuits and the (K + 1) th third circuit of the first to Jth third circuits. A third dummy region is provided between the first and Jth third circuits, and the third dummy region is provided between the first and Jth third circuits. And the first to Jth third circuits in which the fourth dummy region is provided between the first and Jth third circuits and the (L + 1) th third circuit. A step (e1) and a step (e2) of arranging a first group of wirings extending in the second direction to the third dummy region and having the upper bits of the internal address signal supplied from the first circuit And second to M-th group wirings (M is a natural number of 2 or more) extending in the second direction and supplied with bits other than the upper bits of the internal address signal from the first circuit. A step (e3), a step (e4) of arranging a (M + 1) th group of wirings extending from the fourth dummy region along the second direction, a first group of wirings and a (M + 1) th group Is a group of detour wirings connecting between the second dummy area and the second dummy area to the fourth dummy area. A step (e5) of arranging a group of detour wirings extending along the direction of the first group wiring and disposed in an upper layer than the first group wiring and the (M + 1) th group wiring; A step (e6) of arranging a plurality of wirings such that the first to Kth third circuits of the three circuits are connected to one of each of the first to Mth group wirings; The (K + 1) th to Lth third circuits of the first to Jth third circuits are connected to one of the groups of the second to Mth group wirings and the first group of detour wirings. The step (e7) of arranging a plurality of wirings, and the (L + 1) th to Jth third circuits of the first to Jth third circuits are the second to (M + 1) th. And arranging (e8) a plurality of wirings so as to be connected to each one of the groups of wirings, wherein the first to Kth of the first to Jth third circuits are included. The third circuit of The first to K-th word lines of the first to J-th word lines are activated based on a signal on each wiring of each group of the first to M-th group wirings. (K + 1) to Lth third circuits of the third circuit are based on signals on one wiring of each group of the second to Mth groups of wirings and the first group of bypass wirings. The (K + 1) th to Lth word lines of the first to Jth word lines are activated, and the (L + 1) th to Jth third of the first to Jth third circuits are activated. The circuit selects the (L + 1) -th to J-th word lines of the first to J-th word lines based on a signal on one wiring in each group of the second to (M + 1) -th group wirings. It is characterized by being activated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, about the same component, it has shown with the same reference number.
FIG. 1 is a diagram showing an outline of a semiconductor integrated circuit according to the first embodiment of the present invention. In the present embodiment, the present invention is applied to an embedded memory.

  As shown in FIG. 1, this semiconductor integrated circuit has a memory cell array 1, and in the memory cell array 1, there are first to 48th memory cell arrangement areas RA0 to RA47 and dummy memory cell arrangement areas. RB1 and a 49th memory cell arrangement region RA48 are provided in order along the Y direction. In each memory cell arrangement region, 32 memory cells are arranged along the X direction. That is, (32 × 50) memory cells are arranged in the memory cell array 1. However, the 32 memory cells arranged in the dummy memory cell arrangement region RB1 are not used, and the number of used memory cells in the memory cell array 1 is (32 × 49). Each row of memory cells in the memory cell arrangement regions RA0 to RA48 is connected to 49 word lines WL0 to WL48.

  Each column of memory cells is connected to 32 pairs of bit lines BL0, BL0 bar to BL31, BL31 bar. Each of the 32 pairs of bit lines BL0, BL0 bar to BL31, BL31 bar crosses each other in the dummy memory cell arrangement region RB1. By crossing the bit lines in this way, the influence of noise can be reduced.

  The bit lines BL0, BL0 bar to BL31, BL31 bar are connected to the sense amplifier circuit 2, and the sense amplifier circuit 2 is connected to the I / O circuit 3. The I / O circuit 3 outputs data input from the external circuit to the sense amplifier circuit 2 and outputs data input from the sense amplifier circuit 2 to the external circuit under the control of the control circuit 4. The sense amplifier circuit 2 writes data input from the I / O circuit 3 to the memory cell and outputs data read from the memory cell to the I / O circuit 3 under the control of the control circuit 4.

  The word lines WL0 to WL48 are connected to the word line decoding circuit 5, and the word line decoding circuit 5 is connected to the address input circuit 6. The address input circuit 6 is based on 6-bit address signals A0 to A5 (here, A0 is MSB and A5 is LSB) input from an external circuit under the control of the control circuit 4. The lines WL0 to WL48 are driven by the word line decode circuit 5.

  In the word line decode circuit 5, first to 48th word line drive circuit arrangement regions RC0 to RC47, a dummy word line drive circuit arrangement region RD1, and a 49th word line drive circuit arrangement region RD48 are provided. They are provided in order along the Y direction. In the first to 49th word line driving circuit arrangement regions RC0 to RC48, word line driving circuits WD0 to WD48 are arranged. A word line drive circuit is also arranged in the dummy word line drive circuit arrangement region RD1, but this word line drive circuit is a dummy and is not used. Therefore, the number of word line driving circuits used in the word line decoding circuit 5 is 49.

  Each word line driving circuit has a three-input NAND gate circuit and an inverter that inverts an output signal of the NAND gate circuit and outputs the inverted signal to the word line. That is, each word line driving circuit has a function equivalent to that of a 3-input AND gate circuit.

  In the word line decoding circuit 5, a first group of wirings GL0 is arranged to extend to the dummy word line driving circuit arrangement region RD1 along the Y direction. Further, the second and third group wirings GL1 and GL2 are arranged along the Y direction. The first group of wirings GL0 includes four wirings L0 to L3, the second group of wirings GL1 includes four wirings L4 to L7, and the third group of wirings GL2 includes four wirings. Wirings L8 to L11. Here, it is assumed that the wirings L0 to L11 are wirings of the second metal layer. The wiring L0 and the address input circuit 6 are connected by a wiring L40. Here, it is assumed that the wiring L40 is a wiring of the third metal layer.

  In the word line decode circuit 5, a fourth group of wirings GL3 is arranged along the Y direction from the dummy word line drive circuit arrangement region RD1. The fourth group of wirings GL3 includes four wirings L20 to L23. Here, it is assumed that the wirings L20 to L23 are wirings of the second metal layer.

  A fifth group wiring GL4 is arranged in the dummy word line driving circuit arrangement region RD1 and above the first group wiring GL0 and the fourth group wiring GL3 (herein referred to as a third metal layer). ing. The fifth group wiring GL4 includes four detour wirings L30 to L33. The detour wirings L30 to L33 connect the first group of wirings GL0 (wirings L0 to L3) and the fourth group of wirings (wirings L20 to L23).

  FIG. 2 is a diagram showing an internal circuit of the address input circuit 6. As shown in FIG. 2, the address input circuit 6 includes circuits 11 to 13. The circuit 11 includes inverters INV0 to INV1 and circuits 14 to 17, the circuit 12 includes inverters INV2 to INV3, and circuits 18 to 21, and the circuit 13 includes inverters INV4 to INV5. And circuits 22-25. The circuits 14 to 25 each have a 2-input NAND gate circuit and an inverter that inverts an output signal of the NAND gate circuit and outputs the inverted signal to a word line. That is, the circuits 14 to 25 have a function equivalent to that of a 2-input AND gate circuit.

  The inverters INV0 and INV1 output signals A0 bar and A1 bar obtained by inverting the address signals A0 and A1, respectively. The circuit 14 performs an AND operation on the signal A0 bar and the signal A1 bar and outputs the result on the wiring L0. The circuit 15 performs an AND operation on the signal A0 and the signal A1 bar and outputs the result on the wiring L1. The circuit 16 performs an AND operation on the signal A0 bar and the signal A1 and outputs the result on the wiring L2. The circuit 17 performs an AND operation on the signal A0 and the signal A1 and outputs the result on the wiring L3. That is, the circuit 11 decodes the upper 2 bits (here, A0 and A1) in the address signals A0 to A5, and outputs a 4-bit signal as a decoding result to the first group of wirings GL0 (wirings L0 to L3). Output above. Signals output on the wirings L0 to L3 are assumed to be internal address signals IA0 to IA3.

  Inverters INV2 and INV3 output signals A2 bar and A3 bar obtained by inverting address signals A2 and A3, respectively. The circuit 18 performs an AND operation on the signal A2 bar and the signal A3 bar and outputs the result on the wiring L4. The circuit 19 performs an AND operation on the signal A2 and the signal A3 bar and outputs the result on the wiring L5. The circuit 20 performs an AND operation on the signal A2 bar and the signal A3 and outputs the result on the wiring L6. The circuit 21 performs an AND operation on the signal A2 and the signal A3 and outputs the result on the wiring L7. That is, the circuit 12 decodes the middle 2 bits (A2 and A3 in this case) of the address signals A0 to A5, and outputs a 4-bit signal as a decoding result to the second group of wirings GL1 (wirings L4 to L7). ) Output above. Signals output on the wirings L4 to L7 are internal address signals IA4 to IA7.

  Inverters INV4 and INV5 output signals A4 bar and A5 bar obtained by inverting address signals A4 and A5, respectively. The circuit 22 performs an AND operation on the signal A4 bar and the signal A5 bar and outputs the result on the wiring L8. The circuit 23 performs an AND operation on the signal A4 and the signal A5 bar and outputs the result on the wiring L9. The circuit 24 performs an AND operation on the signal A4 bar and the signal A5 and outputs the result on the wiring L10. The circuit 25 performs an AND operation on the signal A4 and the signal A5 and outputs the result on the wiring L11. That is, the circuit 13 decodes the lower 2 bits (here, A4 and A5) in the address signals A0 to A5, and outputs a 4-bit signal as a decoding result to the third group wiring GL2 (wirings L8 to L11). Output above. Signals output on the wirings L8 to L11 are assumed to be internal address signals IA8 to IA11.

  In FIG. 2, the wiring L40 connecting the circuit 14 and the wiring L0 is assumed to be a wiring of the third metal layer. Similarly, the wirings connecting the other circuits 15 to 25 and the wirings L1 to L11 are also wirings of the third metal layer.

  FIG. 3 is a diagram showing a truth table of address signals A0 to A5 and internal address signals IA0 to IA11.

  Referring again to FIG. 1, the three input terminals of the word line driving circuits WD0 to WD47 are connected to one of each group of the first to third groups of wirings GL0 to GL2. The three input terminals of the word line driving circuit WD48 are connected to one of each group of the second to fourth groups of wirings GL1 to GL3. That is, the word line driving circuits WD0 to WD48 have one signal in the internal address signals IA0 to IA3, one signal in the internal address signals IA4 to IA7, and one signal in the internal address signals IA8 to IA11. An AND operation with the signal is performed, and the word lines WL0 to WL48 are driven according to the result of the AND operation. The wiring L20 and the word line driving circuit WD48 are connected by a wiring L50. Here, it is assumed that the wiring L50 is a wiring of the first metal layer.

  For example, the word line drive circuit WD0 performs an AND operation on the internal address signal IA3, the internal address signal IA7, and the internal address signal IA11. That is, the word line drive circuit WD0 drives (activates) the word line WL0 when the value of the address signals A0 to A5 is “0b111111” (see FIG. 3). The word line drive circuit WD1 performs an AND operation on the internal address signal IA3, the internal address signal IA7, and the internal address signal IA10. That is, the word line driving circuit WD1 drives the word line WL1 when the value of the address signals A0 to A5 is “0b111110” (see FIG. 3).

  The word line drive circuit WD47 performs an AND operation on the internal address signal IA1, the internal address signal IA4, and the internal address signal IA8. That is, the word line drive circuit WD47 drives the word line WL47 when the value of the address signals A0 to A5 is “0b010000” (see FIG. 3). The word line driving circuit WD48 performs an AND operation on the internal address signal IA0, the internal address signal IA7, and the internal address signal IA11. That is, the word line driving circuit WD48 drives the word line WL48 when the value of the address signals A0 to A5 is “0b001111” (see FIG. 3).

  FIG. 4 shows the output transistors of the circuit 14 in the address input circuit 6, the wiring L40, the wiring L0, the detour wiring L30, the wiring L20, the wiring L50, and the inputs of the NAND gate circuit in the word line driving circuit WD48. It is a figure which shows the outline | summary of hierarchical structures, such as an impurity diffusion area | region and wiring with a transistor. As shown in FIG. 4, the impurity diffusion region 31 constituting the drain of the output transistor Tr1 in the circuit 14 includes a tungsten plug W1, a first metal layer wiring 34, a tungsten plug W2, a second metal layer wiring 35, and And connected to the wiring L40 via a tungsten plug W3. The wiring L40 is connected to the wiring L0 via the tungsten plug W4. The wiring L0 is connected to the bypass wiring L30 via the tungsten plug W5. The bypass wiring L30 is connected to the wiring L20 via the tungsten plug W6. The wiring L20 is connected to the wiring L50 via the tungsten plug W7. The wiring L50 is connected to the gate electrode 32 of the input transistor Tr2 of the NAND gate in the word line driving circuit WD48 via the tungsten plug W8. A gate insulating film 33 is formed below the gate electrode 32.

  In the manufacturing process of the semiconductor integrated circuit, a large amount of charge may be accumulated in the relatively long wiring L0. However, at this time, the wiring L30 is not yet formed, and the wiring L0 and the gate electrode 32 are not connected. Therefore, the gate insulating film 33 is not deteriorated or destroyed by the charge accumulated in the wiring L0.

FIG. 5 is a diagram illustrating a layout in the vicinity of the bypass lines L30 to L33. As shown in FIG. 5, the bypass wiring L30 is connected to the wiring L0 via a contact. Further, the bypass wiring L30 is connected to the wiring L20 via a contact.
The bypass wiring L31 is connected to the wiring L1 via a contact. Further, the bypass wiring L31 is connected to the wiring L21 through a contact.

The bypass wiring L32 is connected to the wiring L2 via a contact. The bypass wiring L32 is connected to the wiring L22 via a contact.
The bypass wiring L33 is connected to the wiring L3 through a contact. Further, the bypass wiring L33 is connected to the wiring L23 via a contact.

  The contact portions of the bypass lines L30 to L33 need to be wider than the main portion. Therefore, if the positions of the contact portions of the detour wires L30 to L33 are aligned in the Y direction, the interval between adjacent contacts in the X direction is reduced. Therefore, as shown in FIG. 5, if the contact portion connecting the detour wires L30 to L33 and the wires L0 to L3 is formed so as to be shifted in the Y direction from the contact portion adjacent in the X direction, It is possible to ensure an interval between adjacent contact portions. Similarly, if the contact portions connecting the detour wires L30 to L33 and the wires L20 to L23 are formed so as to be displaced in the Y direction from the contact portions adjacent in the X direction, the contact portions adjacent in the X direction are between It is possible to ensure an interval.

  Referring again to FIG. 1, in the present embodiment, a dummy memory cell placement region RB1 is provided in the memory cell array 1 in order to cross each of the 32 pairs of bit lines BL0, BL0 bar to BL31, BL31 bar. ing. Accordingly, a dummy word line drive circuit arrangement region RD1 is provided between the 48th word line drive circuit arrangement region RC47 and the 49th word line drive circuit arrangement region RC48. Since no other wiring is arranged in the dummy word line driving circuit arrangement region RD1, the bypass wirings L30 to L33 can be easily arranged. By disposing the bypass lines L30 to L33, it is possible to prevent the gate insulating film of the input transistor of the NAND gate circuit in the 49th word line driving circuit WD48 from being deteriorated or destroyed by the antenna effect. .

  In the present embodiment, 32 memory cells are arranged in the dummy memory cell arrangement region RB1, but no memory cells may be arranged. If no memory cell is arranged in dummy memory cell arrangement region RB1, the length of dummy memory cell arrangement region RB1 in the Y direction is made shorter than the length of other memory cell arrangement regions RA0 to RA48 in the Y direction. It is also possible. Thereby, the chip area can be reduced. On the other hand, if memory cells are arranged in the dummy memory cell arrangement region RB1 as in the present embodiment, conditional branching, exception processing, etc. are reduced, so that programming of the memory compiler (software) becomes easier. .

  In this embodiment, the word line driving circuit is arranged in the dummy word line driving circuit arrangement region RD1, but the word line driving circuit may not be arranged. If no word line drive circuit is arranged in the dummy word line drive circuit arrangement region RD1, the length of the dummy word line drive circuit arrangement region RD1 in the Y direction is set to the other word line drive circuit arrangement regions RC0 to RC48. It is also possible to make it shorter than the length in the Y direction. Thereby, the chip area can be reduced. On the other hand, if the word line drive circuit is arranged in the dummy word line drive circuit arrangement region RD1 as in the present embodiment, conditional branching, exception processing, etc. are reduced, so that programming of the memory compiler is easier. Become.

In the present embodiment, the number of usable memory cell rows in the memory cell array 1 is 49 rows (= 2 ⁴ +2 ⁵ +1), but other row numbers may be used. The dummy word line drive circuit arrangement region RD1 includes the 48th (= 2 ⁴ +2 ⁵ ) th row word line drive circuit arrangement region RC47 and the 49th (= 2 ⁴ +2 ⁵ +1) th row word line drive circuit arrangement region RD1. Although it arrange | positions between RC48, you may arrange | position in another position.

When the address signal is 6 bits wide, the maximum number of usable memory cells that the memory cell array can have is 64 (= 2 ⁶ ). The carry of the internal address signal to the MSB is between 48 lines (= 2 ⁴ +2 ⁵ ) corresponding to 3/4 of the maximum number of lines 64 and the next 49 lines (= 2 ⁴ +2 ⁵ +1). Arise. Therefore, when the number of rows of the memory cell array 1 is 49 as in the present embodiment, the dummy word line drive circuit arrangement region RD1 is set to the 48th (= 2 ⁴ +2 ⁵ ) th row of word line drive circuits WD47 and 49th. It is preferable to arrange between (= 2 ⁴ +2 ⁵ +1) rows of word line driving circuits WD48.

When the number X of usable memory cell rows is 2 ^N +2 ^{N + 1} <X ≦ 2 ^{N + 2} (N is a natural number), the dummy word line driving circuit arrangement region RD1 is the second (2 ^N +2 ^{N + 1} ) word lines It is preferable to arrange between the driving circuit and the (2 ^N +2 ^{N + 1} +1) -th row word line driving circuit. In particular, when the number X of memory cell rows is X = 2 ^N +2 ^{N + 1} +1 (N is a natural number), the dummy word line driving circuit arrangement region RD1 is replaced with the (2 ^N +2 ^{N + 1} ) th word line driving circuit. It is preferable to arrange it between the (2 ^N +2 ^{N + 1} +1) -th row word line driving circuits.

  Arranging the dummy word line driving circuit arrangement region RD1 and arranging the bypass lines L30 to L33 therein as in the present embodiment can be easily realized by a memory compiler. Therefore, the design of the semiconductor integrated circuit can be realized in a short TAT (turn around time). In addition, the layout in which the detour lines L30 to L33 are arranged in the dummy word line drive circuit arrangement region RD1 is easy to confirm, and the stability of the semiconductor integrated circuit product is increased (problems occur. It becomes difficult).

  Note that a DRAM cell, an SRAM cell, a ROM cell, an EEPROM cell, or the like can be used as the memory cell.

Next, a second embodiment of the present invention will be described.
FIG. 6 is a diagram showing an outline of a semiconductor integrated circuit according to the second embodiment of the present invention. In the present embodiment, the present invention is applied to an embedded memory.

  This semiconductor integrated circuit has a memory cell array 7. Within the memory cell array 7, the first to sixteenth memory cell arrangement regions RA0 to RA15, the first dummy memory cell arrangement region RB0, The 17th to 48th memory cell arrangement areas RA16 to RA47, the second dummy memory cell arrangement area RB1, and the 49th memory cell arrangement area RA48 are provided in order along the Y direction. In each memory cell arrangement region, 32 memory cells are arranged along the X direction. That is, (32 × 51) memory cells are arranged in the memory cell array 1. However, (32 × 2) memory cells arranged in the first and second dummy memory cell arrangement regions RB0 and RB1 are not used, and the number of memory cells used in the memory cell array 7 is (32 × 49). Each row of memory cells in the memory cell arrangement regions RA0 to RA48 is connected to 49 word lines WL0 to WL48.

  Each column of memory cells is connected to 32 pairs of bit lines BL0, BL0 bar to BL31, BL31 bar. Each of the 32 pairs of bit lines BL0, BL0 bar to BL31, BL31 bar crosses each other in the first and second dummy memory cell arrangement regions RB0, RB1. By crossing the bit lines in this way, the influence of noise can be reduced.

  The word lines WL0 to WL48 are connected to the word line decoding circuit 8, and the word line decoding circuit 8 is connected to the address input circuit 6. In the word line decoding circuit 8, the first to sixteenth word line driving circuit arrangement regions RC0 to RC15, the first dummy word line driving circuit arrangement region RD0, and the seventeenth to forty-eighth word line driving circuits. Arrangement regions RC16 to RC47, a second dummy word line drive circuit arrangement region RD1, and a 49th word line drive circuit arrangement region RD48 are sequentially provided along the Y direction. In the first to 49th word line driving circuit arrangement regions RC0 to RC48, word line driving circuits WD0 to WD48 are arranged. Word line drive circuits are also arranged in the first and second dummy word line drive circuit arrangement regions RD0 and RD1, but these word line drive circuits are dummy and are not used. Therefore, the number of word line driving circuits used in the word line decoding circuit 8 is 49.

  In the word line decoding circuit 8, a first group of wirings GL0 is arranged to extend to the first dummy word line driving circuit arrangement region RD0 along the Y direction. Further, the second and third group wirings GL1 and GL2 are arranged along the Y direction. The first group of wirings GL0 includes four wirings L0 to L3, the second group of wirings GL1 includes four wirings L4 to L7, and the third group of wirings GL2 includes four wirings. Wirings L8 to L11. Here, it is assumed that the wirings L0 to L11 are wirings of the second metal layer.

  In the word line decoding circuit 8, a fourth group of wirings GL3 is arranged along the Y direction from the second dummy word line driving circuit arrangement region RD1. The fourth group of wirings GL3 includes four wirings L20 to L23. Here, it is assumed that the wirings L20 to L23 are wirings of the second metal layer.

  The first dummy word line driving circuit arrangement region RD0 to the second dummy word line are arranged above the first group wiring GL0 and the fourth group wiring GL3 (herein, the third metal layer). A sixth group wiring GL5 is arranged along the Y direction up to the drive circuit arrangement region RD1. The sixth group wiring GL5 includes four detour wirings L60 to L63. The detour wirings L60 to L63 connect the first group of wirings GL0 (wirings L0 to L3) and the fourth group of wirings (wirings L20 to L23).

  Similar to the first embodiment described above (see FIG. 5), the contact portions connecting the detour wires L60 to L63 and the wires L0 to L3 are formed so as to be shifted in the Y direction from the contact portions adjacent in the X direction. If it does, it is possible to ensure the space | interval between the contact parts adjacent in a X direction. Similarly, if the contact portions connecting the detour wires L60 to L63 and the wires L20 to L23 are formed so as to be shifted in the Y direction from the contact portions adjacent in the X direction, the contact portions adjacent in the X direction are between It is possible to ensure an interval.

  The three input terminals of the word line driving circuits WD0 to WD15 are connected to one of each group of the first to third groups of wirings GL0 to GL2. The three input terminals of the word line driving circuits WD16 to WD47 are connected to one of each group of the second, third, and sixth groups of wirings GL1, GL2, and GL5. Further, the three input terminals of the word line drive circuit WD48 are connected to one of each group of the second to fourth groups of wirings GL1 to GL3. That is, the word line drive circuits WD16 to WD48 have one signal in the internal address signals IA0 to IA3, one signal in the internal address signals IA4 to IA7, and one signal in the internal address signals IA8 to IA11. An AND operation with the signal is performed, and the word lines WL0 to WL48 are driven according to the result of the AND operation.

  According to the present embodiment, it is possible to widen the interval in the Y direction between the contact portions of the detour wires L60 to L63 and the wires L0 to L3 and the contact portions of the detour wires L60 to L63 and the wires L20 to L23. it can. This makes layout easier.

In the present embodiment, the number of usable memory cell rows in the memory cell array 7 is 49 (= 2 ⁴ +2 ⁵ +1), but other row numbers may be used. The first dummy word line drive circuit arrangement region RD0 includes a word line drive circuit arrangement region RC15 in the 16th (= 2 ⁴ ) row and a word line drive circuit arrangement region RC16 in the 17th (= 2 ⁴ +1) row. The second dummy word line drive circuit arrangement region RD1 is arranged between the word line drive circuit arrangement region RC47 and the 49th (= 2 ⁴ +2 ⁵ ) row in the 48th (= 2 ⁴ +2 ⁵ ) row. +1) is provided between the word line driving circuit arrangement area RC48 in the row, and the detour wirings L60 to L63 are provided from the first dummy word line driving circuit arrangement area RD0 to the second dummy word line driving circuit arrangement area. Although it extends to RD1, a dummy word line driving circuit arrangement region may be provided at another position.

When the address signal is 6 bits wide, the maximum number of usable memory cells that the memory cell array can have is 64 (= 2 ⁶ ). A first dummy word line driving circuit arrangement region RD0 is provided between 16 rows (= 2 ⁴ ) corresponding to ¼ of the maximum number of rows 64 and the next 17 rows (= 2 ⁴ +1), Between the 48 rows (= 2 ⁴ +2 ⁵ ) corresponding to 3/4 of the maximum number of rows 64 and the next 49 rows (= 2 ⁴ +2 ⁵ +1), the second dummy word line drive circuit arrangement region RD1 It is preferable that the bypass wiring is extended from the first dummy word line drive circuit arrangement region to the second dummy word line drive circuit arrangement region.

When the number X of memory cell rows is 2 ^N +2 ^{N + 1} <X ≦ 2 ^{N + 2} (N is a natural number), the first dummy word line driver circuit arrangement region is arranged in the (2 ^N ) th row of word line driver circuits. provided between the region and the (2 N ⁺¹⁾ word line driver circuit arrangement region of the rows, and a word line drive circuit arrangement region of the second dummy first (2 N ⁺² N + ¹⁾ word line driver circuit arrangement region of the line A bypass wiring is provided from the first dummy word line drive circuit arrangement region to the second dummy word line drive circuit arrangement region, provided between the (2 ^N +2 ^{N + 1} +1) th row word line drive circuit arrangement region. If present, it is preferable. In particular, when the number X of memory cell rows is X = 2 ^N +2 ^{N + 1} +1 (N is a natural number), the first dummy word line driver circuit arrangement region is arranged in the (2 ^N ) th row of word line driver circuits. provided between the region and the (2 N ⁺¹⁾ word line driver circuit arrangement region of the rows, and a word line drive circuit arrangement region of the second dummy first (2 N ⁺² N + ¹⁾ word line driver circuit arrangement region of the line A bypass wiring is provided from the first dummy word line drive circuit arrangement region to the second dummy word line drive circuit arrangement region, provided between the (2 ^N +2 ^{N + 1} +1) th row word line drive circuit arrangement region. If present, it is preferable.

  As in the present embodiment, the first and second dummy word line drive circuit arrangement regions RD0 and RD1 are provided, and the bypass wiring extends from the first dummy word line drive circuit arrangement region to the second dummy word line drive circuit. Extending to the arrangement area can be easily realized by a memory compiler.

  The present invention is applicable to a semiconductor integrated circuit having a memory cell array including a plurality of rows of memory cells. In particular, it can be used for embedded memory.

1 is a diagram showing an outline of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing an internal circuit configuration of an address input circuit 6 in FIG. 1. The figure which shows the truth table of an address signal and an internal address signal. 2 is a diagram showing a hierarchical structure of a word line decoding circuit 5 and an address input circuit 6 in FIG. The figure which shows the layout of wiring L30-L33 periphery of FIG. The figure which shows the outline | summary of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. The figure which shows the outline | summary of the conventional semiconductor integrated circuit. 2 is a diagram showing a hierarchical structure of a word line decoding circuit 55 and an address input circuit 56. FIG.

Explanation of symbols

  1,7,51 memory cell array, 2,52 sense amplifier circuit, 3,53 I / O circuit, 4,54 control circuit, 5,8,55 word line decoding circuit, 6,56 address input circuit, 31,61 impurities Diffusion region, 32, 62 gate electrode, 33, 63 gate insulating film, RA0, RA1, ... memory cell placement region, RB0, RB1 dummy memory cell placement region, RC0, RC1, ... word line drive circuit placement region, RD0, RD1 dummy word line driving circuit arrangement region, WL0, WL1,... Word line, BL0, BL0 bar,... Bit line, WD0, WD1,... Word line driving circuit, L0, L1,. , ... Wiring, INV0, INV1, ... Inverter, Tr1, Tr2, ... Transistor

Claims (12)

A plurality of memory cells arranged in a matrix of first to H-th columns (H is a natural number) in a first direction and first to J-th rows (J is a natural number of 2 or more) in a second direction; A memory cell array in which a first dummy region is provided between a memory cell in the Lth row (L is a natural number smaller than J) and a memory cell in the (L + 1) th row;
First to Hth bit line pairs connected to memory cells in the first to Hth columns, each bit line pair intersecting each other in the first dummy region. A bit line pair;
First to Jth word lines connected to the first to Jth rows of the memory cell array;
A first circuit for decoding a multi-bit address signal input from an external circuit and outputting a multi-bit internal address signal;
A second circuit for activating the first to Jth word lines based on the internal address signal;
A semiconductor integrated circuit comprising:
The second circuit comprises:
A first to a Jth third circuit arranged along the second direction, wherein the Lth third circuit of the first to the Jth third circuits and the first The first to J-th third circuits in which a second dummy region is provided between the (L + 1) -th third circuit of the J-th third circuit,
A first group of wirings extending along the second direction to the second dummy region, to which upper bits of the internal address signal are supplied from the first circuit;
Wiring of second to Mth groups (M is a natural number of 2 or more) extending along the second direction and supplied with bits other than the upper bits of the internal address signal from the first circuit When,
A (M + 1) th group of wirings extending from the second dummy region along the second direction;
A group of detour wirings connecting between the first group wirings and the (M + 1) th group wirings, the first group wirings and the (M + 1) th wirings in the second dummy region; The group of detour wirings arranged above the group wiring; and
Comprising
The first to L-th third circuits of the first to J-th third circuits are connected to one of each group of the first to M-th group wirings and connected to each other. Activating the first to Lth word lines of the first to Jth word lines based on a signal on a book wiring;
Of the first to Jth third circuits, the (L + 1) th to Jth third circuits are connected to one of each of the second to (M + 1) th group wirings, A (L + 1) -th to J-th word line among the first to J-th word lines is activated based on signals on M connected wirings.   H dummy memory cells are arranged along the first direction in the first dummy region, and the dummy third circuit is arranged in the second dummy region. The semiconductor integrated circuit according to claim 1. 3. The semiconductor integrated circuit according to claim ¹ , wherein L = 2 ^N +2 ^{N + 1} and L <J ≦ 2 ^{N + 2} (N is a natural number). A plurality of memory cells arranged in a matrix of first to H-th columns (H is a natural number) in a first direction and first to J-th rows (J is a natural number of 2 or more) in a second direction; A first dummy region is provided between a memory cell in the Kth row (K is a natural number) and a memory cell in the (K + 1) th row, and the Lth row (L is a natural number greater than K and smaller than J). A memory cell array in which a second dummy region is provided between the memory cells and the memory cells in the (L + 1) -th row;
First to H-th bit line pairs connected to memory cells in the first to H-th columns, each bit line pair intersecting each other in the first and second dummy regions. An H-th bit line pair;
First to Jth word lines connected to the first to Jth rows of the memory cell array;
A first circuit for decoding a multi-bit address signal input from an external circuit and outputting a multi-bit internal address signal;
A second circuit for activating the first to Jth word lines based on the internal address signal;
A semiconductor integrated circuit comprising:
The second circuit comprises:
A first to a Jth third circuit arranged along the second direction, wherein the Kth third circuit of the first to the Jth third circuits and the first A third dummy region is provided between the (K + 1) -th third circuit and the (J + 1) -th third circuit, and among the first-J-th third circuit, The first to Jth dummy regions are provided between the third L circuit and the (L + 1) th third circuit among the first to Jth third circuits. A third circuit of
A first group of wirings extending along the second direction to the third dummy region, to which upper bits of the internal address signal are supplied from the first circuit;
Wiring of second to Mth groups (M is a natural number of 2 or more) extending along the second direction and supplied with bits other than the upper bits of the internal address signal from the first circuit When,
A (M + 1) th group of wirings extending along the second direction from the fourth dummy region;
A group of detour wirings connecting between the first group wirings and the (M + 1) th group wirings in the second direction from the third dummy region to the fourth dummy region; Extending along the first group of wirings and disposed in an upper layer than the first group of wirings and the (M + 1) th group of wirings;
Comprising
The first to K-th third circuits of the first to J-th third circuits are connected to one of each group of the first to M-th group wirings and connected to each other. Activating the first to Kth word lines of the first to Jth word lines based on a signal on a book wiring;
Of the first to Jth third circuits, the (K + 1) th to Lth third circuits are one of each of the second to Mth group wirings and the first group of bypass wirings. And (K + 1) th to Lth word lines among the first to Jth word lines are activated based on signals on the M connected wirings,
Of the first to Jth third circuits, the (L + 1) th to Jth third circuits are connected to one of each of the second to (M + 1) th group wirings, A (L + 1) -th to J-th word line among the first to J-th word lines is activated based on signals on M connected wirings.   H dummy memory cells are arranged in the first and second dummy regions along the first direction, and the dummy third circuit is provided in the third and fourth dummy regions. The semiconductor integrated circuit according to claim 4, wherein: 6. The semiconductor integrated circuit according to claim 4, wherein K = ^2N , L = K + ^{2N + 1} , and L <J≤2N ^{+ 2} (N is a natural number).   The semiconductor integrated circuit according to claim 3, wherein J = L + 1. First to Jth memory cell arrangement regions are provided in the memory cell array, and first to Jth rows of memory cells are arranged in the first to Jth memory cell arrangement regions,
1st-Jth circuit arrangement | positioning area | region is provided in the said 2nd circuit, The said 1st-Jth 2nd circuit is arrange | positioned in the said 1st-Jth circuit arrangement | positioning area | region. Item 8. The semiconductor integrated circuit according to any one of Items 1 to 7.   Each of the first group of contact portions connecting the first group of bypass wirings and the first group of wirings is formed so as to be displaced in the second direction from an adjacent contact portion in the first direction. And the second group of contact portions connecting the first group of detour wires and the (M + 1) th group of wires are displaced in the second direction from the adjacent contact portions in the first direction. The semiconductor integrated circuit according to claim 1, formed as described above.   The plurality of wirings that connect between the first circuit and the first group of wirings are formed in an upper layer than the first group of wirings. Semiconductor integrated circuit. A computer-implemented method for designing a semiconductor integrated circuit comprising:
A plurality of memory cells arranged in a matrix of first to H-th columns (H is a natural number) in a first direction and first to J-th rows (J is a natural number of 2 or more) in a second direction; (A) disposing a memory cell array in which a first dummy region is provided between a memory cell in the Lth row (L is a natural number smaller than J) and a memory cell in the (L + 1) th row;
First to Hth bit line pairs connected to memory cells in the first to Hth columns, each bit line pair intersecting each other in the first dummy region. Placing a bit line pair (b);
Disposing first to Jth word lines connected to the first to Jth rows of the memory cell array;
Disposing a first circuit for decoding a multi-bit address signal input from an external circuit and outputting a multi-bit internal address signal;
Disposing a second circuit for activating the first to Jth word lines based on the internal address signal;
Comprising
Step (e) is
A first to a Jth third circuit arranged along the second direction, wherein the Lth third circuit of the first to the Jth third circuits and the first Arranging the first to Jth third circuits in which a second dummy region is provided between the (L + 1) th and third (L + 1) third circuits of the Jth third circuit ( e1)
A step (e2) of arranging a first group of wirings extending along the second direction to the second dummy region and in which upper bits of the internal address signal are supplied from the first circuit;
Wiring of second to Mth groups (M is a natural number of 2 or more) extending along the second direction and supplied with bits other than the upper bits of the internal address signal from the first circuit Placing (e3),
Placing (M + 1) th group of wirings extending along the second direction from the second dummy region (e4);
A group of detour wirings connecting between the first group wirings and the (M + 1) th group wirings, the first group wirings and the (M + 1) th wirings in the second dummy region; A step (e5) of arranging the one group of detour wirings arranged in an upper layer than the group wiring;
A plurality of wirings such that the first to Lth third circuits of the first to Jth third circuits are connected to one of each of the first to Mth group wirings. Arranging (e6),
Of the first to Jth third circuits, the (L + 1) th to Jth third circuits are connected to one of each of the second to (M + 1) th group wirings. A step (e7) of arranging a plurality of wires in
Including
The first to L-th third circuits of the first to J-th third circuits are connected to each other based on a signal on one wiring of each group of the first to M-th group wirings. Activating the first to Lth word lines among the Jth word lines,
Of the first to Jth third circuits, the (L + 1) th to Jth third circuits are used as signals on one wiring in each of the second to (M + 1) th group wirings. A method for designing a semiconductor integrated circuit, comprising: activating (L + 1) to Jth word lines among first to Jth word lines. A computer-implemented method for designing a semiconductor integrated circuit comprising:
A plurality of memory cells arranged in a matrix of first to H-th columns (H is a natural number) in a first direction and first to J-th rows (J is a natural number of 2 or more) in a second direction; A first dummy region is provided between a memory cell in the Kth row (K is a natural number) and a memory cell in the (K + 1) th row, and the Lth row (L is a natural number greater than K and smaller than J). Placing a memory cell array in which a second dummy region is provided between the memory cells and the memory cells in the (L + 1) th row;
First to H-th bit line pairs connected to memory cells in the first to H-th columns, each bit line pair intersecting each other in the first and second dummy regions. Arranging the H-th bit line pair (b);
Disposing first to Jth word lines connected to the first to Jth rows of the memory cell array;
Disposing a first circuit for decoding a multi-bit address signal input from an external circuit and outputting a multi-bit internal address signal;
Disposing a second circuit for activating the first to Jth word lines based on the internal address signal;
Comprising
Step (e) is
A first to a Jth third circuit arranged along the second direction, wherein the Kth third circuit of the first to the Jth third circuits and the first A third dummy region is provided between the (K + 1) -th third circuit and the (J + 1) -th third circuit, and among the first-J-th third circuit, The first to Jth dummy regions are provided between the third L circuit and the (L + 1) th third circuit among the first to Jth third circuits. Arranging (e1) a third circuit of
A step (e2) of arranging a first group of wirings extending in the second direction to the third dummy region and having higher bits of the internal address signal supplied from the first circuit;
Wiring of second to Mth groups (M is a natural number of 2 or more) extending along the second direction and supplied with bits other than the upper bits of the internal address signal from the first circuit Placing (e3),
(E4) arranging a (M + 1) th group of wirings extending from the fourth dummy region along the second direction;
A group of detour wirings connecting between the first group wirings and the (M + 1) th group wirings in the second direction from the third dummy region to the fourth dummy region; A step (e5) of extending the first group of wirings and disposing the first group of bypass wirings disposed above the first group of wirings and the (M + 1) th group of wirings;
A plurality of first to Kth third circuits of the first to Jth third circuits are connected to one of each of the first to Mth group wirings. Placing the wiring (e6);
Of the first to Jth third circuits, the (K + 1) th to Lth third circuits are one in each of the groups of the second to Mth groups of wirings and the first group of bypass wirings. A step (e7) of arranging a plurality of wirings so as to be connected to
Of the first to Jth third circuits, the (L + 1) th to Jth third circuits are connected to one of each of the second to (M + 1) th group wirings. A step (e8) of arranging a plurality of wirings;
Including
The first to K-th third circuits of the first to J-th third circuits are based on signals on one wiring in each group of the first to M-th group wirings. Activating first to Kth word lines among the first to Jth word lines;
Of the first to Jth third circuits, the (K + 1) th to Lth third circuits are one of each of the second to Mth group wirings and the first group of bypass wirings. Activating the (K + 1) -th to L-th word lines of the first to J-th word lines based on signals on the respective wirings;
Of the first to Jth third circuits, the (L + 1) th to Jth third circuits are on one wiring in each of the second to (M + 1) th group wirings. A method for designing a semiconductor integrated circuit, comprising: activating (L + 1) to Jth word lines among the first to Jth word lines based on a signal.

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