JP2007179480A - Memory controller and flash memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller and a flash memory system in which dummy data to be added is minimized in encoding data with Reed-Solomon codes. <P>SOLUTION: User data supplied to the flash memory is successively connected in a predetermined bite number unit, and the connected user data is cut out in a predetermined symbol length unit. Dummy data is added only to user data of a length less than the symbol length which is left as a result of this cutting-out in symbol length unit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  In recent years, a flash memory, which is a non-volatile storage medium, has been developed and is widely used as a storage medium for information devices (host systems) such as digital cameras.

  As the data handled by such devices has increased in capacity, flash memory has been increased in capacity and density. Such a flash memory having a large capacity and a high density is applied to a field requiring high reliability such as storing an OS (Operating System) of a host system.

  A NAND flash memory is characterized by a large capacity and a high density, and is one type of flash memory that is particularly frequently used in recent years. In the NAND flash memory, data is managed in units of 512 bytes, which is one sector, and a redundant area of 16 bytes is given to one sector.

  When reading data from the NAND flash memory or writing data to the NAND flash memory, read / write errors may occur. Conventionally, error correction has been performed for these errors by using a simple code such as a Hamming code. However, in order to apply the flash memory to a field requiring high reliability such as storing the OS of the host system, a strong error correction code capable of correcting many bits is required. As such an error correction code, for example, a Reed-Solomon code is known.

Reed-Solomon codes have mathematical limitations on the maximum code length that can be encoded. When the number of bits of one symbol is n, the maximum code length (maximum number of symbols) N of the Reed-Solomon code is (2 ⁿ −1). That is, if the number of bits of one symbol is 8, the Reed-Solomon code can encode up to a code length of 255 symbols including an error correction code (ECC) generated by the Reed-Solomon code.

  In the NAND flash memory, data is managed in units of 512 bytes, which is one sector. When the data of one sector (512 bytes) is encoded by the Reed-Solomon code, n ≧ 10, and one symbol must be encoded with a minimum of 10 bits (the maximum number of symbols is 1023).

However, the data bus of the flash memory usually has a bus width of 1 byte or a plurality of bytes, and there is a problem that the code length of one symbol does not necessarily match the bus width of the data bus. In Patent Document 1, when a 512-byte data is encoded by a Reed-Solomon code in a flash memory having a data bus width of 8 bits, a symbol length is set to 10 bits, and 1-byte (8-bit) data is sequentially converted. There is disclosed a technique of reading and adding 2-bit dummy data to each and encoding it as apparently 10-bit data (that is, handling 512-byte data as a 512-symbol code). Further, in Patent Document 1, in a flash memory having a data bus width of 16 bits, when 512 bytes of data are encoded by Reed-Solomon code, the symbol length is set to 10 bits, and 16 bits of data are sequentially read out. A technique is disclosed in which, after being divided into two pieces of 1-byte (8-bit) data, 2-bit dummy data is added to each of them, and the data is coded as two pieces of apparent 10-bit data.
Japanese Patent Laid-Open No. 9-274591

  In the above-described technique, when data is encoded by the Reed-Solomon code, dummy data for matching the symbol length is added to 1-byte (8-bit) data. As a result, when 1 byte (8 bits) of data is handled as 1 symbol and the symbol length is 10 bits, 128 bytes (1024 bits) of dummy data is added to 512 bytes of data. The efficiency of data error correction is reduced.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory controller and a flash memory system with less dummy data added when data is encoded by Reed-Solomon codes.

In order to solve the above problems, a memory controller according to the first aspect of the present invention provides:
A memory controller that controls access to a flash memory in response to a command from a host system,
Write data supply means for supplying user data to be written to the user area of the flash memory;
Symbol data supply means for receiving the user data, sequentially connecting the user data until a predetermined number of bytes is reached, and sequentially cutting out and outputting the connected data in units of a predetermined symbol length;
Dummy data adding means for adding predetermined dummy data to the final data when the data length of the final data extracted from the user data of the predetermined number of bytes is less than the predetermined symbol length;
An error correction code generation unit configured to generate an error correction code composed of a Reed-Solomon code for the user data of the predetermined number of bytes based on data output in symbol length units from the symbol data supply unit;
Conversion means for performing conversion processing on the error correction code so that the error correction code matches the erased state of the flash memory when the user data of the predetermined number of bytes matches the erased state of the flash memory When,
Redundant data writing means for writing the error correction code subjected to the conversion process into a redundant area corresponding to a user area in which the user data of the predetermined number of bytes is written;
It is characterized by providing.

User data reading means for reading user data written in the user area;
Redundant data reading means for reading the error correction code subjected to the conversion process written in the redundant area;
Inverse conversion means for returning the error correction code subjected to the conversion processing read by the redundant data reading means to the error correction code before the conversion processing;
Based on the error correction code before the conversion process supplied from the inverse conversion means, an error correction code generation means for correcting an error in the symbol length unit supplied via the symbol data supply means;
May be further provided.

  The predetermined number of bytes is preferably 512 bytes.

  The symbol data supply unit may sequentially connect the user data in units of the same number of bits as the bus width of the flash memory, and cut out the connected data in units of a predetermined symbol length.

In order to solve the above problems, a flash memory system according to a second aspect of the present invention provides:
The above memory controller;
Flash memory,
It is comprised from these.

  According to the present invention, user data supplied to the flash memory is sequentially connected in units of a predetermined number of bytes, the connected user data is cut out in units of a predetermined symbol length, and configured by a Reed-Solomon code based on the cut out symbol data Generated error correction codes are generated. Therefore, since dummy data is not added to user data other than the last remaining symbol length cut out in symbol length units, error correction can be performed by reducing the number of symbols subject to error correction compared to the conventional case. The ratio that can be made can be increased.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is composed of a NAND flash memory. The NAND flash memory is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data by copying data between a register and a memory cell.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is shown in FIG. The address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages.

  In the flash memory shown in FIG. 2, one page is composed of a user area 25 of 1 sector (512 bytes) and a redundant area 26 of 16 bytes, and one physical block is composed of 32 pages. . There is a flash memory in which one page is composed of a 4-sector user area and a 64-byte redundant area, and one physical block is composed of 64 pages. The user area 25 is an area for storing user data supplied from the host system 4.

  The redundant area 26 is an area for storing additional data such as ECC (Error Correcting Code), logical address information, and block status (flag).

  The ECC is data for detecting and correcting an error included in data stored in the user area 25, and is generated by an ECC block described later.

  The logical address information is information for specifying a logical block corresponding to the data when valid data is stored in the user area 25 of at least one page included in each physical block of the flash memory 2. It is.

  For a physical block in which valid data is not stored in the user area 25, logical address information is not stored in the redundant area 26 of the block.

  Therefore, by determining whether or not logical address information is stored in the redundant area 26, it is possible to determine whether or not valid data is stored in the physical block including the redundant area 26. . That is, when logical address information is not stored in the redundant area 26, it is determined that valid data is not stored in the physical block.

  As described above, one physical block includes a plurality of pages. Data cannot be overwritten on these pages. For this reason, even when only the data stored in one page is rewritten, the data stored in all the pages in the physical block including the page must be rewritten.

  That is, in normal data rewriting, data stored in all pages of a physical block including a page to be rewritten is written to another erased physical block. At this time, as for the data stored in the page where the data is not changed, the previously stored data is rewritten as it is.

  In rewriting data as described above, normally, the rewritten data is written in a physical block different from the physical block stored previously. For this reason, the correspondence relationship between the logical block address and the physical block address dynamically changes every time data is rewritten in the flash memory 2.

  Therefore, it is necessary to manage the correspondence between the logical block and the physical block, and this correspondence is usually managed by the address conversion table. This address conversion table is created based on the logical address information stored in the redundant area 26 of each physical block. Note that such a dynamic address management method is a method generally used in a memory system using a flash memory as described above.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area 26.

  Such a flash memory 2 receives data, address information, internal commands, and the like from the controller 3 and performs various processes such as a data read process, a write process, a block erase process, and a transfer process.

  Here, the internal command is a command for the controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the controller 3. In contrast, the external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC block 11, and a ROM (Read Only Memory) 12. And. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set defining various processes from the ROM 12, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute processes.

  The host interface block 7 exchanges data, address information, status information, external commands, and the like with the host system 4. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14. More specifically, the flash memory interface block 10 includes an address processing unit, a command register, an instruction processing block, and the like.

  The flash memory interface block 10 supplies the flash memory 2 with internal commands, address information, and the like output from the instruction processing block, thereby causing the flash memory 2 to execute reading and writing.

  The ECC block 11 generates an ECC added to data (user data) to be written to the flash memory 2 and detects an error included in the read data based on the ECC added to the data read from the flash memory 2 ·correct.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines a processing procedure such as creation of an address conversion table, for example.

  Here, the ECC block 11 will be described with reference to FIGS. FIG. 3 is a diagram for explaining the operation of the ECC block 11 in the process of writing data to the flash memory 2. FIG. 4 is a diagram for explaining the operation of the ECC block 11 in the process of reading data from the flash memory 2.

  The ECC block 11 includes an ECC register 30, a buffer register 32, an error correction code / decoder 33, and a mask circuit 34.

The ECC register 30 temporarily holds the error correction code read from the redundant area 26 of the flash memory 2.
The buffer register 32 is connected to the internal bus 14 that connects the buffer 9 and the flash memory 2, and temporarily holds data read from the buffer 9 or the user area 25. The data bus of the flash memory 2 connected to the internal bus 14 has a bus width of 8 bits and transmits data in units of 8 bits. Corresponding to this, as will be described later with reference to FIG. 5, the buffer register 32 includes two 8-bit registers.
The error correction code / decoder 33 receives symbol data obtained by converting user data to be written to the flash memory 2 from the buffer register 32 into a predetermined symbol length of the Reed-Solomon code at the time of writing processing to the flash memory 2, and the symbol data Based on the above, an error correction code of the Reed-Solomon code is generated. During the reading process from the flash memory 2, user data is received from the flash memory 2 and an error correction code is received from the mask circuit 34, and an error in the read data is detected and corrected based on the error correction code.
The mask circuit 34 performs a preset first conversion process on the error correction code input from the error correction code / decoder 33 and reads the error correction code read from the redundant area 26 of the flash memory 2. Is subjected to a second conversion process.
In this first conversion process, when all 512-byte (4096 bits) bit data written to the user area 25 of the flash memory 2 is in the erased state (logical value “1”), Conversion is performed so that all bit data is in an erased state (logical value “1”).
When the conventional Hamming code is used, when all 4096-bit data is logical “1” (erased state), all bits of the error correction code generated by the error correction code / decoder 33 are “1”. When the Reed-Solomon code is used, the error correction code generated by the error correction code / decoder 22 is used even if all the 4096-bit data is logical “1” (erasure state). All of the bits of do not become "1". In order to eliminate inconsistency when this Reed-Solomon code is used, a first conversion process is performed on the error correction code (ECC) generated by the error correction code / decoder 33.
On the other hand, in the second conversion process, the error correction code (ECC-M) subjected to the first conversion read from the redundant area 26 of the flash memory 2 is converted into an error correction code (ECC) before the first conversion. Conversion is performed so as to return to). Further, the error correction code / decoder 33 is based on the error correction code (ECC) subjected to the second conversion process, that is, the error correction code before the first conversion, in the user area 25 of the flash memory 2. Detects and corrects errors contained in the data read from.

  Next, the configuration of the buffer register 32 will be described with reference to FIG.

  The buffer register 32 is connected to the internal bus 14, and includes two registers of a first register 40 and a second register 41 having a bit length of 8 bits having the same bus width as the data bus of the flash memory 2. Therefore, the buffer register 32 can store two 8-bit data. The buffer register 32 includes a read position pointer RP indicating a read position.

  In this embodiment, the symbol length based on the Reed-Solomon code is 10 bits, and the error correction code / decoder 33 reads the data for each symbol length (10 bits) and performs encoding / decoding. The error correction code / decoder 33 generates an 8-symbol error correction code (ECC), and performs 5-symbol error detection and 4-symbol error correction based on the 8-symbol error correction code (ECC). Is set to be able to.

  The operation of the ECC block 11 when 512-byte data given from the host system 4 is written in the user area 25 is described below with reference to FIG. 3, taking a Reed-Solomon code with 10 bits as one symbol as an example. .

  Data provided from the host system 4 is temporarily stored in the buffer 9, and the stored data is written to the flash memory 2 via the internal bus 14.

  FIG. 6A shows 512-byte data output from the buffer 9 to the internal bus 14 in units of 8 bits, which is the bus width of the data bus of the flash memory 2. The data stored in the buffer 9 is supplied to the flash memory 2 via the internal bus 14 in units of 8 bits in the order of Data0, Data1, and Data2 in order from the top, and is supplied to the flash memory 2 as user data. Is written to. These 8-bit data are counted from the least significant bit to the seventh bit in the order of the 0th bit and the 1st bit. In addition, FIG. 6A describes Data1 [1: 0], which means a bit string (2 bits) from the 0th bit to the 1st bit of Data1.

The data output from the buffer 9 in units of 8 bits is also supplied to the buffer register 32 via the internal bus 14.
The buffer register 32 temporarily holds the data supplied from the buffer 9 and outputs the data to the error correction code / decoder 33 by a predetermined symbol length (10 bits). Also, 512-byte data from Data 0 to Data 511 is output to the error correction code / decoder 33 by a predetermined symbol length (10 bits), and finally, data less than the predetermined symbol length (10 bits) remains. In this case, data of a predetermined symbol length (10 bits) with dummy data added is generated and output to the error correction code / decoder 33.
FIG. 6B shows data of a predetermined symbol length (10 bits) output from the buffer register 32 to the error correction code / decoder 33. For example, one symbol data is generated by Data0 [7: 0] and Data1 [1: 0], and one symbol data is generated by Data1 [7: 2] and Data2 [3: 0]. In this way, 512-byte data of Data 0 to Data 511 is concatenated, cut out in units of a predetermined symbol length (10 bits), and finally, 4-bit dummy data is added to generate 410 symbol data. .

  The error correction code / decoder 33 generates an 8-symbol error correction code (ECC) based on the data supplied from the buffer register 32. The 8-symbol error correction code is subjected to the first conversion process by the mask circuit 34, and the error correction code (ECC-M) subjected to the first conversion process is written in the redundant area 26 of the flash memory 2. . When writing to the redundant area 26 of the flash memory 2, the 8-symbol error correction code (ECC-M) subjected to the first conversion process is converted into 8-bit bit string data (10 bytes). .

Next, the operation of the ECC block 11 in the reading process will be described with reference to FIG.
The 512-byte data read from the user area 25 of the flash memory 2 is held in the buffer 9 via the internal bus 14 and is also transferred to the buffer register 32 via the internal bus 14. The buffer register 32 outputs the transferred 512-byte data to the error correction code / decoder 33 by a predetermined symbol length (10 bits). Also, the read 512-byte data is output to the error correction code / decoder 33 by a predetermined symbol length (10 bits), and finally, data that does not satisfy the predetermined symbol length (10 bits) remains. In this case, data of a predetermined symbol length (10 bits) with dummy data added is generated and output to the error correction code / decoder 33.

  On the other hand, the mask circuit 34 performs a second conversion process on the error correction code (ECC-M) read from the redundant area 26 and subjected to the first conversion process, and performs an error before the first conversion process. Returning to the correction code (ECC), the error correction code (ECC) subjected to the second conversion process is output to the error correction code / decoder 33. The error correction code (ECC-M) subjected to the first conversion process read from the redundant area 26 is 8-bit bit string data (10 bytes), and therefore has a predetermined symbol length (10 bits). After being converted into data (8 symbols), the second conversion process described above is performed.

  The error correction code / decoder 33 is stored in the buffer 9 based on the 410-symbol symbol data supplied from the buffer register 32 and the 8-symbol error correction code (ECC) supplied from the mask circuit 34. An error of an error correction code (ECC) stored in user data or the ECC register 30 can be detected and corrected. Here, detection and correction of user data and ECC errors are performed in symbol units.

  Next, the operation of the buffer register 32 will be described with reference to FIGS.

FIGS. 7 and 8 show the inputs input from the buffer 9 to the buffer register 32 (first register 40 and second register 41) in units of the bus width of the data bus of the flash memory 2 (8 bits in FIGS. 7 and 8). Data (user data written to the flash memory 2), retained data held in the buffer register 32, and output data output from the buffer register 32 are shown.
The buffer register 32 receives 512 bytes of input data from Data 0 to Data 511 in units of the bus width (8 bits in FIGS. 7 and 8) of the data bus of the flash memory 2. Input data of Data 0 to Data 511 is alternately input to the first register 40 and the second register 41. That is, Data0 is input to the first register 40, Data1 is input to the second register 41, Data2 is input to the first register 40, Data3 is input to the second register 41, and so on up to Data511. Input data is sequentially input to the buffer register 32. As a result, the input data input to the buffer register 32 is held in the first register 40 or the second register 41.
On the other hand, the held data held in the first register 40 or the second register 40 is output from the buffer register 32 in units of the symbol length of Reed-Solomon code (10 bits in FIGS. 7 and 8), and the error correction code / decoder 33.

  The operation of the buffer register 32 will be described step by step.

  First, as shown in FIG. 7A, Data0 (Data0_0 to Data0_7) and Data1 (Data1_0 to Data1_7) are input to the buffer register 32, Data0 (Data0_0 to Data0_7) is input to the first register 40, and Data1 (Data1_0 to Data1_7) is input. It is held in the second register 41. Here, the read position pointer RP is set to the 0th bit of the first register 40, counting from the 0th bit and the 1st bit from the least significant bit. Bit data is output as output data. That is, output data in which Data1_0 to Data1_1 held in the second register 41 are connected to Data1_0 to Data1_7 held in the first register 40 is output. Thereafter, the setting of the read position pointer RP is changed to the second bit of the second register 41.

  When the setting of the read position pointer RP is changed to the second bit of the second register 41, as shown in FIG. 7B, Data2 (Data2_0 to Data2_7) is input to the buffer register 32, and Data2 (Data2_0 to Data2_7) is the first bit. 1 is held in one register 40. Here, since the read position pointer RP is set to the second bit of the second register 41, data for 10 bits from the second bit of the second register 41 is output as output data. In other words, output data in which Data1_2 to Data1_7 held in the second register 41 are connected to Data2_0 to Data2_3 held in the first register 40 is output. Thereafter, the setting of the read position pointer RP is changed to the fourth bit of the first register 40.

  When the setting of the read position pointer RP is changed to the fourth bit of the first register 40, as shown in FIG. 7C, Data3 (Data3_0 to Data3_7) is input to the buffer register 32, and Data3 (Data3_0 to Data3_7) is the first. 2 is held in the register 41. Here, since the read position pointer RP is set to the fourth bit of the first register 40, the data for 10 bits from the fourth bit of the first register 40 is output as output data. That is, output data obtained by connecting Data3_0 to Data3_5 held in the second register 41 to Data2_4 to Data2_7 held in the first register 40 is output. Thereafter, the setting of the read position pointer RP is changed to the sixth bit of the second register 41.

When the setting of the read position pointer RP is changed to the sixth bit of the second register 41, as shown in FIG. 7D, Data4 (Data4_0 to Data4_7) is input to the buffer register 32, and Data4 (Data4_0 to Data4_7) is the first. 1 is held in one register 40. Here, since the read position pointer RP is set to the 6th bit of the second register 41, 10-bit data from the 6th bit of the second register 41 is output as output data. That is, output data obtained by connecting Data4_0 to Data4_7 held in the first register 40 to Data3_6 to Data3_7 held in the second register 41 is output. Thereafter, the setting of the read position pointer RP is changed to the 0th bit of the second register 41.
The input data after Data5 (Data5_0 to Data5_7) also includes the first register 40 or the second register 41 in the order of Data5 (Data5_0 to Data5_7) to the second register 41 and Data6 (Data6_0 to Data6_7) to the first register 40. And 10 bits of data from the bits set in the read position pointer RP are sequentially output as output data.

  The 512-byte input data input to the buffer register 32 is output as output data in symbol length (10 bits) units, and dummy data is added to data less than the last symbol length (10 bits). The addition of the dummy data will be described with reference to FIG.

  FIG. 8 shows input data after Data 510 input to the buffer register 32 and output data output from the buffer register 32. Data 510 (Data 510 — 0 to Data 510 — 7) input to the buffer register 32 is held in the first register 40, and Data 511 (Data 511 — 0 to Data 511 — 7) is held in the second register 41. Here, as shown in FIG. 8 (i), since the read position pointer RP is set to the 0th bit of the first register 40, 10-bit data from the 0th bit of the first register 40 is output data. Is output as That is, output data in which Data 510_0 to Data 510_7 held in the first register 40 and Data 511_0 to Data 511_1 held in the second register 41 are connected is output. Thereafter, the setting of the read position pointer RP is changed to the second bit of the second register 41. Further, as shown in FIG. 8 (ii), 4-bit dummy data is added to the 6 bits of Data511_2 to Data511_7 and is output from the buffer register 32 as 10-bit output data.

  It should be noted that the number of bits of data that is less than the last remaining symbol length is unit data for generating a correction code (ECC) using a Reed-Solomon code (in this embodiment, 512-byte user data of Data0 to Data511). This coincides with the remainder when the number of all bits included is divided by the number of bits of a predetermined symbol length (10 bits in this embodiment). Further, the logical value (“0” or “1”) of the dummy data added to the data less than the last symbol length can be set as appropriate.

  As described above, in the present embodiment, two registers having the same bus width as the data bus of the flash memory 2 are provided, and the user data supplied to the flash memory 2 is sequentially held in these two registers and held. The user data thus supplied is supplied to the error correction code / decoder 33 in units of a predetermined symbol length. At this time, the user data is concatenated in the order of supply to the flash memory 2, cut out in units of a predetermined symbol length, supplied to the correction code / decoder 33, and the user data other than the last remaining user symbol length. No dummy data is added. Therefore, the number of symbols subject to error correction can be reduced as compared with the prior art. For example, if the predetermined symbol length is 10 bits, conventionally, 2-bit dummy data is added to 1-byte data to form 10-bit symbol data, so that 512-symbol symbol data is generated from 512-byte user data. However, if symbol data is generated as described above, the number of generated symbols can be reduced to 410 symbols.

  In error correction using a Reed-Solomon code, ½ of the number of symbols of the generated error correction code matches the number of symbols that can be corrected. For example, when an 8-symbol error correction code is generated, 4-symbol error correction is possible. Therefore, if the number of symbols of the error correction code is the same, an error of the same number of symbols can be corrected. Therefore, the ratio of error correction can be increased by reducing the number of symbols subject to error correction. . The number of symbols of the error correction code generated by the error correction code / decoder 33 can be set as appropriate according to the capacity of the error correction code that can be stored in the redundant area 26.

  As described above, the memory controller according to the present invention sequentially concatenates user data supplied to the flash memory 2, cuts out the concatenated user data in units of a predetermined symbol length, and supplies it to the error correction code / decoder 33. ing. Therefore, since no dummy data is added except for user data less than the last remaining symbol length, the number of symbols subject to error correction should be reduced compared to the prior art, and the error correction ratio should be increased. Can do.

  The present invention is not limited to the above-described embodiment, and various modifications and applications are possible.

For example, when the bus width of the data bus of the flash memory 2 is 16 bits, it can be similarly implemented by changing the number of bits of the first register 40 and the second register 41 in the buffer register 32 to 16 bits. it can. In this case, 16-bit input data is sequentially held in the first register 40 and the second register 41, and the held data is cut out in units of a predetermined symbol length (10 bits) and supplied to the error correction code / decoder 33. Is done.
FIG. 9A shows 512-byte data output from the buffer 9 to the internal bus 14 in units of 16 bits. The data stored in the buffer 9 is supplied to the flash memory 2 via the internal bus 14 in units of 16 bits from the top to the data 255 in the order of Data0, Data1, and Data2, and the user area 25 of the flash memory 2 as user data. Is written to. These 16-bit data are counted from the least significant bit to the 15th bit in the order of the 0th bit and the 1st bit. Further, FIG. 9A has a description of Data0 [10:15], which means a bit string (6 bits) from the 10th bit to the 15th bit of Data0.
The data output from the buffer 9 in units of 16 bits is also supplied to the buffer register 32 via the internal bus 14.
The buffer register 32 temporarily holds the data supplied from the buffer 9 and outputs the data to the error correction code / decoder 33 by a predetermined symbol length (10 bits). In addition, 512 bytes of data 0 to 255 are output to the error correction code / decoder 33 by a predetermined symbol length (10 bits), and finally, data that does not satisfy the predetermined symbol length (10 bits) remains. In this case, data of a predetermined symbol length (10 bits) with dummy data added is generated and output to the error correction code / decoder 33.
FIG. 9B shows data of a predetermined symbol length (10 bits) output from the buffer register 32 to the error correction code / decoder 33. For example, one symbol data is generated by Data0 [9: 0], and one symbol data is generated by Data0 [15:10] and Data1 [3: 0]. In this way, 512 bytes of data 0 to 255 are concatenated, cut out in units of a predetermined symbol length (10 bits), and finally 4 bits of dummy data are added to generate 410 symbols of symbol data. .

  The symbol length of the Reed-Solomon code can be set as appropriate according to the unit (capacity of user data) for generating the error-correcting code within the range where the generator polynomial in the Reed-Solomon code theory holds. For example, when an error correction code is generated in units of 2048 bytes (4 sectors), the symbol length of the Reed-Solomon code may be increased accordingly.

  Also, in order to shorten the symbol length (in order to reduce the number of bits of one symbol), 512-byte (one sector) user data is divided into a plurality of pieces, and error correction codes are generated in divided user data units. You may do it.

1 is a block diagram illustrating an example of a flash memory system. It is a figure which shows an example of the structure of the address space of flash memory. It is a figure which shows the flow of data at the time of writing data from a buffer to flash memory. It is a figure which shows the data flow at the time of writing data from a flash memory to a buffer. It is a block diagram which shows an example of a buffer register. (A) is a figure which shows the data state of the buffer when data of 512 bytes is stored in the flash memory whose bus width of a data bus is 8 bits. (B) is a diagram showing in what format the data shown in (a) is output to the error correction code / decoder. It is a figure which shows the process which supplies data to an error correction code | symbol decoder from a buffer register. It is a figure which shows the process which supplies data to an error correction code | symbol decoder from a buffer register. It is a figure which shows the process which supplies data to an error correction code | symbol decoder from a buffer register. It is a figure which shows the process which supplies data to an error correction code | symbol decoder from a buffer register. It is a figure which shows the process which supplies data to an error correction code | symbol decoder from a buffer register. (A) is a figure which shows the data state of the buffer when data of 512 bytes is stored in the flash memory whose bus width of a data bus is 16 bits. (B) is a diagram showing in what format the data shown in (a) is output to the error correction code / decoder.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 25 User area 26 Redundant area 30 ECC register 32 Buffer register 33 Error correction code / decoder 34 Mask circuit 40 First register 41 Second register

Claims (5)

A memory controller that controls access to a flash memory in response to a command from a host system,
Write data supply means for supplying user data to be written to the user area of the flash memory;
Symbol data supply means for receiving the user data, sequentially connecting the user data until a predetermined number of bytes is reached, and sequentially cutting out and outputting the connected data in units of a predetermined symbol length;
Dummy data adding means for adding predetermined dummy data to the final data when the data length of the final data extracted from the user data of the predetermined number of bytes is less than the predetermined symbol length;
An error correction code generation unit configured to generate an error correction code composed of a Reed-Solomon code for the user data of the predetermined number of bytes based on data output in symbol length units from the symbol data supply unit;
Conversion means for performing conversion processing on the error correction code so that the error correction code matches the erased state of the flash memory when the user data of the predetermined number of bytes matches the erased state of the flash memory When,
Redundant data writing means for writing the error correction code subjected to the conversion process into a redundant area corresponding to a user area in which the user data of the predetermined number of bytes is written;
A memory controller comprising: User data reading means for reading user data written in the user area;
Redundant data reading means for reading the error correction code subjected to the conversion process written in the redundant area;
Inverse conversion means for returning the error correction code subjected to the conversion processing read by the redundant data reading means to the error correction code before the conversion processing;
Based on the error correction code before the conversion process supplied from the inverse conversion means, an error correction code generation means for correcting an error in the symbol length unit supplied via the symbol data supply means;
The memory controller according to claim 1, further comprising:   3. The memory controller according to claim 1, wherein the predetermined number of bytes is 512 bytes.   The symbol data supply means sequentially connects the user data in units of the same number of bits as the bus width of the flash memory, and cuts out the connected data in units of a predetermined symbol length. The memory controller according to any one of claims. A memory controller according to any one of claims 1 to 4,
Flash memory,
A flash memory system comprising:

Images