JP2007179296A - Timing analysis method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing analysis method for calculating PLL jitter tolerance or clock duty tolerance in a short time. <P>SOLUTION: In timing analysis of a flip-flop circuit, a path to a falling clock drive flip-flop from a rising drive flip-flop and a path to the rising clock drive flip-flop from the falling clock drive flip-flop are extracted, operation margins of the paths are analyzed, and the duty tolerance of a drive clock is calculated by a worst margin value of an analysis result. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a timing analysis method for a flip-flop circuit using a flip-flop or a circuit using a PLL and a flip-flop (hereinafter abbreviated as FF). More specifically, the present invention relates to a timing analysis method such as LSI and FPGA (registered trademark of Xilinx).

  In an LSI or FPGA logic circuit, it is necessary to perform a timing analysis by using a tool to determine whether or not a setup (hold) / hold (hold) timing regulation between FFs driven by the same clock is satisfied. Although the driving clock is the same, timing analysis must be performed in the same manner when one FF is driven by an inverted clock.

  From the viewpoint of the input clock, the data is latched by the rising clock when it reaches the FF without being logically inverted, and by the falling clock when it reaches the FF after being logically inverted. Become. When using a circuit between the FF driven by the rising clock and the FF driven by the falling clock, or vice versa, the clock duty ratio is related to the timing specification. Therefore, it is necessary to calculate the input clock duty tolerance for the LSI / FPGA input clock duty specification and external connection component selection.

  FIG. 7 is a diagram showing a rising clock drive FF circuit. DATA1 is input to the data input terminal DT of FF1, and clock (CLOCK) 1 is input to the clock input terminal CLK. The Q output of FF1 is input to the data input terminal DT of FF2, and the CLOCK1 is input to the clock input terminal CLK of FF2.

  FIG. 8 shows a falling clock drive FF circuit. DATA2 is input to the data input terminal DT of FF3, and CLOCK2 is inverted by the inverter INV1 and input to the clock input terminal CLK. The Q output of FF3 is input to the data input terminal DT of FF4, and the output of INV1 is input to the clock input terminal CLK of FF4.

  FIG. 9 is a diagram showing a rising → falling clock driving FF circuit. DATA3 is input to the data input terminal DT of FF5, and CLOCK3 is input to the clock input terminal CLK. The Q output of FF5 enters the data input terminal DT of FF6, and the clock input terminal CLK of FF6 contains a clock obtained by inverting the CLOCK3 by the inverter INV2. In this circuit, FF5 is latched at the rising edge of CLOCK3, while FF6 is latched at the falling edge of CLOCK3.

  FIG. 10 is a diagram showing a falling-to-rise clock driving FF circuit. DATA4 is input to the data input terminal DT of the FF7, and the clock input terminal CLK is input by inverting the CLOCK4 by the inverter INV3. The Q output of FF7 is input to the data input terminal DT of FF8, and CLOCK4 is input to the clock input terminal CLK of FF8. In this circuit, FF7 is latched at the falling edge of CLOCK4, while FF8 is latched at the rising edge of CLOCK4.

  FIG. 11 is an operation time chart when the clock duty is 25% in FIG. (A) is CLOCK1, (b) is the waveform of the clock entering the clock input terminal CLK of FF1, (c) is the waveform of the data entering the data input terminal DT of FF1, and (d) is the Q output waveform of FF1. (E) shows the waveform of the clock entering the clock input terminal CLK of FF2, (f) shows the waveform of the data entering the data input terminal DT of FF2, and (g) shows the Q output waveform of FF2. . The time from when CLOCK1 of FF1 rises until the input data appears at the Q output is the cell delay Δt1 of FF1. The time until the Q output of FF1 enters the data input terminal DT of FF2 is a delay Δt2. Δt3 is the cell delay time of FF2. The minimum period during which the data at the data input terminal DT of FF2 must be determined is the setup time, and the time that the data must be held at the data input terminal of FF2 after the clock of FF2 rises is the hold time It is.

  FIG. 12 is an operation time chart when the clock duty is 50% in FIG. Signals (a) to (g) are the same as those in FIG. The time chart is not different from the case of FIG. FIG. 13 is an operation time chart when the clock duty is 75% in FIG. Signals (a) to (g) are the same as those in FIG. The time chart is not different from the case of FIG. In the case of the circuit of FIG. 7, it can be seen that the FF2 data capture margin Setup / Hold does not change depending on the clock duty ratio.

  FIG. 14 is an operation time chart when the clock duty is 25% in FIG. (A) is CLOCK2, (b) is the waveform of the clock input terminal CLK of FF3, (c) is the waveform of the data input terminal DT of FF3, (d) is the Q output waveform of FF3, (e) is The waveform of the clock input terminal CLK of FF4, (f) shows the waveform of the data input terminal DT of FF4, and (g) shows the Q output waveform of FF4. CLOCK2 is inverted by an inverter INV1 to drive FF3 and FF4. The time from when CLOCK2 of FF3 rises until the input data appears at the Q output is the cell delay Δt4 of FF3. The time until the Q output of FF3 enters the data input terminal DT of FF4 is a delay Δt5. Δt6 is the cell delay time of FF4.

  The circuit shown in FIG. 8 is the same as the circuit shown in FIG. 7 except that FF3 and FF4 are driven by a pulse obtained by inverting CLOCK2 by an inverter INV1. In FIG. 14, it can be seen that the setup time is sufficiently secured.

  FIG. 15 is an operation time chart when the clock duty is 50% in FIG. The waveforms from (a) to (g) are the same as in FIG. The time chart is not different from the case of FIG. FIG. 16 is an operation time chart when the clock duty is 75% in FIG. The waveforms from (a) to (g) are the same as in FIG. In the case of the circuit shown in FIG. 8, it can be seen that the FF4 data capture margin Setup / Hold does not change depending on the clock duty ratio.

  FIG. 17 is an operation time chart when the clock duty is 25% in FIG. (A) is CLOCK3, (b) is the waveform of the clock input terminal CLK of FF5, (c) is the waveform of the data input terminal DT of FF5, (d) is the Q output waveform of FF5, (e) is The waveform of the clock input terminal CLK of FF6, (f) shows the waveform of the data input terminal DT of FF6, and (g) shows the Q output waveform of FF6. CLOCK3 drives FF5, and the inversion pulse of CLOCK3 drives FF6. Δt7 represents the cell delay time of FF5, Δt8 represents the line delay time from the Q output of FF5 to the data input terminal DT of FF6, and Δt9 represents the cell delay time of FF6.

  In the case of FIG. 9, since FF5 and FF6 are driven by clocks having different phases, the operation is slightly more complicated than the circuits shown in FIGS. DATA3 is latched at the rising edge of CLOCK3 and appears as a Q output as shown in (d). This Q output is input to the data input terminal DT of FF6, and this data is latched by the inverted signal of CLOCK3. Therefore, it can be seen that the setup time that must be established before the Q output of FF5 is latched by the inverted signal of CLOCK3 is extremely short and strict as shown in FIG.

  FIG. 18 is an operation time chart when the clock duty is 50% in FIG. The waveforms from (a) to (g) are the same as those in FIG. Since the duty of CLOCK3 is 50%, the setup time is long as shown in (e). FIG. 19 is an operation time chart when the clock duty is 75% in FIG. The waveforms from (a) to (g) are the same as those in FIG. As a result of the duty of CLOCK3 becoming 75%, the setup time has a margin as shown in (e).

  FIG. 20 is an operation time chart when the clock duty is 25% in FIG. (A) is CLOCK4, (b) is the waveform of the clock input terminal CLK of FF7, (c) is the waveform of the data input terminal DT of FF7, (d) is the Q output waveform of FF7, (e) is The waveform of the clock input terminal CLK of FF8, (f) shows the waveform of the data input terminal DT of FF8, and (g) shows the Q output waveform of FF8. CLOCK4 drives FF8, and the inversion pulse of CLOCK4 drives FF7. Δt10 represents the cell delay time of FF7, Δt11 represents the line delay time from the Q output of FF7 to the data input terminal DT of FF8, and Δt12 represents the cell delay time of FF8.

  In the case of FIG. 10, since FF7 and FF8 are driven by clocks having different phases, the operation is slightly more complicated than the circuits shown in FIGS. DATA4 is latched at the falling edge after inversion of CLOCK4, and appears as a Q output as shown in (d). This Q output is input to the data input terminal DT of FF8, and this data is latched by CLOCK4. Accordingly, the setup time and hold time that must be established before the Q output of the FF 7 is latched by CLOCK 4 are as shown in (f). Setup time is something you can afford.

  FIG. 21 is an operation time chart when the clock duty is 50% in FIG. The waveforms from (a) to (g) are the same as those in FIG. The setup time is shorter than in the case of FIG. FIG. 22 is an operation time chart when the clock duty is 75% in FIG. The waveforms from (a) to (g) are the same as those in FIG. As a result of the duty being 75%, it can be seen that the setup time is very short and strict as shown in FIG.

  There is no conventional technique to calculate duty tolerance or jitter tolerance, and the clock duty and jitter components are changed according to the definition of the input clock period and pulse width, and the timing analysis of all paths of the clock is performed. Was judging.

  As this type of conventional technology, a duty verification unit is provided to provide information related to the duty of clock data on an electronic circuit on which logic / circuit design has been performed, such as probe data obtained from the execution result of a logic simulation. A technique for extracting and verifying whether the duty of the clock data satisfies the specification based on the information is known (see, for example, Patent Document 1). When a circuit having a PLL block is subjected to timing verification by an event-driven logic simulation method, a jitter value specific to the PLL block included in the target circuit is described in a delay library, and the result obtained by timing verification There is known a technique that includes a step of adding or subtracting a jitter value to and performing timing verification in consideration of the jitter value depending on whether or not a target circuit setup / hold is satisfied (for example, see Patent Document 2).

In addition, the disclosed timing verification method includes a clock path formed between a clock supply terminal that supplies a first clock specified as a verification target and a clock input terminal of an FF that is set as an end point as the verification target. When a PLL circuit is present above, a technique for obtaining a second end point clock delay value based on the first end point clock delay value DCE1, the end point loop delay value, the jitter and the steady phase error in the PLL is known. (For example, refer to Patent Document 3).
JP-A-9-17987 (paragraphs 0015 to 0021, FIG. 1) JP 2000-357179 A (paragraphs 0026 to 0034, FIG. 2, FIG. 4, FIG. 5) JP 2001-117906 A (paragraphs 0031 to 0063, FIGS. 1 to 3)

  Since it is necessary to define the period and pulse width of the input clock before performing timing analysis, it is necessary to redefine the input clock and perform timing analysis multiple times before the duty tolerance or jitter tolerance is determined. There is. Here, jitter refers to the degree of fluctuation of the clock frequency. The following is an example of this work.

[In case of duty resistance]
First time: Set H pulse width to 30%, L pulse width to 70%, timing analysis → Timing specification NG
Second time: Set H pulse width to 40%, L pulse width to 60%, timing analysis → OK timing specification
3rd: Set H pulse width to 50%, L pulse width to 50%, timing analysis → Timing specification OK
4th time: Set H pulse width to 60%, L pulse width to 40%, timing analysis → Timing specification OK
5th: Timing analysis with H pulse width set to 70% and L pulse width set to 30% → Timing specification OK
6th: H pulse width is set to 80%, L pulse width is set to 20%, timing analysis → Timing specification NG
As described above, it has been confirmed that the H pulse width can be operated within the range of 40% to 70% after six pulse width redefinition operations. In addition, multiple redefinitions and execution of timing analysis are required. In this method, since the timing analysis of all paths is executed every time the input clock is redefined, the analysis takes time.

[In the case of jitter tolerance]
1st: Set PLL output clock jitter to ± 200 ps and analyze timing → OK timing specification
Second time: PLL output clock jitter is set to ± 300 ps, timing analysis → timing specification OK
3rd: PLL output clock jitter is set to ± 400ps and timing analysis → Timing specification NG
As described above, in the third jitter redefinition operation, it can be confirmed that the PLL output clock jitter can be operated within the range of ± 300 ps. Definition and timing analysis execution are required.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a timing analysis method capable of calculating a clock duty tolerance or a PLL jitter tolerance in a short time.

(1) According to the first aspect of the present invention, the path from the rising drive flip-flop to the falling clock drive flip-flop and the path from the falling clock drive flip-flop to the rising clock drive flip-flop at the time of timing analysis of the flip-flop circuit And the operation margin of these paths is analyzed, and the duty tolerance of the drive clock is calculated from the worst margin value of the analysis result.
(2) The invention according to claim 2 extracts the path of the flip-flop driven by the corresponding PLL output clock at the time of timing analysis of the flip-flop circuit including the PLL, analyzes the operation margin of the path, The jitter tolerance of the PLL is calculated from the worst margin value of the setup timing.

(1) According to the first aspect of the present invention, the clock duty tolerance can be calculated in a short time.
(2) According to the invention of claim 2, the PLL jitter tolerance can be calculated in a short time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit block diagram of an LSI / FPGA. CLOCK5 is a clock input to the LSI / FPGA, MCK is a clock input to the reference of the internal PLL, BUFF1 is a through buffer cell, INV4 and INV5 are inverter cells, and FF9 to FF24 are FF cells.

  When the timing analysis of the input clock CLOCK5 is performed, the FF9 Q → FF10 DT, FF11 Q → FF12 DT, FF13 Q → FF14 DT, FF15 Q → FF16 DT data path are targeted. . From the viewpoint of duty tolerance, since the DT of FF9 between the rising clock drive FFs and the DT of FF11 between the falling clock drive FFs and the DT of FF11 between the falling clock drive FFs are driven at the same edge, the clock duty ratio The margin does not change. When calculating the duty tolerance, it is only necessary to analyze only the timing of DT of Q → FF14 of FF13 and Q of FF15 → DT of FF16.

  Also, when performing timing analysis of the PLL output clock, the data path of FF17 Q → FF18 DT, FF19 Q → FF12 DT, FF21 Q → FF22 DT, FF23 Q → FF24 DT become. From the standpoint of jitter tolerance, it is only necessary to analyze the setup timing of the data path of DT of Q → FF18 of FF17 and Q → FF20 of FF19 and DT of FF20.

[When calculating duty tolerance]
An embodiment of calculating the clock duty of CLOCK 5 will be described with reference to FIG. FIG. 2 is a flowchart showing the duty calculation process. The embodiment of the present invention will be described below with reference to this flowchart.

1. Definition of clock Define the clock cycle and initial pulse width (duty) for which the duty tolerance is to be calculated. Here, CLOCK5 is defined as a cycle of 10 ns (100 MHz), and an initial pulse width (duty) is defined as 5 ns (50%).

2. Extraction of target paths Here, paths are extracted under the following conditions in order to analyze timing only for paths required for duty tolerance calculation.
1) All paths of rising clock drive FF → falling clock driving FF 2) All paths of falling clock driving FF → rising clock driving FF In the case of FIG. 1, 1) is a path from FF13 to FF14. ) Is a path from FF15 to FF16.

3. Timing analysis Performs setup / hold timing analysis for the extracted path.
1) FF13-FF14
Setup margin 2ns (FF14 setup time = 1ns)
Hold margin 6.5ns (FF14 hold time = 0.5ns)
FIG. 3 is a diagram showing an example of the setup margin of FF13-FF14. (A) shows the waveform of CLOCK5, (b) shows the waveform of the clock input terminal CLK of FF13, (c) shows the Q output waveform of FF13, (d) shows the waveform of clock input terminal CLK of FF14, (e ) Shows the waveform of the data input terminal DT of the FF 14 respectively.

According to FIG. 3, the data setup time of the FF 14 (from the data change point to the rising edge of the clock) is 3 ns. Here, if the input setup rule of the FF 14 (setup time required for the FF) is 1 ns, the margin is 3 ns-1 ns = 2 ns.
2) FF15-FF16
Setup margin 3ns (FF16 setup time = 1ns)
Hold margin 5.5ns (FF16 hold time = 0.5ns)
FIG. 4 is a diagram showing an example of the FF 15-16 hold margin. (A) shows the waveform of CLOCK5, (b) shows the waveform of the clock input terminal CLK of FF15, (c) shows the Q output waveform of FF15, (d) shows the waveform of clock input terminal CLK of FF16, (e) Indicates the waveform of the data input terminal DT of the FF 16.

  According to FIG. 4, the data hold time of the FF 16 (from the rising edge of the clock to the data change point) is 6 ns. Here, if the input hold regulation of FF 16 (hold time required for FF) is 0.5 ns, the margin is 6 ns−0.5 ns = 5.5 ns.

4). Worst path extraction From the analysis results, the worst path is determined for each of the following classifications.
1) (a) Setup worst path of rising clock drive FF → falling drive FF: FF13-FF14 (setup margin 2 ns)
(A) Extract hold worst path: FF13-FF14 (hold margin 6.5 ns)
2) Falling drive FF → Rising clock drive FF
(A) Extract the setup worst path: FF15-FF16 (setup margin 3 ns)
(A) Extract hold worst path: FF15-FF16 (hold margin 5.5 ns)

5. Calculate minus duty duty tolerance Calculate the minus value of duty tolerance from the analysis results.
1) The setup worst margin of the rising clock drive FF → the falling clock drive FF is converted into a duty.
(A) Setup worst path margin = 2 ns (FF13-FF14)
(A) Since the setup side has a margin of 2 ns with a duty of 50% (H = 5 ns, L = 5 ns), the falling edge of CLOCK 5 can be moved to the negative side by 2 ns. FIG. 5 is an explanatory diagram for converting the setup margin into a duty. When CLOCK5 has a duty of 50%, it is moved to the minus side by 2 ns. As a result, the duty is 30%. Moreover, if it is moved to the 3 ns plus side, the duty is 80%.
(C) A duty of 30% (H = 3 ns, L = 7 ns) is obtained (represented as = D (−)).
2) Confirm that D (−) satisfies the hold worst of the falling clock drive FF → the rising clock drive FF.
(A) Hold worst path margin = 5.5 ns (FF15-FF16)
(A) Although the hold margin is reduced to 5.5 ns-2 ns = 3.5 ns by moving the falling edge of CLOCK 5 to the minus side by 2 ns, there is no problem.
D (-) = 30%

6). Positive duty tolerance calculation Calculate the plus value of duty tolerance from the analysis results.
1) The setup worst margin of the falling clock driving FF → the rising clock driving FF is converted into a duty. This is D (+).
(A) Setup worst path margin = 3 ns (FF15-FF16)
(A) Since the setup side has a margin of 2 ns with a duty of 50% (H = 5 ns, L = 5 ns), the falling edge of CLOCK 5 can be moved to the 3 ns plus side.
(C) Duty 80% (H = 8 ns, L = 2 ns is obtained (assuming that D = +))
2) Confirm that D (+) satisfies the hold worst of the rising clock drive FF → the falling clock drive FF.
(A) Hold worst path margin = 6.5 ns (FF13-FF14)
(A) Although the hold margin is reduced to 6.5 ns-3 ns = 3.5 ns by moving the falling edge of CLOCK 5 to the minus side by 3 ns, there is no problem.
D (+) = 80%

7). Result output Displays the calculated duty. The duty resistance is expressed as follows, for example.
Duty resistance: 30% -80%
Thus, according to the present invention, the clock duty tolerance can be calculated in a short time.

[When calculating jitter tolerance]
An embodiment of calculating MCK PLL clock jitter will be described with reference to FIG. FIG. 6 is a flowchart showing the jitter calculation process. The embodiment of the present invention will be described below with reference to this flowchart.

1. Definition of clock Define the PLL clock whose jitter tolerance is to be calculated. Define the clock period, initial pulse width (duty), and initial jitter. Here, MCK has a period of 10 ns (100 MHz), a pulse width of 5 ns, and an initial jitter of 200 ps. Here, ps is an abbreviation for pico seconds.

2. Extraction of target paths In order to analyze timing only for paths required for jitter tolerance calculation, paths are extracted under the following conditions.
1) All paths of rising clock driving FF → rising clock driving FF 2) All paths of falling clock driving FF → falling clock driving FF In FIG. 1, 1) is a path from FF17 to FF18, and 2) is from FF19. It becomes the path of FF20.

3. Timing analysis Performs setup timing analysis on the extracted path.
1) FF17-FF18
Setup margin 200ps (FF18 setup time = 1ns)
2) FF19-FF20
Setup margin 300ps (FF20 setup time = 1ns)
4). Worst path extraction Determines the setup worst path from the analysis result.
1) Extract the setup worst paths of all paths of rising clock drive FF → rising clock drive FF and falling clock drive FF → falling clock drive FF.

Setup worst path extraction: FF17-FF18 (setup margin 200 ps)
5. Jitter tolerance calculation Jitter tolerance is calculated from the analysis results.

The setup worst margin is converted to jitter. Since the setup worst margin is 200 ps, initial jitter (200 ps) + ΔJ (200 ps) = ± J (400 ps)
6). Result output Displays the calculated jitter. The jitter tolerance is ± 400 ps.

As described above, according to the present invention, the PLL jitter tolerance can be calculated in a short time.
As described above, according to the present invention, the duty tolerance calculation function and the jitter tolerance calculation function are mounted, so that it is not necessary to perform the timing analysis a plurality of times as in the current tool.

In addition, since only timing analysis necessary for proof stress calculation needs to be performed, the calculation time is short, and when applied to a large-scale circuit or the like that requires a long time for timing analysis, the time reduction effect is great.
Furthermore, since the worst path can be confirmed, it is possible to easily determine a path that needs to be adjusted for improving the yield strength. In addition, by using the information on the path after the worst path, it is possible to provide prediction information for improving the yield strength with respect to the worst path adjustment value.

It is a circuit block diagram of LSI / FPGA. It is a flowchart which shows a duty calculation process. It is a figure which shows the example of FF13-14 setup margin. It is a figure which shows the example of FF15-16 hold margin. It is explanatory drawing which converts a setup margin into a duty. It is a flowchart which shows a jitter calculation process. It is a figure which shows a rising clock drive FF circuit. It is a figure which shows the falling clock drive FF circuit. It is a figure which shows a rising-> falling clock drive FF circuit. It is a diagram showing a falling-to-rise clock drive FF circuit. 8 is an operation time chart when the clock duty is 25% in FIG. 7. 8 is an operation time chart when the clock duty is 50% in FIG. 7. FIG. 8 is an operation time chart when the clock duty is 75% in FIG. 7. FIG. FIG. 9 is an operation time chart when the clock duty is 25% in FIG. 8. FIG. 9 is an operation time chart when the clock duty is 50% in FIG. 8. 9 is an operation time chart when the clock duty is 75% in FIG. 8. 10 is an operation time chart when the block duty of FIG. 9 is 25%. 10 is an operation time chart when the clock duty is 50% in FIG. 9. 10 is an operation time chart when the clock duty is 75% in FIG. 9. 11 is an operation time chart when the clock duty is 25% in FIG. 10. 11 is an operation time chart when the clock duty is 50% in FIG. 10. 11 is an operation time chart when the clock duty is 75% in FIG. 10.

Explanation of symbols

FF9 to FF24 Flip-flop BUFF1 Buffer INV4 Inverter INV5 Inverter

Claims (2)

  During timing analysis of the flip-flop circuit, the path from the rising drive flip-flop to the falling clock drive flip-flop and the path from the falling clock drive flip-flop to the rising clock drive flip-flop are extracted and the operating margin of these paths is analyzed And calculating the duty tolerance of the drive clock from the worst margin value of the analysis result.   At the time of timing analysis of the flip-flop circuit including the PLL, the path of the flip-flop driven by the corresponding PLL output clock is extracted, the operation margin of the path is analyzed, and the PLL jitter is calculated from the worst margin value of the setup timing of the analysis result. A timing analysis method characterized by calculating a yield strength.

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