JP2007179011A - Display device and electronic device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the power consumption of a display device. <P>SOLUTION: The display device includes a wire to which a video signal is input, a first capacitor element and a second capacitor element which are connected to the wire in parallel, and a pixel. Between the first capacitor element and the wire, a first switch is provided so as to control conduction and nonconduction between the first capacitor element and the wire. Between the second capacitor element and the wire, a second switch is provided so as to control the conduction and nonconduction between the second capacitor element and the wire. The pixel and the wire are arranged, such that the pixel and the wire can be connected to each other, and a video signal can be input to the pixel. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device. In particular, the present invention relates to a liquid crystal display device, and particularly to a technique for reducing power consumption.

Examples of the display device include an EL display device, a plasma display, and a liquid crystal display device.
For example, in a liquid crystal display device which is one of them, the counter electrode potential (common potential) is set at regular intervals to prevent deterioration of the liquid crystal material, to eliminate display unevenness such as flicker, and to maintain display quality. ) With the polarity of the voltage applied to the pixel electrode reversed. Such a driving method is called inversion driving.

  Examples of inversion driving include frame inversion driving, source line inversion driving, gate line inversion driving, dot inversion driving, common inversion driving, and the like (for example, see Patent Document 1).

  The frame inversion driving is a driving method in which the polarity of the voltage applied to the pixel electrode is inverted with respect to the common potential for each frame period. A display pattern diagram of frame inversion driving is shown in FIG. The display pattern diagram shown in FIG. 8 shows an example of a model screen of display pixels 3 rows × 4 columns for the sake of simplicity. In the frame inversion driving, the flicker is easily visually recognized because the polarity inversion period is long. Therefore, in order to reduce flicker, a method of combining source line inversion driving, gate line inversion driving, dot inversion driving and the like in addition to frame inversion driving is generally employed.

  The gate line inversion driving is a driving method for inverting the polarity of the voltage applied to each pixel for each adjacent gate line. A display pattern diagram of gate line inversion driving is shown in FIG. In addition, the display pattern diagram shown in FIG. 9 shows a case of a model screen of display pixels 3 rows × 4 columns as an example for simplification.

  Source line inversion driving is a driving method in which the polarity of a voltage applied to each pixel is inverted for each adjacent source line. A display pattern diagram of source line inversion driving is shown in FIG. Note that the display pattern diagram shown in FIG. 10 shows an example of a model screen of display pixels 3 rows × 4 columns for the sake of simplicity.

  The dot inversion driving is a driving method that inverts the polarity of a voltage applied between adjacent pixels, and is a driving method that combines source line inversion driving and gate line inversion driving. FIG. 11 shows a display pattern diagram of dot inversion driving. The display pattern diagram shown in FIG. 11 shows an example of a model screen of display pixels 3 rows × 4 columns for the sake of simplicity.

  By the way, when the above-described frame inversion driving, source line inversion driving, gate line inversion driving, dot inversion driving, or the like is adopted, the fluctuation width of the potential of the video signal written to the source signal line is not inversion driving (common). The polarity of the voltage applied to the pixel electrode with respect to the potential is unipolar, that is, twice as compared with the case of driving without changing the polarity. Therefore, it is necessary to increase the withstand voltage of the drive circuit as compared with the case of driving without inversion driving (when the polarity of the voltage applied to the pixel electrode with respect to the common potential is driven with one polarity). At the same time, power consumption increases. Therefore, in the case of frame inversion driving or gate line inversion driving, common inversion driving may be further employed.

  The common inversion driving is a driving method in which the polarity of the common potential is inverted in synchronization with the timing of the polarity inversion of the potential of the pixel electrode. By performing the common inversion driving, the fluctuation of the potential of the video signal written to the source signal line The width can be halved.

Further, not only in a liquid crystal display device but also in an EL display device, inversion driving may be performed for the purpose of extending the life of an EL element (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 11-231822 JP 2001-222255 A

  As described above, when frame inversion drive, source line inversion drive, gate line inversion drive, dot inversion drive, etc. are adopted, the amplitude of the potential of the video signal written to the source signal line is, in other words, when driving with one polarity, When driving without changing the polarity, twice as much is required. Therefore, as compared with the case of driving with unipolarity, it is necessary to increase the breakdown voltage of the drive circuit, and at the same time, power consumption increases. In order to solve problems such as high power consumption, common inversion drive is adopted for frame inversion drive and gate line inversion drive. The power consumption is increasing.

  As described above, in the case of performing inversion driving, the power consumption becomes larger than in the case of driving with one polarity.

  Therefore, an object of the present invention is to provide a display device with reduced power consumption and an electronic device using the display device.

  The present invention is a display device that performs inversion driving, and a capacitor element that accumulates positive charges and a capacitor element that accumulates negative charges are connected in parallel to a wiring (source signal line) for supplying a video signal. The gist is to reduce power consumption by charging the wiring capacitance by alternately discharging positive or negative charges accumulated in each capacitor element when performing inversion driving.

  One embodiment of the present invention is a display device including a wiring (source signal line) to which a video signal is input, a first capacitor element connected in parallel to the wiring, a second capacitor element, and a pixel. Between the first capacitor element and the wiring, a first switch for controlling the conduction state and the non-conduction state of the two is provided. A second switch is provided between the second capacitor element and the wiring to control the conductive state and the non-conductive state of the two. The pixel and the wiring are arranged so as to be connectable, and a video signal is input to the pixel.

  The first capacitor element has a function of storing positive charges, and the second capacitor element has a function of storing negative charges.

  The display device of the present invention is preferably applied to a liquid crystal display device.

  The display device of the present invention includes the first capacitor element, the second capacitor element, the first switch, and the second switch, so that when the inversion drive is performed, positive charge is applied to the first capacitor element. Power consumption can be reduced by storing, storing negative charge in the second capacitor element, and effectively using the stored charge when the positive charge and the negative charge are inverted.

  Embodiments and examples of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

An embodiment of the present invention will be described with reference to FIG.
In the display device of the present invention, one terminal of the first switch 106 and one terminal of the second switch 108 are electrically connected to the source signal line 101. The first electrode of the first capacitor 107 is electrically connected to the other terminal of the first switch 106, and the second capacitor 109 is connected to the other terminal of the second switch 108. The first electrodes are electrically connected.

  A plurality of pixels 102 to 105 are electrically connected to the source signal line 101, and a video signal output from the source signal line driver circuit 100 is written to the plurality of pixels 102 to 105. Note that although the case where the number of the plurality of pixels electrically connected to the source signal line 101 is four is illustrated here, the number of the pixels electrically connected to the source signal line is not particularly limited to four. . In the case of an n-row × m-column display device, the number of pixels electrically connected to one source signal line is n. Note that n and m are natural numbers of 1 or more.

  Note that in FIG. 1, in a region 111 between the source signal line driver circuit 100 and the pixel portion 110, the first capacitor element 107 is electrically connected to the source signal line 101 through the first switch 106. Although the case where the second capacitor 109 is electrically connected to the source signal line 101 through the second switch 108 is shown, the present invention is not limited to this case.

  For example, as shown in FIG. 2, in a region near the end of the source signal line 101 opposite to the source signal line driver circuit 100 (region facing the source signal line driver circuit 100 via the pixel portion 110) 112. The first capacitor element 107 is electrically connected to the source signal line 101 via the first switch 106, and the second capacitor element 109 is electrically connected to the source signal line 101 via the second switch 108. It may be connected.

  In addition, as illustrated in FIG. 3, in the region 111 between the source signal line driver circuit 100 and the pixel portion 110, the first capacitor element 107 is electrically connected to the source signal line 101 via the first switch 106. In a region 112 (region facing the source signal line driver circuit 100 through the pixel portion 110) 112 that is connected and near the end of the source signal line 101 opposite to the source signal line driver circuit 100, the second capacitor element 109 may be electrically connected to the source signal line 101 via the second switch 108.

  As shown in FIG. 4, a first capacitor transistor 117 and a second capacitor transistor 119 may be provided instead of the first capacitor element 107 and the second capacitor element 109. The source electrode and the drain electrode of the first capacitor transistor 117 and the second capacitor transistor 119 are electrically connected to each other, and the first capacitor transistor 117 and the second capacitor transistor 119 are turned on. A capacitor is formed between the gate electrode and the channel formation region. The cross-sectional structure of such a capacitor transistor is not different from that of a normal thin film transistor as shown in FIG. 12A, the capacitor transistor includes a gate electrode 604, a gate insulating film 603, and a semiconductor film 601 having a channel formation region.

  Note that a capacitor using the gate insulating film 603 as described above is affected by the fact that it does not function as a capacitor depending on the change in threshold voltage of the transistor, and thus the gate electrode of the semiconductor film 601 An impurity element may be added to the region 602 overlapping with the region 604 (see FIG. 12B). In this way, a capacitor is formed regardless of the threshold voltage of the transistor. An equivalent circuit diagram in this case can be expressed as shown in FIG.

  FIG. 4 shows the case where both the first capacitor transistor 117 and the second capacitor transistor 119 are N-type thin film transistors. In this case, since the first capacitor transistor 117 has a function of storing positive charges, the gate electrode of the first capacitor transistor 117 is electrically connected to the source signal line 101 through the first switch 106. To be. Since the second capacitor transistor 119 has a function of storing negative charge, the source electrode and the drain electrode of the second capacitor transistor 119 are electrically connected to the source signal line 101 through the second switch 108. To be connected to.

  FIG. 5 shows the case where the first capacitor transistor and the second capacitor transistor are both P-type thin film transistors. In this case, the first capacitor transistor 127 has a source electrode and a drain electrode electrically connected to the source signal line 101 via the first switch 106, and the second capacitor transistor 129 has a gate electrode. Are electrically connected to the source signal line 101 through the second switch 108.

  Hereinafter, a driving method of the display device of the present embodiment will be described with reference to FIG. FIG. 6 is a diagram showing a change in potential in the source signal line 101. In the following, description will be made by dividing into six periods of period 1 to period 6.

First, in the period 1, the first switch 106 and the second switch 108 are turned off. Then, a video signal having a positive potential V ₁ is input from the source signal line driver circuit 100 to the source signal line 101. Since the first switch 106 and the second switch 108 are off, the potential of the source signal line 101 is V ₁ .

In the period 2, the first switch 106 is turned on. Then, when the first switch 106 is turned on, the first capacitor 107 is brought into conduction with the source signal line 101. Then, will gradually accumulate positive charges in the first capacitor element 107, the first capacitor 107 positive voltage V ₂ is stored, the potential of the source signal line 101 becomes V _3. Here, it is assumed that V ₁ = V ₂ + V ₃ .

In the period 3, the first switch 106 is turned off and the second switch 108 is turned on. Then, when the first switch 106 is turned off, the first capacitor 107 is brought out of electrical conduction with the source signal line 101, and the positive voltage V ₂ stored in the first capacitor 107 in the period 2 is stored. Remains in the state stored in the first capacitor element 107. In addition, when the second switch 108 is turned on, the second capacitor 109 is brought into conduction with the source signal line 101, and the negative voltage V ₆ previously stored in the second capacitor 109 is set. Corresponding charges are discharged to the source signal line 101. By the discharge of the electric charge, the potential of the source signal line 101 becomes V ₄ . In FIG. 6, but V ₄ indicates the case where become common potential need not necessarily V ₄ is equal to the common potential. In FIG. 6, since the case where | V ₃ | = | V ₆ | is described as an example, V ₄ is equal to the common potential. However, the present invention is not limited to this case.

In the period 4, the second switch 108 is turned off. Then, a video signal having a negative potential V ₅ is input to the source signal line 101 from the source signal line driver circuit 100. Then, the first switch 106 and second switch 108 because it has turned off, the potential of the source signal line 101 becomes _{V 5.}

In the period 5, the second switch 108 is turned on. Then, when the second switch 108 is turned on, the second capacitor 109 is brought into conduction with the source signal line 101. The negative charge in the second capacitor element 109 will be gradually accumulated, in the second capacitor 109 negative voltage V ₆ is stored, the potential of the source signal line 101 becomes V _7. Here, it is assumed that V ₅ = V ₆ + V ₇ .

In the period 6, the first switch 106 is turned on and the second switch 108 is turned off. Then, when the second switch 108 is turned off, the second capacitor 109 is brought out of electrical conduction with the source signal line 101, and the negative voltage V ₆ stored in the second capacitor 109 in the period 5 is stored. Remains in the state stored in the second capacitor 109. Further, when the first switch 106 is turned on, the first capacitor 107 is brought into conduction with the source signal line 101, and the positive voltage V ₂ stored in the first capacitor 107 in the period 2 is stored. Is discharged to the source signal line 101. The potential of the source signal line 101 becomes V ₈ due to the discharge of the charge corresponding to the positive voltage V ₂ stored in the first capacitor element 107. In FIG. 6, but V ₈ indicates the case where become common potential need not necessarily V ₈ is common potential. In FIG. 6, since the case where | V ₂ | = | V ₇ | is described as an example, V ₈ is equal to the common potential. However, the present invention is not limited to this case.

  The driving method in the period 1 to period 6 described above is a basic driving method of the display device of the present invention.

Since the display device of the present invention described above uses the negative voltage stored in the second capacitor 109 when rewriting from the positive potential V ₁ to the negative potential V ₅ , the source signal line driver circuit 100 is used. Thus, the amount of charge supplied to the source signal line 101 can be reduced. Therefore, power consumption can be reduced. This point will be described below in comparison with a conventional example.

FIG. 7 is a diagram showing a change in the potential of the source signal line in the conventional inversion driving. In the conventional inversion drive, when the inversion drive is performed from the positive potential V ₁ to the negative potential V ₅ , a charge corresponding to the voltage V ₅ -V ₁ is supplied from the source signal line drive circuit to the source signal line. There was a need to do.

On the other hand, the case where inversion driving is performed using the display device of the present invention will be described below. First, when the inversion drive is performed from the positive potential V ₁ to the negative potential V ₅ , the potential of the source signal line 101 is changed by storing the positive voltage V ₂ in the first capacitor element 107 in the period 2. V ₃ (= V ₁ −V ₂ ), and in period 3, by discharging the negative voltage V ₆ stored in the second capacitor 109 to the source signal line 101, the potential of the source signal line 101 becomes V ₄ (= V ₃ + V ₆ ). Therefore, the charge supplied from the source signal line driver circuit 100 to the source signal line 101 in the period 4 is an amount corresponding to a voltage of V ₅ -V ₄ .

Here, as can be seen from FIG. 6, since V ₁ > V ₄ , | V ₅ −V ₁ |> | V ₅ −V ₄ |, and the source signal line drive circuit 100 changes to the source signal line 101. It can be seen that the amount of charge supplied is smaller in the case of inversion driving using the display device of the present invention than in the conventional inversion driving. Therefore, when performing inversion driving from a positive potential V ₁ to a negative potential V _5, by performing inversion driving using the display device of the present invention, to reduce power consumption as compared with the conventional inversion driving be able to.

Conversely, when the negative potential V ₅ is rewritten to the positive potential V ₁ , the positive voltage stored in the first capacitor element 107 is used, so that the source signal line driver circuit 100 changes to the source signal line 101. Less charge is required. Therefore, power consumption can be reduced.

Negative when performing inversion driving from potential V ₅ at a positive potential V ₁ was, in the conventional inversion driving, as can be seen from Figure 7, the voltage of V ₁ -V ₅ from the source signal line driver circuit to the source signal line There was a need to supply.

On the other hand, in the case where inversion driving is performed using the display device of the present invention, when the inversion driving is performed from the negative potential V ₅ to the positive potential V ₁ , the second capacitor 109 is negatively applied in the period 5. By storing the voltage V ₆ , the potential of the source signal line 101 becomes V ₇ (= V ₅ −V ₆ ) and corresponds to the positive voltage V ₂ stored in the first capacitor element 107 in the period 6. By discharging the electric charge to the source signal line 101, the potential of the source signal line 101 becomes V ₈ (= V ₇ + V ₂ ), and then the potential is increased to the positive potential V ₁ . Therefore, the charge supplied from the source signal line driver circuit 100 to the source signal line 101 when performing inversion driving from a negative potential V ₅ at a positive potential V ₁ was a quantity corresponding to the voltage of V ₁ -V _8.

Here, as can be seen from FIG. 6, since V ₈ > V ₅ , (V ₁ −V ₅ )> (V ₁ −V ₈ ), and the source signal line driver circuit supplies the source signal lines. It can be seen that the amount of charge is smaller when the inversion drive is performed using the display device of the present invention as compared with the conventional inversion drive. Therefore, also when performing inversion driving from the negative potential V ₅ to the positive potential V ₁ , power consumption is reduced by performing inversion driving using the display device of the present invention compared to conventional inversion driving. be able to.

  As described above, the display device of the present invention includes the first switch 106, the second switch 108, the first capacitor element 107, and the second capacitor element 109. By performing the operation in the period 6, the fluctuation width of the potential of the video signal input to the source signal line when performing inversion driving can be reduced. Therefore, power consumption can be reduced.

  In this embodiment, a specific structure of a display device embodying the present invention will be described with reference to FIG.

FIG. 13 shows a schematic diagram of an example of a display device of the present invention. The display device of the present invention includes a pixel portion 11, a first drive circuit 12, and a second drive circuit 13. The pixel unit 11 includes a plurality of pixels 15, and each pixel 15 includes a transistor 73, a capacitor element 75, and a liquid crystal element 74. The first driving circuit 12 is a source signal line driving circuit, and a video signal is output from the first driving circuit 12 to the source signal lines S _{1 to} S _m . The second driving circuit 13 is a gate signal line driving circuit, and scanning signals are output from the second driving circuit 13 to the gate signal lines G _{1 to} G _n . The first driver circuit 12 and the second driver circuit 13 may be provided on the same substrate as the substrate on which the pixel portion 11 is formed, or on a different substrate from the substrate on which the pixel portion 11 is formed. It may be provided. Note that if the first driver circuit 12 and the second driver circuit 13 are formed of thin film transistors, the first driver circuit 12 and the second driver circuit 13 are formed on the same substrate as the substrate on which the pixel portion 11 is formed. Can be provided.

  In the region 20, one terminal of the first switch 16 and one terminal of the second switch 18 are electrically connected in parallel to each source signal line. The first switch 16 and the second switch 18 are formed of transistors such as thin film transistors, for example.

  FIG. 14 shows the case where the first switch 16 and the second switch 18 are formed of transistors. 14 is different from FIG. 13 only in that the first switch 16 and the second switch 18 are transistors, and the first transistor 26 and the second transistor 28 are used. Therefore, the other parts are denoted by the same reference numerals as in FIG.

  Further, FIG. 15 shows the case where the first switch 16 and the second switch 18 are configured by complementary circuits (CMOS circuits) of an N-channel transistor and a P-channel transistor. FIG. 15 differs from FIG. 13 only in that the first switch 16 and the second switch 18 are composed of CMOS circuits, and the first CMOS circuit 36 and the second CMOS circuit 38 are used. Therefore, the other parts are denoted by the same reference numerals as in FIG.

  The other terminal of the first switch 16 is electrically connected to the first electrode of the first capacitive element 17 for storing positive charges, and the other terminal of the second switch 18 is negatively connected. The first electrode of the second capacitor element 19 for storing electric charge is electrically connected. 13 to 15, the second electrodes of the first capacitor element 17 electrically connected to each source signal line are all electrically connected to the same wiring and electrically connected to each source signal line. Although the second electrode of the second capacitor element 19 connected to is also all electrically connected to the same wiring, it is not limited to this. The second electrode of the first capacitor element 17 and the second electrode of the second capacitor element 19 may be kept at a constant potential. Therefore, the second electrodes of the first capacitor element 17 and the second capacitor element 19 may be grounded.

The third drive circuit 14 controls conduction (on) and non-conduction (off) of the first switch 16 and the second switch 18. Note that the third drive circuit 14 that controls the first switch 16 and the second switch 18 may be provided on the same substrate as the substrate on which the pixel portion 11 is formed, or the pixel portion 11. Alternatively, a signal for controlling the first switch 16 and the second switch 18 may be input from the outside of the substrate on which the pixel portion is formed. Note that if the third driver circuit 14 is formed using a thin film transistor, the third driver circuit 14 can be provided over the same substrate as the substrate over which the pixel portion 11 is formed. Although the case where the first switch 16 and the second switch 18 are controlled by the same drive circuit is shown here, the first switch 16 and the second switch 18 are different drive circuits. You may make it control.

  In FIG. 13, in the region 20 between the first driver circuit (source signal line driver circuit) 12 and the pixel portion 11, the first capacitor element 17 is connected to the source signal line via the first switch 16. Although the case where the second capacitor element 19 is electrically connected and the source signal line is electrically connected via the second switch 18 is shown, the present invention is not limited to this case.

  As shown in FIG. 16, the region near the end of the source signal line opposite to the first drive circuit (source signal line drive circuit) 12 (opposite the first drive circuit 12 via the pixel portion 11). In the region 21, the first capacitor 17 is electrically connected to the source signal line via the first switch 16, and the second capacitor 19 is electrically connected to the source signal line via the second switch 18. May be connected to each other. In this case, the region near the end of the source signal line opposite to the first drive circuit (source signal line drive circuit) 12 (region facing the first drive circuit 12 through the pixel portion 11) 21 is formed. Since no other circuit is provided, the capacitor can be formed large (the electrode area can be increased). Therefore, since the amount of charge that can be stored in the capacitor can be increased, the charge output from the source signal line driver circuit can be obtained by holding a large amount of charge in the capacitor and using the held charge for inversion driving. It is possible to drive efficiently with a reduced amount of power.

  In addition, as shown in FIG. 17, in the region 22 between the first drive circuit (source signal line drive circuit) 12 and the pixel portion 11, the first capacitor 17 is controlled by the drive circuit 23. 1 is electrically connected to the source signal line through the switch 16, and is near the end of the source signal line on the side opposite to the first drive circuit (source signal line drive circuit) 12 (via the pixel portion 11. Even if the second capacitor element 19 is electrically connected to the source signal line via the second switch 18 controlled by the drive circuit 24 in the region 25 facing the first drive circuit 12). Good.

  In FIG. 17, the positions of the first switch 16 and the second switch 18, and the first capacitor element 17 and the second capacitor element 19 may be switched. That is, in the region 22, the second capacitor element 19 is electrically connected to the source signal line via the second switch 18, and in the region 25, the first capacitor element 17 is connected via the first switch 16. It may be electrically connected to the source signal line.

  In this embodiment, a driving method when the present invention is applied to gate line inversion driving will be described.

A display pattern diagram of gate line inversion driving is shown in FIG. In addition, the display pattern diagram shown in FIG. 9 shows a case of a model screen of display pixels 3 rows × 4 columns as an example for simplification. In the following, the driving method will be described by taking the case of display pixels 3 rows × 4 columns as an example in order to simplify the description.

  In the gate line inversion drive, as shown in FIG. 9, a video signal is applied to each pixel so that adjacent gate signal lines have opposite polarities. That is, every time one gate signal line is written, the polarity of the video signal written to the source signal line is reversed. In the (N + 1) th frame, a video signal having a polarity opposite to that of the Nth frame is applied to each pixel. That is, the polarity of the video signal applied to each pixel is different for each frame. N is a natural number of 1 or more.

FIG. 18 shows a timing chart when the present invention is applied to the gate line inversion driving method. A driving method when the present invention is applied to the gate line inversion driving method will be described with reference to FIG. Note that those figures, which shows a change in potential at any one source signal line S _x of among the source signal line S ₁ to S _m that indicates the change in the potential of the source signal line in the timing chart of FIG. 18 In the following description, the source signal line _Sx will be described. Note that x is 1 ≦ x ≦ m.

First, in the period 1, the first switch and the second switch are turned off. Then, a video signal having a positive potential V ₁ is input from the first driving circuit (source signal line driving circuit) 12 to the source signal line S _x . Since the first switch is electrically connected to the source signal line S _x, the second switch is off, the potential of the source signal line S _x becomes V _1.

In period 1, an on signal is input to the gate signal line in the first row. Then, the thin film transistor included in the pixel electrically connected to the gate signal line in the first row is turned on, and the source signal line S ₁ to each pixel electrically connected to the gate signal line in the first row is turned on. a video signal is inputted from the signal line S _m. Therefore, in the first row of pixels is electrically connected to the source signal line S _x, positive potential V ₁ is written.

In period 2, the first switch is turned on. Then, since the first switch is turned on, the first capacitor element is brought into conduction with the source signal line _Sx . Then, will gradually accumulate positive charges in the first capacitor element, the first capacitor positive voltage V ₂ is stored, the potential of the source signal line S _x becomes V _3. Here, it is assumed that V ₁ = V ₂ + V ₃ .

In the period 3, the first switch is turned off and the second switch is turned on. Then, when the first switch is turned off, the first capacitor element is brought out of conduction with the source signal line _Sx, and the positive voltage V ₂ stored in the first capacitor element in the period ₂ is It remains in the state stored in one capacitor element. In addition, when the second switch is turned on, the second capacitor element is brought into conduction with the source signal line _Sx, and corresponds to the negative voltage V ₆ previously stored in the second capacitor element. The electric charge is discharged to the source signal line _Sx . By discharging the charges, the potential of the source signal line S _x becomes V _4. In FIG. 18, but V ₄ indicates the case where become common potential, not necessarily V ₄ becomes the common potential. In FIG. 18, since the case where | V ₃ | = | V ₆ | is described as an example, V ₄ is equal to the common potential. However, the present invention is not limited to this case.

In the period 4, the second switch is turned off. Then, a video signal having a negative potential V ₅ is input from the first driving circuit (source signal line driving circuit) 12 to the source signal line S _x . Then, the first and second switches for being turned off, the potential of the source signal line S _x becomes V _5.

Further, in the period 4, and inputs the second row on signal to the gate signal line G ₂ in. Then, the thin film transistor is turned on with the pixel to the gate signal line G ₂ in the second row are electrically connected, the second line source signal to each pixel is electrically connected to the gate signal line G ₂ in Video signals are input from the signal lines of the lines S _{1 to} S _m . Therefore, in the second row of pixels is electrically connected to the source signal line S _x, negative potential V ₁ is inputted.

In a period 5, the second switch is turned on. Then, since the second switch is turned on, the second capacitor element is brought into conduction with the source signal line _Sx . Then, negative charges are gradually accumulated in the second capacitor element, the negative voltage V ₆ is stored in the second capacitor element, and the potential of the source signal line S _x becomes V ₇ . Here, it is assumed that V ₅ = V ₆ + V ₇ .

In the period 6, the first switch is turned on and the second switch is turned off. Then, when the second switch is turned off, the second capacitor element is brought out of conduction with the source signal line _Sx, and the negative voltage V ₆ stored in the second capacitor element in the period 5 is the second voltage element. It remains in the state stored in the second capacitive element. In addition, when the first switch is turned on, the first capacitor element is brought into conduction with the source signal line _Sx, and corresponds to the positive voltage V ₂ stored in the first capacitor element in the period 2. The electric charge is discharged to the source signal line _Sx . By discharging the charges, the potential of the source signal line S _x becomes V _8. In FIG. 18, but V ₈ indicates the case where become common potential need not necessarily V ₈ is common potential. In FIG. 18, since the case where | V ₂ | = | V ₇ | is described as an example, V ₈ is equal to the common potential. However, the present invention is not limited to this case.

In the period 7, the first switch and the second switch are turned off. Then, a video signal having a positive potential V ₁ is input from the first driving circuit (source signal line driving circuit) 12 to the source signal line S _x . Since the first switch, the second switch is off, the potential of the source signal line becomes V _1.

In a period 7, an ON signal is input to the gate signal line G ₃ in the third row. Then, the thin film transistor is turned on with the pixel to the gate signal line G ₃ of the third row are electrically connected, a source signal to each pixel is electrically connected to the gate signal line G ₃ in the third row Video signals are input from the signal lines of the lines S _{1 to} S _m . Therefore, in the third row of pixels that are electrically connected to the source signal line S _x, positive potential V ₁ is written.

In period 8, the first switch is turned on. Then, since the first switch is turned on, the first capacitor element is brought into conduction with the source signal line _Sx . Then, will gradually accumulate positive charges in the first capacitor element, the first capacitor positive voltage V ₂ is stored, the potential of the source signal line S _x becomes V _3.

In the period 9, the first switch is turned off and the second switch is turned on. Then, when the first switch is turned off, the first capacitor element is brought out of conduction with the source signal line _Sx, and the positive voltage V ₂ stored in the first capacitor element in the period 8 is It remains in the state stored in one capacitor element. In addition, when the second switch is turned on, the second capacitor element is brought into conduction with the source signal line _Sx, and the negative voltage V ₆ stored in the second capacitor element in the period 5 is set. Corresponding charges are discharged to the source signal line _Sx . By discharging the charges, the potential of the source signal line S _x becomes V _4.

  By performing the operations from the period 1 to the period 9 described above, the writing of one frame is completed.

  Note that the on / off operation of the first switch and the second switch in the periods 7, 8, and 9 is similar to the on / off operation of the first switch and the second switch in the period 1, the period 2, and the period 3. It is. Therefore, when attention is paid only to the potential change of the source signal line, the potential changes in the periods 7, 8, and 9 are the same as those in the periods 1, 2, and 3, respectively.

  Then, video signals are written to the pixels in the first row in period 1, video signals are written to the pixels in second row in period 4, and pixels in the third row are written in period 7. As can be seen from the writing of the video signal, the period combining the period 2, the period 3 and the period 4, and the period combining the period 5, the period 6 and the period 7 correspond to one line period.

  In the above description, the case of 3 rows × 4 columns of display pixels n rows × m columns has been described for the sake of simplicity. However, the present invention is not limited to the case of n = 3, m = 4. Similar driving can be performed in other cases.

  When attention is paid to the change in the potential of the source signal line, the periods 1 to 6 are one cycle. That is, the period 1 to the period 6 are one cycle of inversion driving. Therefore, in the case of expanding to n rows × m columns, the potential change of the source signal line may be repeatedly performed in the period 1 to period 6 as one cycle when writing up to the n-th row.

  As described above, the gate line inversion driving to which the present invention is applied is input to the source signal line during the inversion driving because of the operations in the periods 2 and 3 and the operations in the periods 5 and 6. The amplitude of the potential of the video signal to be reduced can be reduced. Therefore, power consumption can be reduced.

  In order to implement the driving method described in this embodiment, for example, the display device described in Embodiment 1 may be used.

  In this embodiment, a driving method when the present invention is applied to source line inversion driving will be described.

  A display pattern diagram of source line inversion driving is shown in FIG. Note that the display pattern diagram shown in FIG. 10 shows an example of a model screen of display pixels 3 rows × 4 columns for the sake of simplicity.

  In the source line inversion drive, as shown in FIG. 10, a video signal is applied to each pixel so that adjacent source signal lines have opposite polarities. In the (N + 1) th frame, a video signal having a polarity opposite to that of the Nth frame is applied to each pixel. That is, the polarity of the video signal applied to each pixel is different for each frame.

FIG. 19 shows a timing chart when the present invention is applied to the source line inversion driving method. A driving method when the present invention is applied to the source line inversion driving method will be described with reference to FIG. Note that those figures, which shows a change in potential at any one source signal line S _x of among the source signal line S ₁ to S _m that indicates the change in the potential of the source signal line in the timing chart of FIG. 19 In the following description, the source signal line _Sx will be described.

First, in the period 1, the first switch and the second switch are turned off. Then, a video signal having a positive potential V ₁ is input from the first driving circuit (source signal line driving circuit) 12 to the source signal line S _x . Since the first switch is electrically connected to the source signal line S _x, the second switch is off, the potential of the source signal line S _x becomes V _1.

Then, enter an ON signal to the first row of the gate signal line G _1. Then, the thin film transistor included in the pixel electrically connected to the gate signal line in the first row is turned on, and the source signal line S is connected to each pixel electrically connected to the gate signal line G1 in the _first row. video signals from the signal lines ₁ to S _m is entered. Therefore, in the first row of pixels is electrically connected to the source signal line S _x, positive potential V ₁ is inputted. Then, the first row After completing the writing of the video signal to the gate signal line G _1, and then enter the second row on signal to the gate signal line G ₂ of, to the second row of pixels Write. In this way, writing is performed up to the nth row.

  When the writing of the video signal having the positive potential from the first to the nth row is completed in the period 1, the period 2 is started.

In period 2, first, the first switch is turned on. Then, since the first switch is turned on, the first capacitor element is brought into conduction with the source signal line _Sx . Then, will gradually accumulate positive charges in the first capacitor element, the first capacitor positive voltage V ₂ is stored, the potential of the source signal line S _x becomes V _3. Here, it is assumed that V ₁ = V ₂ + V ₃ .

In the period 3, the first switch is turned off and the second switch is turned on. Then, when the first switch is turned off, the first capacitor element is brought out of conduction with the source signal line _Sx, and the positive voltage V ₂ stored in the first capacitor element in the period ₂ is It remains in the state stored in one capacitor element. In addition, when the second switch is turned on, the second capacitor element is brought into conduction with the source signal line _Sx, and corresponds to the negative voltage V ₆ previously stored in the second capacitor element. The electric charge is discharged to the source signal line _Sx . By discharging the charges, the potential of the source signal line S _x becomes V _4. In FIG. 19, but V ₄ indicates the case where become common potential, not necessarily V ₄ becomes the common potential. In FIG. 19, since the case where | V ₃ | = | V ₆ | is described as an example, V ₄ is equal to the common potential. However, the present invention is not limited to this case.

In the period 4, the second switch is turned off. Then, a video signal having a negative potential V ₅ is input from the first driving circuit (source signal line driving circuit) 12 to the source signal line S _x . Then, the first and second switches for being turned off, the potential of the source signal line S _x becomes V _5.

Then, enter an ON signal to the first row of the gate signal line G _1. Then, the thin film transistor included in the pixel which is electrically connected to the first row of the gate signal line G ₁ is turned on, a source signal to each pixel which is electrically connected to the first row of the gate signal lines G ₁ Video signals are input from the signal lines of the lines S _{1 to} S _m . Therefore, in the first row of pixels is electrically connected to the source signal line S _x, positive potential V ₁ is inputted. Then, the first row After completing the writing of the video signal to the gate signal line G _1, and then enter the second row on signal to the gate signal line G ₂ of, to the second row of pixels Write. In this manner, writing up to the nth row is performed.

  When the writing of the video signal having the negative potential from the first to the nth row is completed in the period 4, the period 5 is started.

In a period 5, the second switch is turned on. Then, since the second switch is turned on, the second capacitor element is brought into conduction with the source signal line _Sx . Then, negative charges are gradually accumulated in the second capacitor element, the negative voltage V ₆ is stored in the second capacitor element, and the potential of the source signal line S _x becomes V ₇ . Here, it is assumed that V ₅ = V ₆ + V ₇ .

In the period 6, the first switch is turned on and the second switch is turned off. Then, when the second switch is turned off, the second capacitor element is brought out of conduction with the source signal line _Sx, and the negative voltage V ₆ stored in the second capacitor element in the period 5 is the second voltage element. It remains in the state stored in the second capacitive element. In addition, when the first switch is turned on, the first capacitor element is brought into conduction with the source signal line _Sx and corresponds to the positive voltage V ₂ stored in the first capacitor element in the period 2. To be discharged to the source signal line _Sx . By discharging the charges, the potential of the source signal line S _x becomes V _8. In FIG. 19, but V ₈ indicates the case where become common potential need not necessarily V ₈ is common potential. In FIG. 19, since the case where | V ₂ | = | V ₇ | is described as an example, V ₈ is equal to the common potential. However, the present invention is not limited to this case.

  Period 1 to period 6 described above is one cycle. By repeating this cycle, source line inversion driving can be performed. FIG. 19 shows the operation in the period from period 1 of the a cycle to period 3 of the next cycle (a + 1 cycle). Since one cycle of period 1 to period 6 is repeatedly performed, the operation in period 1 to period 3 of the a + 1 cycle is the same as the operation in period 1 to period 3 of the a cycle. Note that a is a natural number of 1 or more.

  Assuming that the period 1 of the a cycle belongs to the N frame, the periods 2 to 4 of the a cycle correspond to the N + 1 frame, and the period 1 of the a cycle 5 to the period 1 of the a + 1 cycle corresponds to the N + 2 frame. . Then, the period 2 to the period 3 of the (a + 1) th cycle belong to the N + 3 frame.

  As described above, the source line inversion driving to which the present invention is applied is input to the source signal line during the inversion driving because of the operations in the period 2 and the period 3 and the operations in the period 5 and the period 6. The amplitude of the potential of the video signal to be reduced can be reduced. Therefore, power consumption can be reduced.

  In the case of performing source line inversion driving as in the present embodiment, when controlling the first switch and the second switch electrically connected to each source signal line, an even number as shown in FIG. Control may be performed by electrically connecting columns and odd columns to the same wiring.

  In this embodiment, a driving method when the present invention is applied to dot inversion driving will be described.

  FIG. 11 shows a display pattern diagram of dot inversion driving. The display pattern diagram shown in FIG. 11 shows an example of a model screen of display pixels 3 rows × 4 columns for the sake of simplicity.

  In dot inversion driving, as shown in FIG. 11, a video signal is applied to each pixel so that adjacent pixels in the vertical and horizontal directions have opposite polarities. A video signal is applied to each pixel so that adjacent gate signal lines have opposite polarities. In the (N + 1) th frame, a video signal having a polarity opposite to that of the Nth frame is applied to each pixel. That is, the polarity of the video signal applied to each pixel is different for each frame.

  The dot inversion driving can be performed by combining the gate line inversion driving described in the second embodiment and the source line inversion driving described in the third embodiment.

  Even in the dot inversion driving to which the present invention is applied, as described in the second and third embodiments, the operations in the period 2 and the period 3 and the operations in the period 5 and the period 6 exist, so In addition, the amplitude of the potential of the video signal input to the source signal line can be reduced. Therefore, power consumption can be reduced.

  Note that in the dot inversion drive, pixels to which a positive polarity signal is input and pixels to which a negative polarity signal is input are mixed uniformly, and therefore, compared to source line inversion driving and gate line inversion driving. Flickering can be made difficult to occur.

  In this embodiment, a case where the present invention is applied to a driving method in which gate line inversion driving and common inversion driving are combined will be described.

FIG. 21 shows a timing chart when the present invention is applied to a driving method combining gate line inversion driving and common inversion driving. A case where the present invention is applied to a driving method in which gate line inversion driving and common inversion driving are combined will be described with reference to FIG. Note that those figures, which shows a change in potential at any one source signal line S _x of among the source signal line S ₁ to S _m that indicates the change in the potential of the source signal line in the timing chart of FIG. 21 In the following description, the source signal line _Sx will be described. Further, it is assumed that the reference potential as V _0.

First, in the period 1, the first switch and the second switch are turned off. Then, a video signal having a positive potential V ₁ is input from the first driving circuit (source signal line driving circuit) 12 to the source signal line S _x . Since the first switch is electrically connected to the source signal line S _x, the second switch is off, the potential of the source signal line S _x becomes V _1.

In period 1, the polarity of the common potential is also inverted in synchronization with the polarity inversion of the video signal written to the source signal line. At this time, the polarity of the common potential is set to be opposite to the polarity of the video signal. That is, when the video signal is a positive potential, the common potential is set to a negative potential. In period 1, the potential of the video signal to be written to the source signal line is because it is a positive potential V _1, so that the common potential becomes the negative potential V _15. When | V ₁ | = | V ₁₅ | is set, the potential of the video signal written to the source signal line is halved as compared with the case of driving only by gate line inversion driving. Here, V ₁₅ is set so that | V ₁ | = | V ₁₅ |. However, such a value is not necessarily required.

In period 1, an on signal is input to the gate signal line in the first row. Then, the thin film transistor included in the pixel electrically connected to the gate signal line G1 in the first row is turned on, and the source signal line S ₁ is connected to each pixel electrically connected to the gate signal line in the first row. a video signal is inputted from the signal line to S _m. Therefore, in the first row of pixels is electrically connected to the source signal line S _x, positive potential V ₁ is inputted.

In period 2, the first switch is turned on. Then, since the first switch is turned on, the first capacitor element is brought into conduction with the source signal line _Sx . Then, will gradually accumulate positive charges in the first capacitor element, the first capacitor positive voltage V ₂ is stored, the potential of the source signal line S _x becomes V _3. Here, it is assumed that V ₁ = V ₂ + V ₃ .

Further, in the period 2, the common potential to the negative potential _{V 17.} Here, the potential of V ₁₇ is set so that | V ₁₇ | = | V ₃ |. However, such a value is not necessarily required. For example, in the period 2, the same common potential as that in the period 1 may be maintained, or in the period 2, the common potential may be set as the reference potential V ₀ .

In the period 3, the first switch is turned off and the second switch is turned on. Then, when the first switch is turned off, the first capacitor element is brought out of conduction with the source signal line _Sx, and the positive voltage V ₂ stored in the first capacitor element in the period ₂ is It remains in the state stored in one capacitor element. In addition, when the second switch is turned on, the second capacitor element is brought into conduction with the source signal line _Sx, and corresponds to the negative voltage V ₆ previously stored in the second capacitor element. The electric charge is discharged to the source signal line _Sx . By discharging the charges, the potential of the source signal line S _x becomes V _4. Incidentally, in FIG. 21 shows a case _{where V 4} is the reference potential _{V 0,} it is not always necessary _{to V 4} becomes the reference potential _{V 0.} In FIG. 21, since the case where | V ₃ | = | V ₆ | is described as an example, V ₄ is equal to the reference potential V ₀ , but the present invention is not limited to this case.

Further, in the period 3, the common potential as the reference potential V _0.

Note that FIG. 21 illustrates the case where the common potential is changed in each of the two periods, the period 2 and the period 3, but this is not necessarily required. For example, it may also be allowed to maintain the same common potential as the period 1 to period 3, the reference potential V ₀ which the common potential even in the period 3 so as to be equal to the common potential to the reference potential V ₀ which in the period 2 It may be kept at Further, the same common potential as that in the period 1 may be maintained in the period 2, and the reference potential V ₀ may be set in the period 3. Further, as shown in FIG. 22, in the period 2, the common potential may be the common potential V ₁₁ input in the period 4, and the same potential as that in the period 2 may be maintained until the period 4. Note that less power is consumed when the number of times of changing the common potential is smaller. Therefore, the method of changing the common potential shown in FIG. 22 can suppress power consumption lower than the method of changing the common potential shown in FIG.

In the period 4, the second switch is turned off. Then, a video signal having a negative potential V ₅ is input from the first driving circuit (source signal line driving circuit) 12 to the source signal line S _x . Then, the first and second switches for being turned off, the potential of the source signal line S _x becomes V _5.

In period 4, the polarity of the common potential is also inverted in synchronization with the polarity inversion of the video signal written to the source signal line. At this time, the polarity of the common potential is set to be opposite to the polarity of the video signal. In the period 4, since the potential of the video signal to be written to the source signal line is a negative potential V _5, the common potential is set to be a positive potential V _11. When | V ₅ | = | V ₁₁ | is set, the potential of the video signal written to the source signal line is halved as compared with the case of driving only by gate line inversion driving. Here, V ₁₁ is set so that | V ₅ | = | V ₁₁ |. However, such a value is not necessarily required.

Further, in the period 4, and inputs the second row on signal to the gate signal line G ₂ in. Then, the thin film transistor is turned on with the pixel to the gate signal line G ₂ in the second row are electrically connected, the second line source signal to each pixel is electrically connected to the gate signal line G ₂ in Video signals are input from the signal lines of the lines S _{1 to} S _m . Therefore, in the second row of pixels is electrically connected to the source signal line S _x, negative potential V ₅ is inputted.

In a period 5, the second switch is turned on. Then, since the second switch is turned on, the second capacitor element is brought into conduction with the source signal line _Sx . Then, negative charges are gradually accumulated in the second capacitor element, the negative voltage V ₆ is stored in the second capacitor element, and the potential of the source signal line S _x becomes V ₇ . Here, it is assumed that V ₅ = V ₆ + V ₇ .

Further, in the period 5, the common potential and positive potential _{V 13.} Here, the potential of V ₁₃ is set so that | V ₁₃ | = | V ₇ |. However, such a value is not necessarily required. For example, in the period 5, the same common potential as that in the period 4 may be maintained, or in the period 5, the common potential may be set as the reference potential V ₀ .

In the period 6, the first switch is turned on and the second switch is turned off. Then, when the second switch is turned off, the second capacitor element is brought out of conduction with the source signal line _Sx, and the negative voltage V ₆ stored in the second capacitor element in the period 5 is the second voltage element. It remains in the state stored in the second capacitive element. In addition, when the first switch is turned on, the first capacitor element is brought into conduction with the source signal line _Sx and corresponds to the positive voltage V ₂ stored in the first capacitor element in the period 2. To be discharged to the source signal line _Sx . By discharging the charges, the potential of the source signal line S _x becomes V _8. Incidentally, in FIG. 21, but V ₈ indicates the case where become common potential need not necessarily V ₈ is common potential. In FIG. 21, since the case where | V ₂ | = | V ₇ | is described as an example, V ₈ is equal to the common potential. However, the present invention is not limited to this case.

Further, in the period 6, the common potential as the reference potential V _0.

Note that FIG. 21 illustrates the case where the common potential is changed in each of the two periods, that is, the period 5 and the period 6, but this is not necessarily required. For example, it may also be allowed to maintain the same common potential as the period 4 to period 6, the reference potential V ₀ which the common potential even in the period 6 so as to be equal to the common potential to the reference potential V ₀ which in the period 5 It may be kept at Further, the same common potential as that in the period 4 may be maintained in the period 5, and the reference potential V ₀ may be set in the period 6. Further, as shown in FIG. 22, in the period 5, the common potential may be the common potential V ₁₅ input in the period 7, and the same potential as that in the period 5 may be maintained until the period 7. Note that less power is consumed when the number of times of changing the common potential is smaller. Therefore, the method of changing the common potential shown in FIG. 22 can suppress power consumption lower than the method of changing the common potential shown in FIG.

In the period 7, the first switch and the second switch are turned off. Then, a video signal having a positive potential V ₁ is input from the first driving circuit (source signal line driving circuit) 12 to the source signal line S _x . Since the first switch and the second switch are off, the potential of the source signal line is V ₁ −V ₈ (= V ₉ ). Note that FIG. 21 shows the case where V ₉ = V ₁ for simplicity of explanation, but V ₉ = V ₁ is not necessarily required.

In period 7, the polarity of the common potential is also inverted in synchronization with the polarity inversion of the video signal written to the source signal line. At this time, the polarity of the common potential is set to be opposite to the polarity of the video signal. In the period 7, the potential of the video signal to be written to the source signal line is because it is a positive potential V _1, so that the common potential becomes the negative potential V _15. When | V ₁ | = | V ₁₅ | is set, the potential of the video signal written to the source signal line is halved as compared with the case of driving only by gate line inversion driving. Here, V ₁₅ is set so that | V ₁ | = | V ₁₅ |. However, such a value is not necessarily required.

In a period 7, an ON signal is input to the gate signal line G ₃ in the third row. Then, the thin film transistor is turned on with the pixel to the gate signal line G ₃ of the third row are electrically connected, a source signal to each pixel is electrically connected to the gate signal line G ₃ in the third row Video signals are input from the signal lines of the lines S _{1 to} S _m . Therefore, in the third row of pixels that are electrically connected to the source signal line S _x, positive potential V ₁ is inputted.

In period 8, the first switch is turned on. Then, since the first switch is turned on, the first capacitor element is brought into conduction with the source signal line _Sx . Then, will gradually accumulate positive charges in the first capacitor element, the first capacitor positive voltage V ₂ is stored, the potential of the source signal line S _x becomes V _10. Here, it is assumed that V ₉ = V ₂ + V ₁₀ . FIG. 21 shows the case where V ₁₀ = V ₃ for simplicity of explanation, but V ₁₀ = V ₃ is not necessarily required.

In the period 9, the first switch is turned off and the second switch is turned on. Then, when the first switch is turned off, the first capacitor element is brought out of conduction with the source signal line _Sx, and the positive voltage V ₂ stored in the first capacitor element in the period 8 is It remains in the state stored in one capacitor element. In addition, when the second switch is turned on, the second capacitor element is brought into conduction with the source signal line _Sx, and the negative voltage V ₆ stored in the second capacitor element in the period 5 is set. Corresponding charges are discharged to the source signal line _Sx . By discharging the charges, the potential of the source signal line _{S x} becomes _{V 11.} Incidentally, in FIG. 21 _{is V 11} indicates the case becomes _{V 4} and the common potential need not necessarily _{V 11} is equal to _{V 4} and the common potential. In FIG. 21, since the case where | V ₁₀ | = | V ₆ | is described as an example, V ₁₁ is equal to the common potential. However, the present invention is not limited to this case.

  Note that the change in the potential of the video signal written to the source signal line and the change in the common potential are performed by repeating the same operation with the periods 1 to 6 as one cycle. Therefore, the method of changing the potential of the video signal written to the source signal line in the periods 7, 8, and 9 in FIG. 21 and the method of changing the common potential are the source signals in the periods 1, 2, and 3, respectively. This is the same as the method of changing the potential of the video signal written to the line and the method of changing the common potential.

  In the above description, for the sake of simplification, the case of the model screen of display pixels 3 rows × 4 columns has been described as an example, so only writing to the pixels in the third row has been described, but n = 3 and m The same can be done for display pixels of n rows × m columns other than = 4.

  In the case where the number of display pixels is n rows × m columns, the same operation as the operation of the video signal potential and the common potential in the periods 1 to 6 may be repeated until the writing of the n-th row is completed. .

  As described above, the driving method combining the gate line inversion driving and the common inversion driving by applying the present invention includes the operations in the period 2 and the period 3 and the operations in the period 5 and the period 6. It is possible to reduce the amplitude of the potential of the video signal input to the source signal line when performing inversion driving. Therefore, power consumption can be reduced.

  In this embodiment, an example of the layout of the first switch and the first capacitor will be described. In this embodiment, the case of the display device of FIG. 15 in which the first switch is constituted by a CMOS circuit will be described as an example.

  FIG. 23A is a top view showing a layout in region A shown in FIG. 23A is a cross-sectional view taken along A-A ′ in FIG. 23A, and FIG. 23C is a cross-sectional view taken along B-B ′ in FIG.

  In FIG. 23, reference numeral 220 denotes an N-channel thin film transistor (N-channel TFT) constituting the first CMOS circuit 36, and reference numeral 221 denotes a P-channel thin film transistor (P-channel TFT) constituting the first CMOS circuit 36. ). FIG. 23 shows a case of a double-gate TFT in which both the N-channel TFT and the P-channel TFT constituting the first switch have two gate electrodes, but the present invention is not limited to this structure. A single-gate TFT having one gate electrode or a TFT having two or more gate electrodes may be used. Further, a general TFT structure such as a TFT having a structure having an offset region or a TFT having a structure having an LDD region may be used.

  In FIG. 23A, a capacitor is formed in a region where the semiconductor film 202 and the second electrode 206c of the capacitor overlap. A region of the semiconductor film 202 that overlaps with the second electrode 206c of the capacitor functions as the first electrode of the capacitor. The second electrode 206c of the capacitor is formed using the same metal film as the gate wirings 206f and 206g. The first gate electrode 206a and the second gate electrode 206b included in the N-channel TFT 220 are extended from the gate wiring 206f. The third gate electrode 206d and the fourth gate electrode 206e of the P-channel TFT 221 are extended from the gate wiring 206g.

  A cross-sectional structure in a region where the N-channel TFT 220 and the capacitor are formed, that is, a cross-sectional structure taken along A-A ′ will be described with reference to FIG. Over the substrate 200, a base film composed of a stacked film of a silicon nitride film 201a and a silicon oxide film 201b is formed, and a semiconductor film 202 is formed over the base film. The semiconductor film includes a first N-type impurity region 205a, a second N-type impurity region 205b, a third N-type impurity region 205c, and between the first N-type impurity region 205a and the second N-type impurity region 205b. The second intrinsic region formed between the second n-type impurity region 205c and the first n-type impurity region 205c is formed. A part of the third N-type impurity region 205c functions as a first electrode of the capacitor.

  A gate insulating film 203 is formed over the semiconductor film 202, and a first gate electrode 206a, a second gate electrode 206b, and a second electrode 206c of the capacitor are formed over the gate insulating film 203. . Note that a capacitor is formed by part of the third N-type impurity region 205c, the gate insulating film 203, and the second electrode 206c of the capacitor.

  An interlayer insulating film 209 is formed over the gate insulating film 203, the first gate electrode 206a, the second gate electrode 206b, and the second electrode 206c of the capacitor, and a source signal line is formed over the interlayer insulating film 209. 210a is formed. The source signal line 210 a is electrically connected to the first N-type impurity region 205 a of the N-channel TFT 220.

  Next, a cross-sectional structure in a region where the P-channel TFT 221 and the capacitor are formed, that is, a cross-sectional structure along B-B ′ will be described with reference to FIG. Over the substrate 200, a base film composed of a stacked film of a silicon nitride film 201a and a silicon oxide film 201b is formed, and a semiconductor film 202 is formed over the base film. The semiconductor film includes the first P-type impurity region 208a, the second P-type impurity region 208b, the third P-type impurity region 208c, the third N-type impurity region 205c, the first P-type impurity region 208a and the first P-type impurity region 208a. A second intrinsic region formed between the second P-type impurity region 208b and a fourth intrinsic region formed between the second P-type impurity region 208b and the third P-type impurity region 208c. is doing. Note that part of the third N-type impurity region 205c functions as the first electrode of the capacitor.

  A gate insulating film 203 is formed over the semiconductor film 202, and a third gate electrode 206d, a fourth gate electrode 206e, and a second electrode 206c of the capacitor are formed over the gate insulating film 203. . Note that a capacitor is formed by part of the third N-type impurity region 205c, the gate insulating film 203, and the second electrode 206c of the capacitor.

  An interlayer insulating film 209 is formed over the gate insulating film 203, the third gate electrode 206d, the fourth gate electrode 206e, and the second electrode 206c of the capacitor, and a source signal line is formed over the interlayer insulating film 209. 210c is formed. The source signal line 210 c is electrically connected to the first P-type impurity region 208 a of the P-channel TFT 221.

  A manufacturing process of the first switch and the first capacitor element laid out in the state described above will be described below with reference to FIGS.

  24 to 26, the left side of the drawing shows a cross-sectional view taken along the line A-A 'of FIG. 23, and the right side of the drawing shows a cross-sectional view taken along the line B'-B of FIG.

  First, as illustrated in FIG. 24A, a base film is formed over the substrate 200. Here, as the base film, a stacked film of the silicon nitride film 201a and the silicon oxide film 201b is formed by a plasma CVD method, a sputtering method, or the like; however, the present invention is not limited to this case. A film containing silicon oxide, a film containing silicon oxynitride, or a film containing silicon nitride oxide may be formed as a single-layer structure, or these films may be stacked as appropriate. Then, a semiconductor film 202 is formed over the silicon oxide film 201b that forms the base film. Here, a silicon film is formed as the semiconductor film 202. The silicon film may be an amorphous silicon film or a crystalline silicon film. Then, a gate insulating film 203 that covers the semiconductor film 202 is formed. The gate insulating film 203 is formed by a single layer or a stack of films containing silicon oxide or silicon nitride by various CVD methods such as a sputtering method and a plasma CVD method. Specifically, a film containing silicon oxide, a film containing silicon oxynitride, or a film containing silicon nitride oxide is formed as a single-layer structure, or these films are stacked as appropriate.

  Next, as shown in FIG. 24B, masks 204a, 204b, and 204c are formed. Then, an impurity having an N-type conductivity is doped into the semiconductor film 202 from above the masks 204a, 204b, 204c and the gate insulating film 203. By this doping, a first N-type impurity region 205a, a second N-type impurity region 205b, and a third N-type impurity region 205c are formed in regions where the masks 204a, 204b, and 204c are not formed.

  Then, as shown in FIG. 25A, a first gate electrode 206a, a second gate electrode 206b, one electrode 206c of a capacitor, a third gate electrode 206d, and a fourth gate electrode 206e are formed. .

  Here, in FIG. 25A, the first gate electrode is set to be equal to the width of the first intrinsic region existing between the first N-type impurity region 205a and the second N-type impurity region 205b. 206a is formed, but the width of the first gate electrode 206a is shorter than the width of the first intrinsic region existing between the first N-type impurity region 205a and the second N-type impurity region 205b. The first gate electrode 206a may be formed so as to be. In that case, an offset region can be formed between the first N-type impurity region 205a and the first intrinsic region and between the first intrinsic region and the second N-type impurity region 205b.

  The second gate electrode 206b is formed so as to be equal to the width of the second intrinsic region existing between the second N-type impurity region 205b and the third N-type impurity region 205c. The second gate electrode 206b has a width shorter than that of the second intrinsic region existing between the second N-type impurity region 205b and the third N-type impurity region 205c. 206b may be formed. In that case, an offset region can be formed between the second N-type impurity region 205b and the second intrinsic region and between the second intrinsic region and the third N-type impurity region 205c.

  Next, as illustrated in FIG. 25B, a region to be a P-channel thin film transistor (P-channel TFT) is exposed, and a mask 207 is formed in the other region. Then, an impurity having P-type conductivity is doped into the semiconductor film 202 from above the mask 207 and the gate insulating film 203. By this doping, the first P-type impurity region 208a, the second P-type impurity region 208b, and the third P-type impurity region are formed in the region where the mask 207, the third gate electrode 206d, and the fourth gate electrode 206e are not formed. A type impurity region 208c is formed.

  Then, as shown in FIG. 26, over the gate insulating film 203, the first gate electrode 206a, the second gate electrode 206b, one electrode 206c of the capacitor, the third gate electrode 206d, and the fourth gate electrode 206e. Then, an interlayer insulating film 209 is formed. Then, source signal lines 210 a and 210 c and an electrode 210 b are formed on the interlayer insulating film 209.

  The source signal line 210a is electrically connected to the first N-type impurity region 205a, and the source signal line 210c is electrically connected to the third P-type impurity region 208c. The electrode 210b electrically connects the third N-type impurity region 205c and the first P-type impurity region 208a.

  As described above, an N-channel thin film transistor (N-channel TFT) and a P-channel thin film transistor (P-channel TFT) that form the first switch and a capacitor can be formed.

  In the manufacturing process described above, only the first CMOS circuit 36 and the first capacitor 17 have been described. However, the second CMOS circuit 38 and the second capacitor 19 also include the first CMOS circuit 36 and the first capacitor 19. It may be manufactured in the same manner as the capacitor element 17 in FIG.

  In the above description, the case of a liquid crystal display device has been described. However, the present invention can also be implemented in the case of an EL display device.

  In an EL display device, in order to extend the life of a light emitting element, particularly an organic EL element, the light emitting element may be driven in an inverted manner. The present invention can also be applied to that case.

  However, since the inversion driving of the light emitting element has a longer polarity inversion period of the video signal than the inversion driving in the liquid crystal display device, the frequency of inversion is low. Therefore, the effect of lower power consumption can be obtained by applying the present invention to the inversion driving of the liquid crystal display device than applying the present invention to the inversion driving of the light emitting element.

  Further, the present invention can be implemented even when the inorganic EL is AC driven.

  Electronic devices using the display device of the present invention will be described with reference to FIG. Examples of the electronic device of the present invention include a camera such as a video camera and a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio component, MP3 player, etc.), a computer, a game device, and a mobile phone. An information terminal (mobile computer, mobile phone, portable game machine, electronic dictionary, electronic book, etc.), an image playback device provided with a recording medium (specifically, a digital versatile disc (DVD), etc.) And a device provided with a display capable of displaying an image).

  FIG. 27A shows a display device such as a personal computer monitor or a television receiver. A housing 2001, a support base 2002, a display portion 2003, and the like are included. By using the present invention, a display device with reduced power consumption can be manufactured.

  FIG. 27B illustrates a mobile phone that can be viewed on television, which includes a main body 2101, a housing 2102, a display portion 2103, an audio input portion 2104, an audio output portion 2105, operation keys 2106, an antenna 2108, and the like. By using the present invention, a mobile phone with reduced power consumption can be manufactured.

  FIG. 27C illustrates a computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. By using the present invention, a computer with reduced power consumption can be manufactured. FIG. 27C illustrates a notebook computer, but the present invention can also be applied to, for example, a monitor-integrated desktop computer.

  FIG. 27D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. By using the present invention, a mobile computer with reduced power consumption can be manufactured.

  FIG. 27E illustrates a portable game machine including a housing 2401, a display portion 2402, a speaker 2403, operation keys 2404, a recording medium insertion portion 2405, and the like. By using the present invention, a game machine with reduced power consumption can be manufactured.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

  This example can be combined with any of the embodiment mode and Examples 1 to 5 as appropriate.

The figure shown about the display apparatus of this invention The figure shown about the display apparatus of this invention The figure shown about the display apparatus of this invention The figure shown about the display apparatus of this invention The figure shown about the display apparatus of this invention FIG. 11 shows a change in potential of a source signal line in a display device of the present invention. The figure which shows about the change of the electric potential of the source signal line in the conventional inversion drive Diagram showing display pattern of frame inversion drive The figure shown about the display pattern of gate line inversion drive The figure which shows the display pattern of source line inversion drive Diagram showing dot inversion drive display pattern FIG. 6 illustrates a capacitor transistor. The figure shown about the example of the display apparatus of this invention The figure shown about the example of the display apparatus of this invention The figure shown about the example of the display apparatus of this invention The figure shown about the example of the display apparatus of this invention The figure shown about the example of the display apparatus of this invention The figure explaining the drive method at the time of applying this invention to gate line inversion drive The figure explaining the drive method at the time of applying this invention to source line inversion drive The figure which shows about the control method of the 1st and 2nd switch at the time of applying this invention to a source line inversion drive The figure explaining the drive method at the time of combining gate line inversion drive with common inversion drive The figure explaining the drive method at the time of combining gate line inversion drive with common inversion drive The figure shown about the layout figure of a 1st switch and a 1st capacitive element FIG. 5 shows a manufacturing process of a first switch and a first capacitor element. FIG. 5 shows a manufacturing process of a first switch and a first capacitor element. FIG. 5 shows a manufacturing process of a first switch and a first capacitor element. FIG. 11 is a diagram showing an electronic device to which the display device of the invention is applied

Explanation of symbols

11 pixel portion 12 first drive circuit 13 second drive circuit 14 third drive circuit 15 pixel 16 first switch 17 first capacitive element 18 second switch 19 second capacitive element 20 region 21 region 22 Region 25 Region 26 First transistor 28 Second transistor 36 First CMOS circuit 38 Second CMOS circuit 73 Transistor 74 Liquid crystal element 75 Capacitance element 100 Source signal line driver circuit 101 Source signal line 102 Pixel 106 First switch 107 first capacitor element 108 second switch 109 second capacitor element 110 pixel portion 111 region 117 first capacitor transistor 119 second capacitor transistor 127 first capacitor transistor 129 second capacitor transistor 200 Substrate 201 Base film 202 Semiconductor film 203 Gate insulating film 207 Disk 209 interlayer insulating film 220 N-channel type TFT
221 P-channel TFT
601 Semiconductor film 602 Region 603 Gate insulating film 604 Gate electrode 2001 Housing 2002 Support base 2003 Display portion 201a Silicon nitride film 201b Silicon oxide film 204a Mask 204b Mask 204c Mask 205a First N-type impurity region 205b Second N-type impurity Region 205c third N-type impurity region 206a first gate electrode 206b second gate electrode 206c electrode 206d third gate electrode 206e fourth gate electrode 208a first P-type impurity region 208b second P-type impurity Region 208c Third P-type impurity region 2101 Main body 2102 Case 2103 Display portion 2104 Audio input portion 2105 Audio output portion 2106 Operation key 2108 Antenna 210a Source signal line 210b Electrode 210c Source signal line 2201 Main body 2202 Case 2203 Radical 113 2204 keyboard 2205 an external connection port 2206 pointing mouse 2301 body 2302 display unit 2303 switches 2304 operation keys 2305 infrared port 2401 housing 2402 display unit 2403 speaker 2404 operating keys 2405 a recording medium insertion portion

Claims (7)

Wiring for video signal input,
A first capacitive element;
A second capacitive element;
A first switch for controlling a conductive state and a non-conductive state between the wiring and the first capacitor element;
A second switch for controlling a conductive state and a non-conductive state between the wiring and the second capacitor element;
And a pixel to which the video signal is input from the wiring. Wiring for video signal input,
A first capacitive element that stores a positive charge;
A second capacitive element that stores a negative charge;
A first switch for controlling a conductive state and a non-conductive state between the wiring and the first capacitor element;
A second switch for controlling a conductive state and a non-conductive state between the wiring and the second capacitor element;
And a pixel to which the video signal is input from the wiring. Wiring for video signal input,
A first switch and a second switch having one terminal electrically connected to the wiring;
A first capacitive element having one electrode electrically connected to the other terminal of the first switch;
A second capacitive element having one electrode electrically connected to the other terminal of the second switch;
A pixel to which the video signal is input from the wiring;
A display device comprising: Wiring for video signal input,
A first switch and a second switch having one terminal electrically connected to the wiring;
A first capacitive element having one electrode electrically connected to the other terminal of the first switch and storing positive charge;
A second capacitor element having one electrode electrically connected to the other terminal of the second switch and storing negative charge;
A pixel to which the video signal is input from the wiring;
A display device comprising: In any one of Claims 1 thru | or 4,
The display device is a liquid crystal display device. In any one of Claims 1 thru | or 5,
The display device, wherein the first switch and the second switch are formed of thin film transistors.   An electronic apparatus using the display device according to any one of claims 1 to 6.

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